Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6812687 |
1 |
|
|
T21 |
191 |
|
T22 |
1088 |
|
T23 |
28 |
| auto[1] |
4622686 |
1 |
|
|
T21 |
398 |
|
T22 |
770 |
|
T25 |
53 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10843662 |
1 |
|
|
T21 |
549 |
|
T22 |
1692 |
|
T23 |
28 |
| auto[1] |
591711 |
1 |
|
|
T21 |
40 |
|
T22 |
166 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6806583 |
1 |
|
|
T21 |
367 |
|
T22 |
970 |
|
T23 |
28 |
| auto[1] |
4628790 |
1 |
|
|
T21 |
222 |
|
T22 |
888 |
|
T25 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2016166 |
1 |
|
|
T21 |
75 |
|
T22 |
491 |
|
T25 |
21 |
| auto[1] |
auto[0] |
auto[1] |
294678 |
1 |
|
|
T21 |
16 |
|
T22 |
116 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2020913 |
1 |
|
|
T21 |
107 |
|
T22 |
231 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[1] |
297033 |
1 |
|
|
T21 |
24 |
|
T22 |
50 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |