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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 936
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T761 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1770841366 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:19 PM PDT 24 100660893 ps
T106 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4259756510 Aug 01 05:14:30 PM PDT 24 Aug 01 05:14:31 PM PDT 24 62800204 ps
T762 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1227290540 Aug 01 05:15:13 PM PDT 24 Aug 01 05:15:14 PM PDT 24 215532265 ps
T763 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1673885453 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:47 PM PDT 24 53193952 ps
T764 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2580880313 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:46 PM PDT 24 74216640 ps
T765 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3923511221 Aug 01 05:15:02 PM PDT 24 Aug 01 05:15:03 PM PDT 24 63279250 ps
T766 /workspace/coverage/cover_reg_top/27.gpio_intr_test.15358006 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:18 PM PDT 24 26708349 ps
T41 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1466840676 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 277018686 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3847988913 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:45 PM PDT 24 37692737 ps
T768 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.333119999 Aug 01 05:14:50 PM PDT 24 Aug 01 05:14:51 PM PDT 24 69372797 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.6709263 Aug 01 05:14:34 PM PDT 24 Aug 01 05:14:35 PM PDT 24 41797908 ps
T769 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3511797548 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 42222913 ps
T770 /workspace/coverage/cover_reg_top/46.gpio_intr_test.4008155762 Aug 01 05:15:20 PM PDT 24 Aug 01 05:15:21 PM PDT 24 42951954 ps
T771 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3510442631 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 57327381 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.4238695043 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:46 PM PDT 24 14541391 ps
T773 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.642936940 Aug 01 05:15:03 PM PDT 24 Aug 01 05:15:03 PM PDT 24 38095732 ps
T774 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3119961609 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 14640112 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3215162989 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:03 PM PDT 24 76330566 ps
T776 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1482605649 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 51587474 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3936106708 Aug 01 05:14:33 PM PDT 24 Aug 01 05:14:33 PM PDT 24 31764160 ps
T778 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1331627124 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 51196595 ps
T779 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1951543313 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:44 PM PDT 24 28528777 ps
T780 /workspace/coverage/cover_reg_top/3.gpio_intr_test.267256309 Aug 01 05:14:49 PM PDT 24 Aug 01 05:14:50 PM PDT 24 51797081 ps
T781 /workspace/coverage/cover_reg_top/30.gpio_intr_test.627447605 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 12898971 ps
T782 /workspace/coverage/cover_reg_top/38.gpio_intr_test.548169429 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:15 PM PDT 24 39607454 ps
T783 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3093696703 Aug 01 05:14:59 PM PDT 24 Aug 01 05:14:59 PM PDT 24 54077988 ps
T784 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3837631299 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 17285454 ps
T785 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1784440365 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 15276565 ps
T786 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1051578193 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 28683666 ps
T98 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4062978885 Aug 01 05:14:47 PM PDT 24 Aug 01 05:14:48 PM PDT 24 15578683 ps
T787 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3435496797 Aug 01 05:14:47 PM PDT 24 Aug 01 05:14:48 PM PDT 24 25663420 ps
T48 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1961149741 Aug 01 05:15:20 PM PDT 24 Aug 01 05:15:21 PM PDT 24 73842848 ps
T788 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.943850249 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:46 PM PDT 24 415350104 ps
T789 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2175600872 Aug 01 05:14:29 PM PDT 24 Aug 01 05:14:30 PM PDT 24 14735982 ps
T790 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1306261330 Aug 01 05:14:47 PM PDT 24 Aug 01 05:14:48 PM PDT 24 87706393 ps
T791 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1072503342 Aug 01 05:15:03 PM PDT 24 Aug 01 05:15:03 PM PDT 24 16884204 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3409185275 Aug 01 05:15:14 PM PDT 24 Aug 01 05:15:15 PM PDT 24 79780306 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.474993465 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:45 PM PDT 24 69213577 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2374432925 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:46 PM PDT 24 20696475 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_intr_test.172892864 Aug 01 05:14:46 PM PDT 24 Aug 01 05:14:47 PM PDT 24 13767523 ps
T796 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3179023175 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 16505291 ps
T797 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2021186487 Aug 01 05:15:18 PM PDT 24 Aug 01 05:15:19 PM PDT 24 49798443 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2746765221 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:49 PM PDT 24 1775026136 ps
T799 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3479137842 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 36942932 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2443559047 Aug 01 05:14:49 PM PDT 24 Aug 01 05:14:50 PM PDT 24 31987454 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.315628521 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:45 PM PDT 24 43673038 ps
T801 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2820238018 Aug 01 05:15:02 PM PDT 24 Aug 01 05:15:04 PM PDT 24 329902594 ps
T113 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1613434538 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:19 PM PDT 24 126141230 ps
T802 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3649221574 Aug 01 05:15:21 PM PDT 24 Aug 01 05:15:22 PM PDT 24 15904628 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1392136493 Aug 01 05:14:59 PM PDT 24 Aug 01 05:15:00 PM PDT 24 24153426 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1007680560 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:45 PM PDT 24 47443135 ps
T805 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3131338150 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:17 PM PDT 24 17795187 ps
T806 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.598684192 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:03 PM PDT 24 102268765 ps
T96 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3638183430 Aug 01 05:14:46 PM PDT 24 Aug 01 05:14:46 PM PDT 24 83355234 ps
T111 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.316839382 Aug 01 05:15:02 PM PDT 24 Aug 01 05:15:04 PM PDT 24 227334433 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3025908422 Aug 01 05:14:48 PM PDT 24 Aug 01 05:14:49 PM PDT 24 338282828 ps
T808 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1573160933 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:18 PM PDT 24 75018790 ps
T809 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1176015283 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 18837679 ps
T810 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2942170027 Aug 01 05:15:14 PM PDT 24 Aug 01 05:15:14 PM PDT 24 38866618 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4291452520 Aug 01 05:15:18 PM PDT 24 Aug 01 05:15:19 PM PDT 24 159286236 ps
T812 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.484096044 Aug 01 05:14:30 PM PDT 24 Aug 01 05:14:31 PM PDT 24 203356594 ps
T813 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.949413764 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 16387030 ps
T814 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1202267108 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:46 PM PDT 24 22263033 ps
T815 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2533612921 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:19 PM PDT 24 37814946 ps
T816 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2572689928 Aug 01 05:14:52 PM PDT 24 Aug 01 05:14:53 PM PDT 24 22637390 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.114337075 Aug 01 05:14:31 PM PDT 24 Aug 01 05:14:32 PM PDT 24 80910227 ps
T818 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.414134458 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 46690490 ps
T819 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.282775840 Aug 01 05:15:16 PM PDT 24 Aug 01 05:15:19 PM PDT 24 258318587 ps
T820 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.359849369 Aug 01 05:15:01 PM PDT 24 Aug 01 05:15:02 PM PDT 24 50777245 ps
T821 /workspace/coverage/cover_reg_top/21.gpio_intr_test.126552653 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 19504404 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.157454662 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:46 PM PDT 24 130084993 ps
T823 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.235574078 Aug 01 05:15:02 PM PDT 24 Aug 01 05:15:02 PM PDT 24 21275960 ps
T824 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2843307340 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:18 PM PDT 24 14686941 ps
T825 /workspace/coverage/cover_reg_top/48.gpio_intr_test.610506695 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:16 PM PDT 24 34932130 ps
T826 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1760509367 Aug 01 05:15:15 PM PDT 24 Aug 01 05:15:15 PM PDT 24 50155360 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2975332085 Aug 01 05:15:14 PM PDT 24 Aug 01 05:15:15 PM PDT 24 44818280 ps
T97 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2838567983 Aug 01 05:14:34 PM PDT 24 Aug 01 05:14:36 PM PDT 24 433511174 ps
T828 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.714913133 Aug 01 05:14:50 PM PDT 24 Aug 01 05:14:51 PM PDT 24 34972348 ps
T829 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2843854190 Aug 01 05:15:18 PM PDT 24 Aug 01 05:15:19 PM PDT 24 22864609 ps
T830 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2319355833 Aug 01 05:14:44 PM PDT 24 Aug 01 05:14:45 PM PDT 24 69040146 ps
T831 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1654319689 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:18 PM PDT 24 47258467 ps
T832 /workspace/coverage/cover_reg_top/11.gpio_intr_test.20582622 Aug 01 05:15:00 PM PDT 24 Aug 01 05:15:01 PM PDT 24 33624994 ps
T833 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4265162062 Aug 01 05:15:14 PM PDT 24 Aug 01 05:15:16 PM PDT 24 23068032 ps
T834 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.714877795 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:45 PM PDT 24 30955959 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2061340288 Aug 01 05:14:45 PM PDT 24 Aug 01 05:14:46 PM PDT 24 16361333 ps
T836 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1058573322 Aug 01 05:15:17 PM PDT 24 Aug 01 05:15:18 PM PDT 24 23304219 ps
T837 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.687831489 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 54059368 ps
T838 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2273302722 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 327399193 ps
T839 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3923422432 Aug 01 05:19:43 PM PDT 24 Aug 01 05:19:44 PM PDT 24 241586357 ps
T840 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513213598 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 222556271 ps
T841 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.876415216 Aug 01 05:19:22 PM PDT 24 Aug 01 05:19:23 PM PDT 24 163229118 ps
T842 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.960409129 Aug 01 05:19:25 PM PDT 24 Aug 01 05:19:27 PM PDT 24 200678093 ps
T843 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2178877083 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:33 PM PDT 24 175882090 ps
T844 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.363861906 Aug 01 05:19:42 PM PDT 24 Aug 01 05:19:43 PM PDT 24 54047152 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.301350191 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:22 PM PDT 24 120425334 ps
T846 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3077683378 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 194645259 ps
T847 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3965651711 Aug 01 05:19:39 PM PDT 24 Aug 01 05:19:40 PM PDT 24 37233991 ps
T848 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4070238416 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:34 PM PDT 24 213066937 ps
T849 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1068502809 Aug 01 05:19:39 PM PDT 24 Aug 01 05:19:40 PM PDT 24 29600270 ps
T850 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422142777 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 438478223 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1412501493 Aug 01 05:19:18 PM PDT 24 Aug 01 05:19:19 PM PDT 24 36487756 ps
T852 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247660597 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 49302688 ps
T853 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.348870730 Aug 01 05:19:18 PM PDT 24 Aug 01 05:19:20 PM PDT 24 312314317 ps
T854 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.114212151 Aug 01 05:19:24 PM PDT 24 Aug 01 05:19:25 PM PDT 24 54600108 ps
T855 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4213142739 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 34279599 ps
T856 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1575119942 Aug 01 05:19:39 PM PDT 24 Aug 01 05:19:40 PM PDT 24 40375970 ps
T857 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1445961526 Aug 01 05:19:44 PM PDT 24 Aug 01 05:19:45 PM PDT 24 66919074 ps
T858 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1664830696 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:32 PM PDT 24 29127675 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2755835924 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 161132341 ps
T860 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2848237539 Aug 01 05:19:47 PM PDT 24 Aug 01 05:19:48 PM PDT 24 54246452 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.473274213 Aug 01 05:19:19 PM PDT 24 Aug 01 05:19:21 PM PDT 24 39269998 ps
T862 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.847020693 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:22 PM PDT 24 222752340 ps
T863 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3567597443 Aug 01 05:19:44 PM PDT 24 Aug 01 05:19:46 PM PDT 24 49875022 ps
T864 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2451571384 Aug 01 05:19:43 PM PDT 24 Aug 01 05:19:44 PM PDT 24 140520841 ps
T865 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150111262 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:43 PM PDT 24 116152128 ps
T866 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.275116266 Aug 01 05:19:42 PM PDT 24 Aug 01 05:19:43 PM PDT 24 74466702 ps
T867 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3996725116 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 165091043 ps
T868 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2218897226 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:32 PM PDT 24 285241342 ps
T869 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265380616 Aug 01 05:19:20 PM PDT 24 Aug 01 05:19:21 PM PDT 24 57207494 ps
T870 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3425721681 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:43 PM PDT 24 135986147 ps
T871 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3442039017 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 199620178 ps
T872 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3826331503 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 133132141 ps
T873 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.202087768 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 343416846 ps
T874 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1591618913 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:23 PM PDT 24 166028339 ps
T875 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2959364009 Aug 01 05:19:25 PM PDT 24 Aug 01 05:19:26 PM PDT 24 44686516 ps
T876 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2297301942 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:22 PM PDT 24 99003474 ps
T877 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3449952948 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:33 PM PDT 24 68744661 ps
T878 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4029375110 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:33 PM PDT 24 65169355 ps
T879 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849369215 Aug 01 05:19:43 PM PDT 24 Aug 01 05:19:44 PM PDT 24 33568374 ps
T880 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2864962136 Aug 01 05:19:29 PM PDT 24 Aug 01 05:19:31 PM PDT 24 138274517 ps
T881 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2959585279 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:23 PM PDT 24 115416673 ps
T882 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4109097785 Aug 01 05:19:46 PM PDT 24 Aug 01 05:19:47 PM PDT 24 117461197 ps
T883 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41253937 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 79712987 ps
T884 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1516259535 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:32 PM PDT 24 41434564 ps
T885 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3620904270 Aug 01 05:19:29 PM PDT 24 Aug 01 05:19:30 PM PDT 24 233500529 ps
T886 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3309676276 Aug 01 05:19:20 PM PDT 24 Aug 01 05:19:22 PM PDT 24 76067498 ps
T887 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1299824269 Aug 01 05:19:25 PM PDT 24 Aug 01 05:19:26 PM PDT 24 58038634 ps
T888 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3522914678 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 42843409 ps
T889 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1568736899 Aug 01 05:19:42 PM PDT 24 Aug 01 05:19:43 PM PDT 24 172257829 ps
T890 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.267066457 Aug 01 05:19:24 PM PDT 24 Aug 01 05:19:26 PM PDT 24 340340849 ps
T891 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3528930725 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:47 PM PDT 24 33898262 ps
T892 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1265145338 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 84476778 ps
T893 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330857261 Aug 01 05:19:38 PM PDT 24 Aug 01 05:19:39 PM PDT 24 204539917 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4061305844 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:33 PM PDT 24 23693107 ps
T895 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2540810687 Aug 01 05:19:42 PM PDT 24 Aug 01 05:19:43 PM PDT 24 167113539 ps
T896 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099893336 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:31 PM PDT 24 43532961 ps
T897 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3584207711 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 59925013 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1979784600 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 36578739 ps
T899 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2187035253 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 38619606 ps
T900 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1065363860 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:43 PM PDT 24 49812329 ps
T901 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4243742701 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:22 PM PDT 24 35952693 ps
T902 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1772553327 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 74243290 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.225648099 Aug 01 05:19:22 PM PDT 24 Aug 01 05:19:23 PM PDT 24 109969939 ps
T904 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3374197048 Aug 01 05:19:23 PM PDT 24 Aug 01 05:19:24 PM PDT 24 384661035 ps
T905 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.743585164 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 329901412 ps
T906 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1972058195 Aug 01 05:19:23 PM PDT 24 Aug 01 05:19:25 PM PDT 24 258793631 ps
T907 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2205390669 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 19820322 ps
T908 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1713507481 Aug 01 05:19:20 PM PDT 24 Aug 01 05:19:21 PM PDT 24 92373129 ps
T909 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.599917548 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 194307564 ps
T910 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3738640477 Aug 01 05:19:22 PM PDT 24 Aug 01 05:19:23 PM PDT 24 51167274 ps
T911 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1078510419 Aug 01 05:19:44 PM PDT 24 Aug 01 05:19:45 PM PDT 24 150826226 ps
T912 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.980235144 Aug 01 05:19:31 PM PDT 24 Aug 01 05:19:33 PM PDT 24 70648149 ps
T913 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805729061 Aug 01 05:19:42 PM PDT 24 Aug 01 05:19:44 PM PDT 24 183088331 ps
T914 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870530595 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 158085296 ps
T915 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921047515 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:43 PM PDT 24 60005330 ps
T916 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2402049880 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 33800188 ps
T917 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3786987727 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:35 PM PDT 24 43869631 ps
T918 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1007398597 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 305302538 ps
T919 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1827463156 Aug 01 05:19:30 PM PDT 24 Aug 01 05:19:32 PM PDT 24 174315052 ps
T920 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2217932666 Aug 01 05:19:24 PM PDT 24 Aug 01 05:19:25 PM PDT 24 190163196 ps
T921 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325770641 Aug 01 05:19:32 PM PDT 24 Aug 01 05:19:34 PM PDT 24 203477946 ps
T922 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454208469 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:23 PM PDT 24 78755529 ps
T923 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541711297 Aug 01 05:19:33 PM PDT 24 Aug 01 05:19:34 PM PDT 24 58704897 ps
T924 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3916880526 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 353635154 ps
T925 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.513738611 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 184932173 ps
T926 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1256644275 Aug 01 05:19:46 PM PDT 24 Aug 01 05:19:47 PM PDT 24 37199942 ps
T927 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.770640147 Aug 01 05:19:22 PM PDT 24 Aug 01 05:19:23 PM PDT 24 153090168 ps
T928 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1978395499 Aug 01 05:19:22 PM PDT 24 Aug 01 05:19:23 PM PDT 24 213908047 ps
T929 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2013738625 Aug 01 05:19:44 PM PDT 24 Aug 01 05:19:46 PM PDT 24 362567949 ps
T930 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873547117 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 382513293 ps
T931 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.175473420 Aug 01 05:19:19 PM PDT 24 Aug 01 05:19:20 PM PDT 24 46188455 ps
T932 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701471571 Aug 01 05:19:41 PM PDT 24 Aug 01 05:19:42 PM PDT 24 252309798 ps
T933 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1788009081 Aug 01 05:19:45 PM PDT 24 Aug 01 05:19:46 PM PDT 24 245543780 ps
T934 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1203355750 Aug 01 05:19:21 PM PDT 24 Aug 01 05:19:22 PM PDT 24 163816515 ps
T935 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3589277244 Aug 01 05:19:18 PM PDT 24 Aug 01 05:19:19 PM PDT 24 70718850 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101024086 Aug 01 05:19:44 PM PDT 24 Aug 01 05:19:45 PM PDT 24 27760983 ps

Test location /workspace/coverage/default/0.gpio_full_random.3601546427
Short name T27
Test name
Test status
Simulation time 73054857 ps
CPU time 1 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 198416 kb
Host smart-b8aaea5c-1fdb-4aba-9b8c-fb7a444b44c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601546427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3601546427
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2430896886
Short name T114
Test name
Test status
Simulation time 338690627 ps
CPU time 3.24 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:11 PM PDT 24
Peak memory 198520 kb
Host smart-a2d1c5f5-5e22-4635-9f09-85cd371f301f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430896886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2430896886
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.164952892
Short name T61
Test name
Test status
Simulation time 54290400161 ps
CPU time 1305.63 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:42:58 PM PDT 24
Peak memory 198856 kb
Host smart-80578121-5838-4d93-a7dc-2a243b5eea61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=164952892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.164952892
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1900689606
Short name T1
Test name
Test status
Simulation time 854649122 ps
CPU time 4.96 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:11 PM PDT 24
Peak memory 198484 kb
Host smart-fd67cd8b-1874-4038-8a16-b229552d2470
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900689606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1900689606
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4014636167
Short name T18
Test name
Test status
Simulation time 66096142 ps
CPU time 0.8 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 215112 kb
Host smart-0c32f3ab-9ae4-4be0-a5a1-f2cce3f65cc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014636167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4014636167
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2366748553
Short name T36
Test name
Test status
Simulation time 228257053 ps
CPU time 1.37 seconds
Started Aug 01 05:14:50 PM PDT 24
Finished Aug 01 05:14:52 PM PDT 24
Peak memory 198696 kb
Host smart-2f22bc69-cbae-435f-ad97-fe830757514d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366748553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2366748553
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.27708273
Short name T154
Test name
Test status
Simulation time 32125361 ps
CPU time 0.56 seconds
Started Aug 01 05:19:46 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 194404 kb
Host smart-b45cee2f-f281-4f44-bb1e-5b8e5db70265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.27708273
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.576832535
Short name T85
Test name
Test status
Simulation time 17923608 ps
CPU time 0.79 seconds
Started Aug 01 05:14:32 PM PDT 24
Finished Aug 01 05:14:33 PM PDT 24
Peak memory 196556 kb
Host smart-77581bb6-905f-4ac4-8d68-a1a4b025d426
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576832535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.576832535
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1039413900
Short name T100
Test name
Test status
Simulation time 16780347 ps
CPU time 0.63 seconds
Started Aug 01 05:14:33 PM PDT 24
Finished Aug 01 05:14:34 PM PDT 24
Peak memory 195264 kb
Host smart-0cf6f009-af7a-49ab-b39d-87b98b051083
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039413900 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1039413900
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.484096044
Short name T812
Test name
Test status
Simulation time 203356594 ps
CPU time 1.38 seconds
Started Aug 01 05:14:30 PM PDT 24
Finished Aug 01 05:14:31 PM PDT 24
Peak memory 198632 kb
Host smart-4389608d-b0a7-4a04-be0a-adacaf00d884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484096044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.484096044
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3180459905
Short name T14
Test name
Test status
Simulation time 6543670061 ps
CPU time 184.17 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:22:59 PM PDT 24
Peak memory 198668 kb
Host smart-af811f8e-1bbc-4cad-bc45-61b93c186537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180459905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3180459905
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2920620602
Short name T110
Test name
Test status
Simulation time 81881676 ps
CPU time 1.14 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:01 PM PDT 24
Peak memory 198784 kb
Host smart-dfdd4e46-0bca-4bf5-b86a-e5f5c25d028e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920620602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2920620602
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2838567983
Short name T97
Test name
Test status
Simulation time 433511174 ps
CPU time 1.42 seconds
Started Aug 01 05:14:34 PM PDT 24
Finished Aug 01 05:14:36 PM PDT 24
Peak memory 197444 kb
Host smart-a7064cb0-3499-49cf-a2de-dfe96cc2adb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838567983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2838567983
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1373077628
Short name T84
Test name
Test status
Simulation time 43569249 ps
CPU time 0.64 seconds
Started Aug 01 05:14:31 PM PDT 24
Finished Aug 01 05:14:32 PM PDT 24
Peak memory 195240 kb
Host smart-c2f287c4-c6fc-41ed-b748-b5adb5ee4827
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373077628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1373077628
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.114337075
Short name T817
Test name
Test status
Simulation time 80910227 ps
CPU time 0.97 seconds
Started Aug 01 05:14:31 PM PDT 24
Finished Aug 01 05:14:32 PM PDT 24
Peak memory 198472 kb
Host smart-9e8f1beb-a4d3-460b-98f9-abbafc4a226e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114337075 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.114337075
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2175600872
Short name T789
Test name
Test status
Simulation time 14735982 ps
CPU time 0.58 seconds
Started Aug 01 05:14:29 PM PDT 24
Finished Aug 01 05:14:30 PM PDT 24
Peak memory 195904 kb
Host smart-30de7880-70c1-42a1-9652-99625ee75883
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175600872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2175600872
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1404632668
Short name T758
Test name
Test status
Simulation time 14719510 ps
CPU time 0.6 seconds
Started Aug 01 05:14:32 PM PDT 24
Finished Aug 01 05:14:33 PM PDT 24
Peak memory 194388 kb
Host smart-62139381-aae2-4df5-b2dd-2e54231e4e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404632668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1404632668
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.703277568
Short name T746
Test name
Test status
Simulation time 356078171 ps
CPU time 3.58 seconds
Started Aug 01 05:14:33 PM PDT 24
Finished Aug 01 05:14:37 PM PDT 24
Peak memory 198716 kb
Host smart-76754cea-fcf0-4361-a93e-c9fe8866e791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703277568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.703277568
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3195200757
Short name T46
Test name
Test status
Simulation time 333904823 ps
CPU time 1.29 seconds
Started Aug 01 05:14:32 PM PDT 24
Finished Aug 01 05:14:34 PM PDT 24
Peak memory 198720 kb
Host smart-ca106f38-b268-4170-8e27-ea7992a704e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195200757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3195200757
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.6709263
Short name T94
Test name
Test status
Simulation time 41797908 ps
CPU time 0.9 seconds
Started Aug 01 05:14:34 PM PDT 24
Finished Aug 01 05:14:35 PM PDT 24
Peak memory 196724 kb
Host smart-66344620-5d83-426a-93c2-9830716e1ab5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6709263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.g
pio_csr_aliasing.6709263
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2580880313
Short name T764
Test name
Test status
Simulation time 74216640 ps
CPU time 1.45 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 198548 kb
Host smart-1aeb7837-16db-4d33-959e-1016452aa429
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580880313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2580880313
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2131466940
Short name T83
Test name
Test status
Simulation time 49318030 ps
CPU time 0.58 seconds
Started Aug 01 05:14:30 PM PDT 24
Finished Aug 01 05:14:31 PM PDT 24
Peak memory 194912 kb
Host smart-d07b72ce-4ef0-4168-ab36-5d0f2963a09b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131466940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2131466940
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3920436319
Short name T754
Test name
Test status
Simulation time 24737842 ps
CPU time 1.08 seconds
Started Aug 01 05:14:32 PM PDT 24
Finished Aug 01 05:14:34 PM PDT 24
Peak memory 198692 kb
Host smart-dae48918-d8b5-4658-9ebe-00ebe721cdf7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920436319 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3920436319
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.456754916
Short name T89
Test name
Test status
Simulation time 11880580 ps
CPU time 0.68 seconds
Started Aug 01 05:14:32 PM PDT 24
Finished Aug 01 05:14:33 PM PDT 24
Peak memory 195632 kb
Host smart-94830eb1-3e9a-44be-9773-b7cfa959a0af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456754916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.456754916
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3936106708
Short name T777
Test name
Test status
Simulation time 31764160 ps
CPU time 0.56 seconds
Started Aug 01 05:14:33 PM PDT 24
Finished Aug 01 05:14:33 PM PDT 24
Peak memory 194444 kb
Host smart-7a1a424a-93b6-47fb-a315-267fa6b31712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936106708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3936106708
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4259756510
Short name T106
Test name
Test status
Simulation time 62800204 ps
CPU time 0.85 seconds
Started Aug 01 05:14:30 PM PDT 24
Finished Aug 01 05:14:31 PM PDT 24
Peak memory 197024 kb
Host smart-76754b4d-b010-494a-b09f-5f45729c9ec8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259756510 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4259756510
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2988308281
Short name T718
Test name
Test status
Simulation time 114733888 ps
CPU time 2.18 seconds
Started Aug 01 05:14:33 PM PDT 24
Finished Aug 01 05:14:35 PM PDT 24
Peak memory 198704 kb
Host smart-fd987d09-91e2-402b-b6ca-c905dce0768c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988308281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2988308281
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1777662940
Short name T721
Test name
Test status
Simulation time 72834658 ps
CPU time 1.71 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 198884 kb
Host smart-75214c90-90a9-490f-adcc-b7f84460faf8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777662940 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1777662940
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.642936940
Short name T773
Test name
Test status
Simulation time 38095732 ps
CPU time 0.64 seconds
Started Aug 01 05:15:03 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 195460 kb
Host smart-06b807d1-52b4-4045-bec5-44e270099d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642936940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.642936940
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2113025267
Short name T728
Test name
Test status
Simulation time 11420625 ps
CPU time 0.58 seconds
Started Aug 01 05:14:58 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 194404 kb
Host smart-166b5a40-d146-4d80-954b-3868e5eb5319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113025267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2113025267
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3971947148
Short name T88
Test name
Test status
Simulation time 72777056 ps
CPU time 0.73 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 196112 kb
Host smart-5cf77caf-7e85-43eb-9b96-3575580c1bae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971947148 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3971947148
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1959011087
Short name T756
Test name
Test status
Simulation time 36962100 ps
CPU time 1.05 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 198488 kb
Host smart-25af0e5d-d42d-4647-8c5c-64c923d1d8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959011087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1959011087
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1331627124
Short name T778
Test name
Test status
Simulation time 51196595 ps
CPU time 0.95 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 197376 kb
Host smart-75871b01-a452-4fbb-8789-74c21db5ba98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331627124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1331627124
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.842609225
Short name T715
Test name
Test status
Simulation time 186872403 ps
CPU time 1.03 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:01 PM PDT 24
Peak memory 198624 kb
Host smart-40605bc1-ca65-417a-b6d6-b48dee5083f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842609225 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.842609225
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3093696703
Short name T783
Test name
Test status
Simulation time 54077988 ps
CPU time 0.63 seconds
Started Aug 01 05:14:59 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 195528 kb
Host smart-cddec224-9973-420c-926e-af7d3358d3e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093696703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3093696703
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.20582622
Short name T832
Test name
Test status
Simulation time 33624994 ps
CPU time 0.62 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:01 PM PDT 24
Peak memory 194500 kb
Host smart-8a7af9b3-47db-497a-9ac1-828fd766cc9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.20582622
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.359849369
Short name T820
Test name
Test status
Simulation time 50777245 ps
CPU time 0.73 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 196276 kb
Host smart-c329de51-d5f7-422b-8fa5-361b4b7725ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359849369 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.359849369
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.497734934
Short name T748
Test name
Test status
Simulation time 185195414 ps
CPU time 2.59 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 198652 kb
Host smart-7570479b-471b-451f-8abb-3ecf35fc76a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497734934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.497734934
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.316839382
Short name T111
Test name
Test status
Simulation time 227334433 ps
CPU time 1.36 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:04 PM PDT 24
Peak memory 198664 kb
Host smart-4ff0bf13-2c69-47aa-bfcf-f5071b694cd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316839382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.316839382
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1392136493
Short name T803
Test name
Test status
Simulation time 24153426 ps
CPU time 0.78 seconds
Started Aug 01 05:14:59 PM PDT 24
Finished Aug 01 05:15:00 PM PDT 24
Peak memory 198536 kb
Host smart-fd782f02-6722-4e98-8c69-67ede82d9825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392136493 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1392136493
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1847049897
Short name T91
Test name
Test status
Simulation time 17227506 ps
CPU time 0.61 seconds
Started Aug 01 05:14:59 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 195192 kb
Host smart-6db07759-562e-47bf-b3ee-838185f247dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847049897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1847049897
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2778063298
Short name T732
Test name
Test status
Simulation time 46608678 ps
CPU time 0.61 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 195152 kb
Host smart-85da9826-60e4-4302-96ac-342b4e663108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778063298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2778063298
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3923511221
Short name T765
Test name
Test status
Simulation time 63279250 ps
CPU time 0.88 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 196924 kb
Host smart-956ad285-96c1-41b9-902b-035a3ea2d79a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923511221 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3923511221
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3740370204
Short name T755
Test name
Test status
Simulation time 44639987 ps
CPU time 1.21 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 198736 kb
Host smart-fe87ef7a-9073-4e81-b5be-a35d161a91f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740370204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3740370204
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4073575949
Short name T741
Test name
Test status
Simulation time 23016605 ps
CPU time 1.03 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:04 PM PDT 24
Peak memory 198536 kb
Host smart-6afa05ce-3e61-4e0a-b0d1-06e73a78bdd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073575949 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4073575949
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3510442631
Short name T771
Test name
Test status
Simulation time 57327381 ps
CPU time 0.62 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 195452 kb
Host smart-b1aec58f-2df6-43c8-9681-d44e50d937c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510442631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3510442631
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.84061153
Short name T727
Test name
Test status
Simulation time 14609678 ps
CPU time 0.63 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 194340 kb
Host smart-224c3ac7-1bd6-4c24-9e0c-c3c71d0ee470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84061153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.84061153
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3011175949
Short name T87
Test name
Test status
Simulation time 13322196 ps
CPU time 0.63 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 195808 kb
Host smart-b9d61151-19d3-4f2d-85e5-bd95f7f2f79b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011175949 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3011175949
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3215162989
Short name T775
Test name
Test status
Simulation time 76330566 ps
CPU time 2.07 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 198712 kb
Host smart-2726e356-fabf-47be-85bc-adaa3c902c84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215162989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3215162989
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.884904666
Short name T112
Test name
Test status
Simulation time 49353919 ps
CPU time 0.9 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 197816 kb
Host smart-92536d65-99ca-41df-bb4e-6d7787c0e3ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884904666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.884904666
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3654348845
Short name T747
Test name
Test status
Simulation time 444983836 ps
CPU time 0.98 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:04 PM PDT 24
Peak memory 198588 kb
Host smart-4f8e3d71-a8d0-45f0-aa55-9af69c572040
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654348845 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3654348845
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2783685519
Short name T93
Test name
Test status
Simulation time 54230445 ps
CPU time 0.63 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 195608 kb
Host smart-2850dab2-33c7-4215-843a-ebc4c23b467f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783685519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2783685519
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2479879124
Short name T724
Test name
Test status
Simulation time 123908750 ps
CPU time 0.59 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:01 PM PDT 24
Peak memory 195116 kb
Host smart-00709ce6-3d45-4241-9207-b43e74c8ab0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479879124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2479879124
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2941626974
Short name T101
Test name
Test status
Simulation time 87954270 ps
CPU time 0.64 seconds
Started Aug 01 05:14:58 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 195360 kb
Host smart-307184e9-7053-4285-ac28-413e96586287
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941626974 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2941626974
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3667285989
Short name T738
Test name
Test status
Simulation time 376630605 ps
CPU time 2.2 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:04 PM PDT 24
Peak memory 198728 kb
Host smart-588d0f76-0bbe-4d83-85b6-14d18d0f20cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667285989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3667285989
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2639320539
Short name T43
Test name
Test status
Simulation time 793775893 ps
CPU time 1.46 seconds
Started Aug 01 05:15:00 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 198656 kb
Host smart-745d7919-cef6-4cdd-af4d-d8d88b59c48a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639320539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2639320539
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.414134458
Short name T818
Test name
Test status
Simulation time 46690490 ps
CPU time 0.87 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 198576 kb
Host smart-7c4b88df-4c4e-4341-8641-9af40761890d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414134458 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.414134458
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.235574078
Short name T823
Test name
Test status
Simulation time 21275960 ps
CPU time 0.58 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 195272 kb
Host smart-122c40f4-2529-46d3-96df-164549cca036
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235574078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.235574078
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3623024417
Short name T744
Test name
Test status
Simulation time 42646335 ps
CPU time 0.6 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 194356 kb
Host smart-2852bf7a-e57a-4570-8e48-ee3d0988a215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623024417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3623024417
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2835910035
Short name T103
Test name
Test status
Simulation time 76659397 ps
CPU time 0.71 seconds
Started Aug 01 05:14:59 PM PDT 24
Finished Aug 01 05:15:00 PM PDT 24
Peak memory 195620 kb
Host smart-44d2928c-571c-40b8-97b2-f1922d361c84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835910035 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2835910035
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.598684192
Short name T806
Test name
Test status
Simulation time 102268765 ps
CPU time 1.85 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 198648 kb
Host smart-836de8aa-bb03-4b86-9e81-f93669c463ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598684192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.598684192
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.846559724
Short name T45
Test name
Test status
Simulation time 131442406 ps
CPU time 1.09 seconds
Started Aug 01 05:14:58 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 198688 kb
Host smart-5e067bd3-6679-4e32-97f9-25a888d2ce11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846559724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.846559724
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4291452520
Short name T811
Test name
Test status
Simulation time 159286236 ps
CPU time 0.78 seconds
Started Aug 01 05:15:18 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198616 kb
Host smart-8ddfdb80-1eba-4652-8c57-a504e0dbfc02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291452520 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4291452520
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1325930714
Short name T92
Test name
Test status
Simulation time 14070685 ps
CPU time 0.6 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 194980 kb
Host smart-8f8a3a9e-4c3f-4654-9540-b35bf7349ae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325930714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1325930714
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3351211770
Short name T753
Test name
Test status
Simulation time 29402582 ps
CPU time 0.62 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 195076 kb
Host smart-d5764323-457c-44f8-a179-e892e1962d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351211770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3351211770
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1072503342
Short name T791
Test name
Test status
Simulation time 16884204 ps
CPU time 0.79 seconds
Started Aug 01 05:15:03 PM PDT 24
Finished Aug 01 05:15:03 PM PDT 24
Peak memory 196660 kb
Host smart-17afd428-bdf5-49f0-9bed-34ed5b99d7fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072503342 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1072503342
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.282775840
Short name T819
Test name
Test status
Simulation time 258318587 ps
CPU time 2.75 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198732 kb
Host smart-f948dabc-2733-4ab1-a7e9-69d6b6d82ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282775840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.282775840
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1961149741
Short name T48
Test name
Test status
Simulation time 73842848 ps
CPU time 0.86 seconds
Started Aug 01 05:15:20 PM PDT 24
Finished Aug 01 05:15:21 PM PDT 24
Peak memory 197568 kb
Host smart-4e95d974-bb19-44a1-acad-22814064e34d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961149741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1961149741
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3275975868
Short name T713
Test name
Test status
Simulation time 21179082 ps
CPU time 0.75 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 198456 kb
Host smart-0fad2e07-df23-4972-9fc1-5a1e6d148a17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275975868 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3275975868
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.470338213
Short name T739
Test name
Test status
Simulation time 29668758 ps
CPU time 0.56 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 193948 kb
Host smart-1f1f2c27-6578-47b9-9b2a-9c890a1c393a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470338213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.470338213
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1784440365
Short name T785
Test name
Test status
Simulation time 15276565 ps
CPU time 0.63 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 195080 kb
Host smart-34e35a6e-7d41-4aa0-9448-e0634f888a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784440365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1784440365
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2975332085
Short name T827
Test name
Test status
Simulation time 44818280 ps
CPU time 0.65 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 194996 kb
Host smart-30446cc6-680c-4788-b360-fe1f2b61f4d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975332085 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2975332085
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4265162062
Short name T833
Test name
Test status
Simulation time 23068032 ps
CPU time 1.21 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 198652 kb
Host smart-eda63787-0215-429c-a720-14edfc3300b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265162062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4265162062
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1189515706
Short name T743
Test name
Test status
Simulation time 41286324 ps
CPU time 0.85 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:14 PM PDT 24
Peak memory 197800 kb
Host smart-4e4dbbe3-89fe-4023-a265-44bcf0eda7e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189515706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1189515706
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2533612921
Short name T815
Test name
Test status
Simulation time 37814946 ps
CPU time 1.45 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198748 kb
Host smart-50e8b8d8-9b94-489b-9ead-bd9d30f78cec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533612921 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2533612921
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2122846422
Short name T86
Test name
Test status
Simulation time 58250732 ps
CPU time 0.56 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 193944 kb
Host smart-53b44646-23b6-4ecc-8ca9-d8eead8f1949
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122846422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2122846422
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1227290540
Short name T762
Test name
Test status
Simulation time 215532265 ps
CPU time 0.58 seconds
Started Aug 01 05:15:13 PM PDT 24
Finished Aug 01 05:15:14 PM PDT 24
Peak memory 194484 kb
Host smart-c39b9b76-523d-49c4-b7a2-5ca40998c325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227290540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1227290540
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3682072189
Short name T102
Test name
Test status
Simulation time 65883978 ps
CPU time 0.77 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 196852 kb
Host smart-58146c10-c7b9-4d8b-83d9-e89610710dd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682072189 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3682072189
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3222697026
Short name T730
Test name
Test status
Simulation time 32881724 ps
CPU time 1.5 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198668 kb
Host smart-efdf65cb-220e-409c-8ff9-32c857dd5a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222697026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3222697026
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1613434538
Short name T113
Test name
Test status
Simulation time 126141230 ps
CPU time 1.46 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198624 kb
Host smart-b787ab7c-fec4-4550-affd-00066ec6a6e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613434538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1613434538
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1770841366
Short name T761
Test name
Test status
Simulation time 100660893 ps
CPU time 1.4 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 198712 kb
Host smart-18ff48b5-f6d8-4d36-8174-420c34263e97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770841366 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1770841366
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1573160933
Short name T808
Test name
Test status
Simulation time 75018790 ps
CPU time 0.61 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 196064 kb
Host smart-dace23df-d924-4c23-ad3e-7ad69a164c9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573160933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1573160933
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3131338150
Short name T805
Test name
Test status
Simulation time 17795187 ps
CPU time 0.58 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 194692 kb
Host smart-68a8cc7a-40c2-44ee-b8f2-bb9f31f13a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131338150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3131338150
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.407520190
Short name T105
Test name
Test status
Simulation time 134810080 ps
CPU time 0.72 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 196760 kb
Host smart-cdac3fb7-b14a-4cf1-a70e-d3e6cabc914c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407520190 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.407520190
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2432542955
Short name T711
Test name
Test status
Simulation time 113989584 ps
CPU time 1.96 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 198736 kb
Host smart-3ef581c7-d36a-4e85-936d-423fe4ad5ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432542955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2432542955
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3409185275
Short name T792
Test name
Test status
Simulation time 79780306 ps
CPU time 0.88 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 197576 kb
Host smart-9d3af715-62f4-4686-8947-f4fae23be440
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409185275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3409185275
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2319355833
Short name T830
Test name
Test status
Simulation time 69040146 ps
CPU time 0.64 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 195540 kb
Host smart-8b4da2a2-af51-45b7-895d-a75a5392fad7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319355833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2319355833
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2746765221
Short name T798
Test name
Test status
Simulation time 1775026136 ps
CPU time 3.51 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:49 PM PDT 24
Peak memory 197788 kb
Host smart-c7b0408c-6eda-4dfb-bcc3-99b7a59fa55d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746765221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2746765221
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2374432925
Short name T794
Test name
Test status
Simulation time 20696475 ps
CPU time 0.6 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 194912 kb
Host smart-5ad6aab4-29ff-4d18-b1a6-9eec0cd9c50b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374432925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2374432925
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4157838276
Short name T745
Test name
Test status
Simulation time 22121252 ps
CPU time 0.75 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 198420 kb
Host smart-628ba436-eb7d-42b3-9555-a880d35d791a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157838276 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4157838276
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2061340288
Short name T835
Test name
Test status
Simulation time 16361333 ps
CPU time 0.68 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 196252 kb
Host smart-85ae79aa-6739-43d9-971c-71e176cd3df0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061340288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2061340288
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1202267108
Short name T814
Test name
Test status
Simulation time 22263033 ps
CPU time 0.6 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 194496 kb
Host smart-45ef6d33-acb7-4b96-abf9-22845b03b7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202267108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1202267108
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3847988913
Short name T767
Test name
Test status
Simulation time 37692737 ps
CPU time 0.83 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 197564 kb
Host smart-a042fb0b-f395-402c-a040-efddb0bafdef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847988913 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3847988913
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1007680560
Short name T804
Test name
Test status
Simulation time 47443135 ps
CPU time 1.41 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 198728 kb
Host smart-2770f913-0b4d-4f8e-879e-a0f6c4e4a1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007680560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1007680560
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1092633985
Short name T44
Test name
Test status
Simulation time 252926911 ps
CPU time 1.41 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 198640 kb
Host smart-025992a3-1113-47e7-951a-c33ed0ed6172
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092633985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1092633985
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2872618263
Short name T731
Test name
Test status
Simulation time 31599062 ps
CPU time 0.63 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194484 kb
Host smart-4d86f0f0-b0fe-4e42-b51c-55531d9d9bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872618263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2872618263
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.126552653
Short name T821
Test name
Test status
Simulation time 19504404 ps
CPU time 0.63 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194420 kb
Host smart-6cefe939-d55c-4a9e-85c6-ef1c4a2aa548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126552653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.126552653
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1176015283
Short name T809
Test name
Test status
Simulation time 18837679 ps
CPU time 0.63 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 195108 kb
Host smart-40411763-ee9a-4e50-91b6-8eff8dc36fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176015283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1176015283
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1482605649
Short name T776
Test name
Test status
Simulation time 51587474 ps
CPU time 0.62 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194416 kb
Host smart-6ecd6ed3-0a69-45d6-af3f-1ee198c80dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482605649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1482605649
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2942170027
Short name T810
Test name
Test status
Simulation time 38866618 ps
CPU time 0.57 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:14 PM PDT 24
Peak memory 194460 kb
Host smart-6682c42a-3057-4edd-8bf9-bc4d70a67fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942170027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2942170027
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3599635839
Short name T734
Test name
Test status
Simulation time 13522547 ps
CPU time 0.64 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 194356 kb
Host smart-84a76428-b677-49c9-b45f-9bc819e545ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599635839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3599635839
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3119961609
Short name T774
Test name
Test status
Simulation time 14640112 ps
CPU time 0.7 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 194404 kb
Host smart-32bda1da-b564-47ea-a7ee-81de7cd7dd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119961609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3119961609
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.15358006
Short name T766
Test name
Test status
Simulation time 26708349 ps
CPU time 0.57 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 194328 kb
Host smart-55a9994c-f9bb-4859-ada1-b01878a5f4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15358006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.15358006
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2759895160
Short name T726
Test name
Test status
Simulation time 25283341 ps
CPU time 0.6 seconds
Started Aug 01 05:15:14 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 194484 kb
Host smart-6c270868-f311-4c9b-aac9-ea5e964df4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759895160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2759895160
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2875501724
Short name T735
Test name
Test status
Simulation time 18116682 ps
CPU time 0.59 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 195084 kb
Host smart-9fc8cd17-688c-4cfa-8304-29fc08934ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875501724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2875501724
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.315628521
Short name T95
Test name
Test status
Simulation time 43673038 ps
CPU time 0.63 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 195048 kb
Host smart-0ea1a9b2-68d9-4a51-9209-3ef3336bfe86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315628521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.315628521
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.157454662
Short name T822
Test name
Test status
Simulation time 130084993 ps
CPU time 1.36 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 197528 kb
Host smart-33504b51-92fa-4dbe-8339-59a1849c9390
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157454662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.157454662
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4062978885
Short name T98
Test name
Test status
Simulation time 15578683 ps
CPU time 0.68 seconds
Started Aug 01 05:14:47 PM PDT 24
Finished Aug 01 05:14:48 PM PDT 24
Peak memory 196168 kb
Host smart-42dbc9fa-7f64-447f-b7ff-f57421c19230
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062978885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4062978885
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.714913133
Short name T828
Test name
Test status
Simulation time 34972348 ps
CPU time 0.66 seconds
Started Aug 01 05:14:50 PM PDT 24
Finished Aug 01 05:14:51 PM PDT 24
Peak memory 197600 kb
Host smart-38b3891a-ec7d-4856-bd76-92640d448d41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714913133 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.714913133
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4015547899
Short name T742
Test name
Test status
Simulation time 25400581 ps
CPU time 0.63 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 195436 kb
Host smart-2670cfd0-4305-4a99-8cb0-2bc808198747
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015547899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4015547899
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.267256309
Short name T780
Test name
Test status
Simulation time 51797081 ps
CPU time 0.6 seconds
Started Aug 01 05:14:49 PM PDT 24
Finished Aug 01 05:14:50 PM PDT 24
Peak memory 194524 kb
Host smart-997ffa69-aad9-42f7-973b-5daac557547a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267256309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.267256309
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3830046084
Short name T104
Test name
Test status
Simulation time 53864190 ps
CPU time 0.81 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 197440 kb
Host smart-e9ffedca-692e-4c4f-9405-19890b3ba973
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830046084 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3830046084
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.368006951
Short name T723
Test name
Test status
Simulation time 201383180 ps
CPU time 3.04 seconds
Started Aug 01 05:14:54 PM PDT 24
Finished Aug 01 05:14:57 PM PDT 24
Peak memory 198720 kb
Host smart-8c51ca23-1eea-41b4-bc2a-206130c0b6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368006951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.368006951
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2419021296
Short name T35
Test name
Test status
Simulation time 38654646 ps
CPU time 0.89 seconds
Started Aug 01 05:14:52 PM PDT 24
Finished Aug 01 05:14:53 PM PDT 24
Peak memory 197768 kb
Host smart-f0c4e967-d277-4df8-9bbd-d34b030ff7f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419021296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2419021296
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.627447605
Short name T781
Test name
Test status
Simulation time 12898971 ps
CPU time 0.61 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 194332 kb
Host smart-9ef07798-e1c4-40b6-854b-cfb65f221c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627447605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.627447605
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2843854190
Short name T829
Test name
Test status
Simulation time 22864609 ps
CPU time 0.62 seconds
Started Aug 01 05:15:18 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 194536 kb
Host smart-aa7b991f-ed6c-4b7d-b96f-525a06dc172d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843854190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2843854190
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3511797548
Short name T769
Test name
Test status
Simulation time 42222913 ps
CPU time 0.61 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 195032 kb
Host smart-21a90a2a-b936-4b07-8fe3-58524211f0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511797548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3511797548
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2843307340
Short name T824
Test name
Test status
Simulation time 14686941 ps
CPU time 0.62 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 194424 kb
Host smart-28b1613c-488f-4aad-b6e4-c710a8462537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843307340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2843307340
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1107140365
Short name T740
Test name
Test status
Simulation time 14693770 ps
CPU time 0.65 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194360 kb
Host smart-4ea8b07b-5c98-4e5e-b4cf-37d9893a1dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107140365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1107140365
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3179023175
Short name T796
Test name
Test status
Simulation time 16505291 ps
CPU time 0.71 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194368 kb
Host smart-0fc1c159-335f-44f5-b243-33f7a965926c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179023175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3179023175
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2390745372
Short name T722
Test name
Test status
Simulation time 12691685 ps
CPU time 0.61 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 195040 kb
Host smart-3f30a78f-2cef-4cc8-95d4-0cef067c357d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390745372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2390745372
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2021186487
Short name T797
Test name
Test status
Simulation time 49798443 ps
CPU time 0.62 seconds
Started Aug 01 05:15:18 PM PDT 24
Finished Aug 01 05:15:19 PM PDT 24
Peak memory 195144 kb
Host smart-48c71566-0125-45ea-8c73-c30738aea113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021186487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2021186487
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.548169429
Short name T782
Test name
Test status
Simulation time 39607454 ps
CPU time 0.56 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 194340 kb
Host smart-b7395017-4f12-46ad-b57a-235f5961ae76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548169429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.548169429
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3769809040
Short name T717
Test name
Test status
Simulation time 16284646 ps
CPU time 0.73 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 194448 kb
Host smart-4cac62ef-5230-46c9-9fe3-8622b699d35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769809040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3769809040
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3638183430
Short name T96
Test name
Test status
Simulation time 83355234 ps
CPU time 0.73 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 196760 kb
Host smart-bbe6f039-e290-439d-8540-cecf11fdd609
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638183430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3638183430
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.206865216
Short name T757
Test name
Test status
Simulation time 234627392 ps
CPU time 1.43 seconds
Started Aug 01 05:14:53 PM PDT 24
Finished Aug 01 05:14:55 PM PDT 24
Peak memory 197496 kb
Host smart-fb1bcdc4-bd90-49b0-90aa-8b1496f1432d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206865216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.206865216
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.714877795
Short name T834
Test name
Test status
Simulation time 30955959 ps
CPU time 0.62 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 195360 kb
Host smart-f035aa53-96f0-4f75-b70b-28e65b0bfbde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714877795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.714877795
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3450663316
Short name T749
Test name
Test status
Simulation time 16281826 ps
CPU time 0.86 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 198540 kb
Host smart-b1b0df8b-577b-419b-8d87-dce42a77d556
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450663316 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3450663316
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3269033868
Short name T108
Test name
Test status
Simulation time 47604490 ps
CPU time 0.61 seconds
Started Aug 01 05:14:53 PM PDT 24
Finished Aug 01 05:14:53 PM PDT 24
Peak memory 195180 kb
Host smart-c5b8e3d2-b8a4-4af2-9210-30eb02fad049
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269033868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3269033868
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3201512800
Short name T750
Test name
Test status
Simulation time 216426185 ps
CPU time 0.59 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 195048 kb
Host smart-004bcd0b-4a9f-421f-94e4-8aeeca28f14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201512800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3201512800
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3025908422
Short name T807
Test name
Test status
Simulation time 338282828 ps
CPU time 0.74 seconds
Started Aug 01 05:14:48 PM PDT 24
Finished Aug 01 05:14:49 PM PDT 24
Peak memory 195452 kb
Host smart-68722a6c-bbbe-49cc-8f21-6721bc915487
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025908422 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3025908422
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2778592356
Short name T725
Test name
Test status
Simulation time 512356385 ps
CPU time 2.31 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:49 PM PDT 24
Peak memory 198748 kb
Host smart-2258aa69-4c0a-4870-93b0-c92a44f06351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778592356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2778592356
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3837631299
Short name T784
Test name
Test status
Simulation time 17285454 ps
CPU time 0.63 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194432 kb
Host smart-2a3a1c23-c9be-484a-a025-7c56387f73c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837631299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3837631299
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1006845555
Short name T712
Test name
Test status
Simulation time 37134039 ps
CPU time 0.59 seconds
Started Aug 01 05:15:20 PM PDT 24
Finished Aug 01 05:15:21 PM PDT 24
Peak memory 194400 kb
Host smart-75f37b76-d0c1-4b5a-8e12-8e099bdf620a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006845555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1006845555
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4144905415
Short name T720
Test name
Test status
Simulation time 91518243 ps
CPU time 0.57 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194384 kb
Host smart-5be0414f-4552-41f9-8915-52e0f3c2eddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144905415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4144905415
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1760509367
Short name T826
Test name
Test status
Simulation time 50155360 ps
CPU time 0.58 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:15 PM PDT 24
Peak memory 194400 kb
Host smart-a98c5231-4bfe-43e9-bce2-f772f146f5cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760509367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1760509367
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3649221574
Short name T802
Test name
Test status
Simulation time 15904628 ps
CPU time 0.61 seconds
Started Aug 01 05:15:21 PM PDT 24
Finished Aug 01 05:15:22 PM PDT 24
Peak memory 194560 kb
Host smart-4771b590-e5dc-4b56-a4a4-830443762ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649221574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3649221574
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1654319689
Short name T831
Test name
Test status
Simulation time 47258467 ps
CPU time 0.6 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 194428 kb
Host smart-ad074661-24be-4439-8cf6-8d1a25527f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654319689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1654319689
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.4008155762
Short name T770
Test name
Test status
Simulation time 42951954 ps
CPU time 0.62 seconds
Started Aug 01 05:15:20 PM PDT 24
Finished Aug 01 05:15:21 PM PDT 24
Peak memory 194436 kb
Host smart-adaf341b-95bc-4b72-9b7c-6acadd392762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008155762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4008155762
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1051578193
Short name T786
Test name
Test status
Simulation time 28683666 ps
CPU time 0.61 seconds
Started Aug 01 05:15:16 PM PDT 24
Finished Aug 01 05:15:17 PM PDT 24
Peak memory 195040 kb
Host smart-876e3e40-98af-4aba-a6f8-988e520a58c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051578193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1051578193
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.610506695
Short name T825
Test name
Test status
Simulation time 34932130 ps
CPU time 0.55 seconds
Started Aug 01 05:15:15 PM PDT 24
Finished Aug 01 05:15:16 PM PDT 24
Peak memory 194256 kb
Host smart-72e15c36-bf4c-48bd-880f-4bd885ed8265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610506695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.610506695
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1058573322
Short name T836
Test name
Test status
Simulation time 23304219 ps
CPU time 0.61 seconds
Started Aug 01 05:15:17 PM PDT 24
Finished Aug 01 05:15:18 PM PDT 24
Peak memory 194436 kb
Host smart-790f814a-b947-4795-a095-5652cac08b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058573322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1058573322
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.906595509
Short name T733
Test name
Test status
Simulation time 21969064 ps
CPU time 0.69 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 197724 kb
Host smart-53c433ed-943f-4c93-9899-386d69850be4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906595509 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.906595509
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3312221215
Short name T760
Test name
Test status
Simulation time 30109176 ps
CPU time 0.62 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 195228 kb
Host smart-d7b9b654-cf35-4e5f-b89f-a8eb2744266e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312221215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3312221215
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.172892864
Short name T795
Test name
Test status
Simulation time 13767523 ps
CPU time 0.58 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 194308 kb
Host smart-c61a80f5-a611-4711-81a2-aff90490838b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172892864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.172892864
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3323372855
Short name T99
Test name
Test status
Simulation time 31068269 ps
CPU time 0.82 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 196916 kb
Host smart-83f90b51-e937-4014-b33c-6fc35df1d4e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323372855 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3323372855
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.943850249
Short name T788
Test name
Test status
Simulation time 415350104 ps
CPU time 2.26 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 198820 kb
Host smart-bc0a25ea-9a38-4b1b-9640-4beafb1160f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943850249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.943850249
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3309943577
Short name T42
Test name
Test status
Simulation time 43848720 ps
CPU time 0.85 seconds
Started Aug 01 05:14:50 PM PDT 24
Finished Aug 01 05:14:51 PM PDT 24
Peak memory 197808 kb
Host smart-7ec58543-1b4d-4404-b582-edfe426b9a15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309943577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3309943577
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1673885453
Short name T763
Test name
Test status
Simulation time 53193952 ps
CPU time 1.66 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 198764 kb
Host smart-22d69fb8-4033-4075-a7a0-cb1bbe65c9f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673885453 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1673885453
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.4238695043
Short name T772
Test name
Test status
Simulation time 14541391 ps
CPU time 0.58 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 193904 kb
Host smart-e4334942-8752-4dfc-b7f6-f4d0147a5c6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238695043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.4238695043
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1951543313
Short name T779
Test name
Test status
Simulation time 28528777 ps
CPU time 0.56 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:44 PM PDT 24
Peak memory 194344 kb
Host smart-8c60f92f-c29a-4e6c-92c0-7784b0fda42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951543313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1951543313
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2572689928
Short name T816
Test name
Test status
Simulation time 22637390 ps
CPU time 0.85 seconds
Started Aug 01 05:14:52 PM PDT 24
Finished Aug 01 05:14:53 PM PDT 24
Peak memory 197036 kb
Host smart-9e787799-7157-4442-b9fa-4e42a96dcc5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572689928 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2572689928
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3438899738
Short name T736
Test name
Test status
Simulation time 77450994 ps
CPU time 1.68 seconds
Started Aug 01 05:14:47 PM PDT 24
Finished Aug 01 05:14:49 PM PDT 24
Peak memory 198760 kb
Host smart-eea0b318-821d-49a5-b923-d1247b4b493b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438899738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3438899738
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4262557242
Short name T34
Test name
Test status
Simulation time 441845779 ps
CPU time 1.42 seconds
Started Aug 01 05:14:53 PM PDT 24
Finished Aug 01 05:14:55 PM PDT 24
Peak memory 198620 kb
Host smart-72b2e521-0910-4d54-9601-0a0a4640f115
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262557242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4262557242
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.333119999
Short name T768
Test name
Test status
Simulation time 69372797 ps
CPU time 1.01 seconds
Started Aug 01 05:14:50 PM PDT 24
Finished Aug 01 05:14:51 PM PDT 24
Peak memory 198564 kb
Host smart-143f5d21-a46e-4662-a54f-47bdb1eb1fb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333119999 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.333119999
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3501957500
Short name T752
Test name
Test status
Simulation time 13214093 ps
CPU time 0.56 seconds
Started Aug 01 05:14:50 PM PDT 24
Finished Aug 01 05:14:51 PM PDT 24
Peak memory 194084 kb
Host smart-da3c3102-f741-4a13-a70c-0846fea271ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501957500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3501957500
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2443559047
Short name T800
Test name
Test status
Simulation time 31987454 ps
CPU time 0.56 seconds
Started Aug 01 05:14:49 PM PDT 24
Finished Aug 01 05:14:50 PM PDT 24
Peak memory 194408 kb
Host smart-04b7871f-c627-403b-93b5-79593418da58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443559047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2443559047
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3435496797
Short name T787
Test name
Test status
Simulation time 25663420 ps
CPU time 0.75 seconds
Started Aug 01 05:14:47 PM PDT 24
Finished Aug 01 05:14:48 PM PDT 24
Peak memory 196728 kb
Host smart-9070d83e-1d42-4d75-84a0-54a8314f5bf9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435496797 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3435496797
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1067869804
Short name T751
Test name
Test status
Simulation time 413280788 ps
CPU time 1.87 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 198664 kb
Host smart-3a1dbdb8-280e-4ead-997d-b5ece4c8e431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067869804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1067869804
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2428530851
Short name T737
Test name
Test status
Simulation time 154344245 ps
CPU time 0.82 seconds
Started Aug 01 05:14:46 PM PDT 24
Finished Aug 01 05:14:47 PM PDT 24
Peak memory 197588 kb
Host smart-91962f08-cf45-417f-8629-15cacad8be36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428530851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2428530851
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3017198955
Short name T759
Test name
Test status
Simulation time 37025564 ps
CPU time 0.96 seconds
Started Aug 01 05:14:45 PM PDT 24
Finished Aug 01 05:14:46 PM PDT 24
Peak memory 198520 kb
Host smart-6b7593d5-c187-4056-804d-e06a2905b6c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017198955 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3017198955
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2198849310
Short name T729
Test name
Test status
Simulation time 18422080 ps
CPU time 0.59 seconds
Started Aug 01 05:14:48 PM PDT 24
Finished Aug 01 05:14:49 PM PDT 24
Peak memory 195404 kb
Host smart-0c9f8a70-a185-4157-95d6-eec0cd688187
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198849310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2198849310
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3479137842
Short name T799
Test name
Test status
Simulation time 36942932 ps
CPU time 0.59 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 194392 kb
Host smart-6c9d03bb-9a3c-4f03-91d3-2cdf98324420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479137842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3479137842
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.474993465
Short name T793
Test name
Test status
Simulation time 69213577 ps
CPU time 0.64 seconds
Started Aug 01 05:14:44 PM PDT 24
Finished Aug 01 05:14:45 PM PDT 24
Peak memory 195344 kb
Host smart-c64968a6-3990-44f1-823e-13222e8101bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474993465 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.474993465
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1445792867
Short name T719
Test name
Test status
Simulation time 84917460 ps
CPU time 2.21 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:05 PM PDT 24
Peak memory 198616 kb
Host smart-df5394e2-b5ef-47fc-9b19-ef25f4f952e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445792867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1445792867
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1306261330
Short name T790
Test name
Test status
Simulation time 87706393 ps
CPU time 0.86 seconds
Started Aug 01 05:14:47 PM PDT 24
Finished Aug 01 05:14:48 PM PDT 24
Peak memory 197540 kb
Host smart-8eec345e-ff00-4aa0-822b-b4bade9108df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306261330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1306261330
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2820238018
Short name T801
Test name
Test status
Simulation time 329902594 ps
CPU time 1.44 seconds
Started Aug 01 05:15:02 PM PDT 24
Finished Aug 01 05:15:04 PM PDT 24
Peak memory 198748 kb
Host smart-beda580d-70a8-4038-b0b9-28f2010ded11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820238018 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2820238018
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1096382153
Short name T90
Test name
Test status
Simulation time 11982080 ps
CPU time 0.62 seconds
Started Aug 01 05:14:59 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 195860 kb
Host smart-f64c5214-8fd5-4f0e-ba29-06d1a659c32d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096382153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1096382153
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3819599052
Short name T716
Test name
Test status
Simulation time 40930981 ps
CPU time 0.59 seconds
Started Aug 01 05:14:58 PM PDT 24
Finished Aug 01 05:14:59 PM PDT 24
Peak memory 194980 kb
Host smart-7834853f-905a-4769-ba38-42a674938add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819599052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3819599052
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.949413764
Short name T813
Test name
Test status
Simulation time 16387030 ps
CPU time 0.68 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 195372 kb
Host smart-721bece7-a316-4c99-8896-d6e3d7a416fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949413764 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.949413764
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3860467800
Short name T714
Test name
Test status
Simulation time 204396945 ps
CPU time 2.95 seconds
Started Aug 01 05:15:03 PM PDT 24
Finished Aug 01 05:15:06 PM PDT 24
Peak memory 198764 kb
Host smart-0ee8daf7-8d1f-42f0-b078-6a275f450c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860467800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3860467800
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1466840676
Short name T41
Test name
Test status
Simulation time 277018686 ps
CPU time 1.09 seconds
Started Aug 01 05:15:01 PM PDT 24
Finished Aug 01 05:15:02 PM PDT 24
Peak memory 198664 kb
Host smart-439736eb-8fb8-4ae8-ad61-88702c15fb72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466840676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1466840676
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1206904347
Short name T196
Test name
Test status
Simulation time 61146974 ps
CPU time 0.7 seconds
Started Aug 01 05:19:46 PM PDT 24
Finished Aug 01 05:19:47 PM PDT 24
Peak memory 196444 kb
Host smart-be1dc9b2-63b4-43c5-98f5-c5d88577d803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206904347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1206904347
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2062243613
Short name T635
Test name
Test status
Simulation time 1905425891 ps
CPU time 25.51 seconds
Started Aug 01 05:19:46 PM PDT 24
Finished Aug 01 05:20:12 PM PDT 24
Peak memory 198520 kb
Host smart-6faf9667-835c-46fe-931f-25da69dbbb3f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062243613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2062243613
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1284929981
Short name T565
Test name
Test status
Simulation time 96522744 ps
CPU time 0.69 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 194804 kb
Host smart-26f51d77-f06e-4848-a8e4-ccf2db7fe2b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284929981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1284929981
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3470921351
Short name T574
Test name
Test status
Simulation time 48436041 ps
CPU time 1.11 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 198348 kb
Host smart-023f9d95-fde6-4f79-8594-06aa1dba0655
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470921351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3470921351
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.120206416
Short name T575
Test name
Test status
Simulation time 59857004 ps
CPU time 0.95 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 195940 kb
Host smart-602dcc5e-5703-4601-a2bf-87b1de3f4389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120206416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.120206416
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.31632009
Short name T617
Test name
Test status
Simulation time 131556703 ps
CPU time 0.72 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 195772 kb
Host smart-0e4a5d06-e1f6-43fd-92e2-92b7de3ed2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31632009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.31632009
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4120805408
Short name T119
Test name
Test status
Simulation time 106663987 ps
CPU time 1.08 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 197100 kb
Host smart-8da19a1b-3026-4b59-b9a2-63e451896f57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120805408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4120805408
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.947578152
Short name T476
Test name
Test status
Simulation time 97310817 ps
CPU time 4.23 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:48 PM PDT 24
Peak memory 198376 kb
Host smart-57442e57-649e-44ce-a429-fa23a35bdbc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947578152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.947578152
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.99705593
Short name T38
Test name
Test status
Simulation time 297588213 ps
CPU time 0.95 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 215336 kb
Host smart-7aed930a-daad-4354-8dee-019465caa6a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99705593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.99705593
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.654329648
Short name T164
Test name
Test status
Simulation time 83003510 ps
CPU time 1.3 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 195980 kb
Host smart-125af4f4-af60-4543-b185-338e8215ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654329648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.654329648
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1811665544
Short name T540
Test name
Test status
Simulation time 35957473 ps
CPU time 0.91 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196860 kb
Host smart-0561909a-afb1-49c2-8901-ae4cd7898266
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811665544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1811665544
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.402852486
Short name T412
Test name
Test status
Simulation time 5491637595 ps
CPU time 136.41 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:21:59 PM PDT 24
Peak memory 198664 kb
Host smart-4d792295-b927-4285-af47-6acd128d520c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402852486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.402852486
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1086301820
Short name T377
Test name
Test status
Simulation time 25407589 ps
CPU time 0.65 seconds
Started Aug 01 05:19:55 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 194548 kb
Host smart-d767fd4e-53ab-4d65-ab8f-621eed0926ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086301820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1086301820
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2730780849
Short name T579
Test name
Test status
Simulation time 46957157 ps
CPU time 0.94 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196804 kb
Host smart-972c481e-f96f-425d-bce7-023c4b62690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730780849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2730780849
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4034245304
Short name T54
Test name
Test status
Simulation time 745348807 ps
CPU time 10.77 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:20:04 PM PDT 24
Peak memory 197240 kb
Host smart-aec1eb5f-e8ba-4755-9fd0-d85bf15a37ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034245304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4034245304
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.729354059
Short name T394
Test name
Test status
Simulation time 38474381 ps
CPU time 0.8 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:53 PM PDT 24
Peak memory 196252 kb
Host smart-d3f98556-9bb6-4dad-81ee-5157988b32df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729354059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.729354059
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1018874483
Short name T422
Test name
Test status
Simulation time 63431324 ps
CPU time 0.74 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:53 PM PDT 24
Peak memory 195864 kb
Host smart-e5a5c175-e5ba-48d7-ac94-7c27daa80bdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018874483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1018874483
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2856025221
Short name T455
Test name
Test status
Simulation time 38057591 ps
CPU time 1.58 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 196972 kb
Host smart-812077fd-7ab4-47bf-a4a4-2939bbd2734f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856025221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2856025221
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3833372098
Short name T645
Test name
Test status
Simulation time 167667130 ps
CPU time 2.53 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 197504 kb
Host smart-e3e34161-5ecf-49b8-a8ff-a295dac73683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833372098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3833372098
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2892726824
Short name T204
Test name
Test status
Simulation time 67740586 ps
CPU time 1.37 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 198512 kb
Host smart-86cfad74-110c-4f06-95d3-8f6d9ba6ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892726824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2892726824
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2836993790
Short name T222
Test name
Test status
Simulation time 183851999 ps
CPU time 1.21 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 196524 kb
Host smart-aa0575cb-1288-4107-a99f-4eff9379565b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836993790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2836993790
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2322596972
Short name T674
Test name
Test status
Simulation time 1598808895 ps
CPU time 4.52 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 198560 kb
Host smart-df31afb7-0a2d-42d8-a027-e5f89ca3073a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322596972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2322596972
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3446738774
Short name T49
Test name
Test status
Simulation time 215799117 ps
CPU time 0.79 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 214232 kb
Host smart-4344dae1-bb26-4763-bba3-ba31247472d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446738774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3446738774
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3909879884
Short name T679
Test name
Test status
Simulation time 1065788510 ps
CPU time 1.67 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 197320 kb
Host smart-456c3caf-ecd8-4c6e-9460-e85736f42dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909879884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3909879884
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3747759706
Short name T563
Test name
Test status
Simulation time 30865270 ps
CPU time 0.92 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 197708 kb
Host smart-16abc7fd-5d1e-4c55-949f-0f7d9c6b4423
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747759706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3747759706
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_alert_test.952644127
Short name T545
Test name
Test status
Simulation time 13406098 ps
CPU time 0.58 seconds
Started Aug 01 05:20:22 PM PDT 24
Finished Aug 01 05:20:23 PM PDT 24
Peak memory 194664 kb
Host smart-60d604f2-c98e-4b7b-97b7-c1003cd6c816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952644127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.952644127
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2071101840
Short name T125
Test name
Test status
Simulation time 172655504 ps
CPU time 0.73 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 195780 kb
Host smart-95ce111f-4966-48b9-8d8d-ace574b08685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071101840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2071101840
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1116300573
Short name T262
Test name
Test status
Simulation time 2258846185 ps
CPU time 22.96 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:51 PM PDT 24
Peak memory 198716 kb
Host smart-11e04cd1-b9c6-49fd-8615-1ad120960d17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116300573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1116300573
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3327727978
Short name T373
Test name
Test status
Simulation time 46330858 ps
CPU time 0.81 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 196476 kb
Host smart-5fbe87bb-5f4c-45e7-bd82-7eee237b90f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327727978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3327727978
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.582850586
Short name T396
Test name
Test status
Simulation time 189089988 ps
CPU time 1.48 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 198612 kb
Host smart-672829fa-2ca3-4e0c-9106-532f84099308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582850586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.582850586
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2446165100
Short name T185
Test name
Test status
Simulation time 58654231 ps
CPU time 1.31 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:23 PM PDT 24
Peak memory 197124 kb
Host smart-09cf96d8-0123-4d97-a528-40d947ed6929
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446165100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2446165100
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.136778055
Short name T140
Test name
Test status
Simulation time 135953892 ps
CPU time 2.81 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 197672 kb
Host smart-1b53e7f4-db92-4d50-b449-fe60ed1845fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136778055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
136778055
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.862856502
Short name T393
Test name
Test status
Simulation time 47269487 ps
CPU time 0.69 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 194696 kb
Host smart-a59a9d1e-ed0f-4795-940a-347f03a92919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862856502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.862856502
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.690951286
Short name T490
Test name
Test status
Simulation time 440256634 ps
CPU time 0.78 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 196588 kb
Host smart-1c4c1c54-e7a2-42e2-a0c5-2d156b58b1fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690951286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.690951286
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.548729240
Short name T5
Test name
Test status
Simulation time 126592007 ps
CPU time 1.37 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 198444 kb
Host smart-30cc8b6b-fedc-4345-b075-12f656b542d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548729240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.548729240
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2544572355
Short name T452
Test name
Test status
Simulation time 37184397 ps
CPU time 0.97 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 196104 kb
Host smart-9bfb3847-a681-4ece-b6be-7634f1bbdebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544572355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2544572355
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1695307084
Short name T323
Test name
Test status
Simulation time 136471051 ps
CPU time 1.07 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 197016 kb
Host smart-adf1bd89-7c5a-4856-b2eb-99aab64f1eec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695307084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1695307084
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.773976914
Short name T227
Test name
Test status
Simulation time 6072727688 ps
CPU time 159.35 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 198672 kb
Host smart-636656b2-0745-4dbf-8952-f6ba51fa6bc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773976914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.773976914
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1300260556
Short name T336
Test name
Test status
Simulation time 42736282 ps
CPU time 0.58 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 194308 kb
Host smart-80aa94a9-919f-41cf-8936-38c33d717bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300260556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1300260556
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2418203449
Short name T506
Test name
Test status
Simulation time 161087251 ps
CPU time 0.79 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 195896 kb
Host smart-7c85c2d8-1860-43de-8da0-95d189cf9a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418203449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2418203449
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2347502731
Short name T497
Test name
Test status
Simulation time 7460297565 ps
CPU time 21.62 seconds
Started Aug 01 05:20:18 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 198660 kb
Host smart-3f9f1761-d133-42c1-80de-f1a88ae0c517
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347502731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2347502731
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.701817774
Short name T47
Test name
Test status
Simulation time 94701168 ps
CPU time 0.81 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 196456 kb
Host smart-b8505a2b-c5d7-4e69-ba88-74f47350f7c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701817774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.701817774
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.800323181
Short name T428
Test name
Test status
Simulation time 40198822 ps
CPU time 0.92 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 198016 kb
Host smart-7e165ef4-c336-43e5-8550-755a4efa9f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800323181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.800323181
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.617289407
Short name T15
Test name
Test status
Simulation time 51216489 ps
CPU time 2.25 seconds
Started Aug 01 05:20:18 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 198612 kb
Host smart-d6da3674-5d60-4f72-802c-4adcfcf5ca23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617289407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.617289407
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4279771270
Short name T470
Test name
Test status
Simulation time 71925171 ps
CPU time 2.04 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 196340 kb
Host smart-dcdb3d66-1357-4e82-97a7-0b7188197352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279771270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4279771270
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4250307042
Short name T321
Test name
Test status
Simulation time 25315636 ps
CPU time 0.73 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 195980 kb
Host smart-ca8240cc-eb89-4994-a12d-27c47e35da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250307042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4250307042
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2828081794
Short name T259
Test name
Test status
Simulation time 82448385 ps
CPU time 1.06 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 197220 kb
Host smart-1b2308ee-457b-421a-87fa-7c70c2fb6282
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828081794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2828081794
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2872916939
Short name T568
Test name
Test status
Simulation time 414937946 ps
CPU time 5.35 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:23 PM PDT 24
Peak memory 198524 kb
Host smart-23527747-f495-4264-8f3b-ab566b5f1478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872916939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2872916939
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1267462133
Short name T450
Test name
Test status
Simulation time 222930358 ps
CPU time 1.28 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 196056 kb
Host smart-9ee633cc-9fd6-44b3-840c-a343af96d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267462133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1267462133
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1326788063
Short name T664
Test name
Test status
Simulation time 83053994 ps
CPU time 1.51 seconds
Started Aug 01 05:20:18 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 196008 kb
Host smart-54f39b11-45a4-48b0-841c-69417f7446c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326788063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1326788063
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2230254701
Short name T693
Test name
Test status
Simulation time 9388248827 ps
CPU time 132.33 seconds
Started Aug 01 05:20:22 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 198712 kb
Host smart-844aa22e-c59f-4951-9b49-27b942765258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230254701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2230254701
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.494607081
Short name T136
Test name
Test status
Simulation time 23493326 ps
CPU time 0.54 seconds
Started Aug 01 05:20:23 PM PDT 24
Finished Aug 01 05:20:24 PM PDT 24
Peak memory 194508 kb
Host smart-81f1b1aa-34ea-4a5e-a5bb-6f23de1d491a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494607081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.494607081
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2589393733
Short name T198
Test name
Test status
Simulation time 25042732 ps
CPU time 0.79 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 195212 kb
Host smart-e0d9e5bd-2327-4663-afbf-6213fdf3a109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589393733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2589393733
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2502946287
Short name T409
Test name
Test status
Simulation time 1866617709 ps
CPU time 15.16 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:34 PM PDT 24
Peak memory 196840 kb
Host smart-06ba2e18-193b-499a-8a90-ccd2d08abeae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502946287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2502946287
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3439514044
Short name T576
Test name
Test status
Simulation time 48988293 ps
CPU time 0.87 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 196524 kb
Host smart-9341f068-6c07-4695-8622-de2bf5285a3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439514044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3439514044
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2017035622
Short name T681
Test name
Test status
Simulation time 26688702 ps
CPU time 0.96 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 197020 kb
Host smart-3e711bf0-6aef-438e-8435-ef01950058ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017035622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2017035622
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1800633917
Short name T522
Test name
Test status
Simulation time 22310149 ps
CPU time 0.96 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 196276 kb
Host smart-d6da0982-f706-4f02-9fa1-b5552b955782
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800633917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1800633917
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.133381354
Short name T462
Test name
Test status
Simulation time 219369989 ps
CPU time 1.92 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:21 PM PDT 24
Peak memory 197212 kb
Host smart-aa4000ef-a5d0-458c-a55d-5209237fd42b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133381354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
133381354
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.694880826
Short name T121
Test name
Test status
Simulation time 21233754 ps
CPU time 0.83 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 197740 kb
Host smart-77c7588d-770d-4d86-b943-f4b01e1761b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694880826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.694880826
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.751695385
Short name T577
Test name
Test status
Simulation time 213606692 ps
CPU time 0.92 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 196380 kb
Host smart-dad4cc17-4b8d-4438-9c3b-08542dc80c84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751695385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.751695385
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.602598513
Short name T305
Test name
Test status
Simulation time 298397400 ps
CPU time 3.56 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:25 PM PDT 24
Peak memory 198460 kb
Host smart-efd1a6bc-938e-4941-978f-0e1e658cc5ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602598513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.602598513
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.249951376
Short name T148
Test name
Test status
Simulation time 31891071 ps
CPU time 0.97 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 196052 kb
Host smart-9d6a78cf-76b0-4353-90d9-30a4d291aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249951376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.249951376
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3749094064
Short name T532
Test name
Test status
Simulation time 28401228 ps
CPU time 0.88 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 196880 kb
Host smart-a88ca940-ef94-4c47-a814-544ab630c811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749094064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3749094064
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4033744479
Short name T410
Test name
Test status
Simulation time 6220929792 ps
CPU time 82.02 seconds
Started Aug 01 05:20:22 PM PDT 24
Finished Aug 01 05:21:44 PM PDT 24
Peak memory 198788 kb
Host smart-147f6cd3-36ff-47db-9f20-635647c1e601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033744479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4033744479
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1695510447
Short name T669
Test name
Test status
Simulation time 20295117 ps
CPU time 0.55 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 194372 kb
Host smart-c8fb1f5a-ee84-40cf-b067-5699e985b2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695510447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1695510447
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2904092002
Short name T130
Test name
Test status
Simulation time 91959521 ps
CPU time 0.95 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:29 PM PDT 24
Peak memory 196492 kb
Host smart-2a342c6f-78f1-4046-bdf8-5dd0b0a5b1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904092002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2904092002
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3367728145
Short name T147
Test name
Test status
Simulation time 198753253 ps
CPU time 10.62 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:39 PM PDT 24
Peak memory 196752 kb
Host smart-e6335e30-45ea-455a-b743-37a3c2e38671
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367728145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3367728145
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.431633545
Short name T601
Test name
Test status
Simulation time 51851821 ps
CPU time 0.86 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 196448 kb
Host smart-99d619e5-0bef-450a-8f32-bf100b71b0d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431633545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.431633545
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.572397924
Short name T266
Test name
Test status
Simulation time 71592747 ps
CPU time 1.09 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 197088 kb
Host smart-7c995784-2b83-4cd4-b13a-36a07a7e6520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572397924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.572397924
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3356830110
Short name T460
Test name
Test status
Simulation time 58711044 ps
CPU time 2.2 seconds
Started Aug 01 05:20:24 PM PDT 24
Finished Aug 01 05:20:27 PM PDT 24
Peak memory 198704 kb
Host smart-d8d11044-dc1d-469f-90c6-b991163667e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356830110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3356830110
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1520361704
Short name T414
Test name
Test status
Simulation time 76383736 ps
CPU time 1.92 seconds
Started Aug 01 05:20:22 PM PDT 24
Finished Aug 01 05:20:24 PM PDT 24
Peak memory 196648 kb
Host smart-f1f71191-c2a6-44d8-b967-408ea3f1118e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520361704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1520361704
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1776175538
Short name T71
Test name
Test status
Simulation time 247743533 ps
CPU time 1.2 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 196552 kb
Host smart-960d8432-bd46-4d1d-af83-d06992543e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776175538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1776175538
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2203472049
Short name T251
Test name
Test status
Simulation time 15583778 ps
CPU time 0.66 seconds
Started Aug 01 05:20:24 PM PDT 24
Finished Aug 01 05:20:25 PM PDT 24
Peak memory 194844 kb
Host smart-803af13a-bd1c-4aab-8aa8-bf4bb30d77e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203472049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2203472049
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3453475059
Short name T329
Test name
Test status
Simulation time 431202947 ps
CPU time 5.65 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:36 PM PDT 24
Peak memory 198488 kb
Host smart-32ae7c21-ba73-4233-b003-8dd3eb5d93da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453475059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3453475059
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1106989392
Short name T536
Test name
Test status
Simulation time 36897115 ps
CPU time 1 seconds
Started Aug 01 05:20:24 PM PDT 24
Finished Aug 01 05:20:25 PM PDT 24
Peak memory 197076 kb
Host smart-890f4e1a-a10e-4525-b18c-4facc3d08850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106989392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1106989392
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1831401006
Short name T221
Test name
Test status
Simulation time 37829322 ps
CPU time 0.84 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:20:21 PM PDT 24
Peak memory 195808 kb
Host smart-299cda76-6fbf-4b89-934f-2d2e431d8c31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831401006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1831401006
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2006785236
Short name T253
Test name
Test status
Simulation time 8800281591 ps
CPU time 61.92 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 198732 kb
Host smart-d9044939-d6f6-4dc3-bc8f-aed6e7d264be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006785236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2006785236
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3370303048
Short name T600
Test name
Test status
Simulation time 88039984378 ps
CPU time 995.6 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:37:06 PM PDT 24
Peak memory 198816 kb
Host smart-e193be7a-602b-4f01-9641-5f6447d6750a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3370303048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3370303048
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4240911299
Short name T510
Test name
Test status
Simulation time 28112707 ps
CPU time 0.59 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 194692 kb
Host smart-0fee4dbf-0482-4dbb-bef3-3b589e60291f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240911299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4240911299
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.580175012
Short name T360
Test name
Test status
Simulation time 62205484 ps
CPU time 0.69 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:28 PM PDT 24
Peak memory 195312 kb
Host smart-884b9178-87a9-475f-b03f-45ab805ad971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580175012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.580175012
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1416048113
Short name T498
Test name
Test status
Simulation time 1106749911 ps
CPU time 6.81 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:34 PM PDT 24
Peak memory 197048 kb
Host smart-63abb383-e611-4dc5-84d6-8cdeac3b4cc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416048113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1416048113
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1650328805
Short name T649
Test name
Test status
Simulation time 629910002 ps
CPU time 1.05 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 197160 kb
Host smart-449a350b-543e-490e-b4c4-98fe54bb5475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650328805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1650328805
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3064194649
Short name T219
Test name
Test status
Simulation time 290983150 ps
CPU time 0.75 seconds
Started Aug 01 05:20:33 PM PDT 24
Finished Aug 01 05:20:34 PM PDT 24
Peak memory 196732 kb
Host smart-fe10ef58-3614-4c5c-a419-a7b27a17740d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064194649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3064194649
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.154046240
Short name T28
Test name
Test status
Simulation time 44965116 ps
CPU time 1.73 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:33 PM PDT 24
Peak memory 198524 kb
Host smart-78ae233b-ede2-43fe-b3fc-eaf01ced9c1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154046240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.154046240
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3682001156
Short name T16
Test name
Test status
Simulation time 604357753 ps
CPU time 2.74 seconds
Started Aug 01 05:20:27 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 197668 kb
Host smart-2326f1e6-35f1-4030-b63a-21954d107dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682001156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3682001156
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2798417576
Short name T648
Test name
Test status
Simulation time 75753853 ps
CPU time 1.04 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 197272 kb
Host smart-443808f8-b415-4f5a-9ed3-73dc858ffdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798417576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2798417576
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2878554439
Short name T469
Test name
Test status
Simulation time 34906186 ps
CPU time 1.26 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 198500 kb
Host smart-5e435e2e-0299-4986-881e-e2e901cd05ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878554439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2878554439
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2822764171
Short name T272
Test name
Test status
Simulation time 229020033 ps
CPU time 5.29 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:34 PM PDT 24
Peak memory 198468 kb
Host smart-2747327e-0f26-43fd-8548-1b9d82c7b07f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822764171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2822764171
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3524538504
Short name T171
Test name
Test status
Simulation time 212883593 ps
CPU time 1.17 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:20:33 PM PDT 24
Peak memory 196088 kb
Host smart-c6305ecc-971a-4feb-967f-b93437883fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524538504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3524538504
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1277251886
Short name T491
Test name
Test status
Simulation time 43900972 ps
CPU time 1.28 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 196680 kb
Host smart-ea209dc0-e54f-488b-a05c-cb6ea7416626
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277251886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1277251886
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3893691979
Short name T692
Test name
Test status
Simulation time 51199419798 ps
CPU time 174.19 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:23:25 PM PDT 24
Peak memory 198680 kb
Host smart-9656258f-f8c7-441e-b13a-136647ef5267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893691979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3893691979
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.43705255
Short name T513
Test name
Test status
Simulation time 19282395 ps
CPU time 0.59 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 195372 kb
Host smart-fdd01e1b-bcc6-4014-80d3-0ad27ae4b119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43705255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.43705255
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1219377089
Short name T420
Test name
Test status
Simulation time 30339970 ps
CPU time 0.69 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 194740 kb
Host smart-aebb41a8-d422-4914-be75-4391f7a292e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219377089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1219377089
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4149994718
Short name T190
Test name
Test status
Simulation time 1248529438 ps
CPU time 8.75 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:38 PM PDT 24
Peak memory 195992 kb
Host smart-edba4bea-411a-4bf8-9b3c-5d219bbd8e7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149994718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4149994718
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.950638650
Short name T182
Test name
Test status
Simulation time 25450308 ps
CPU time 0.64 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 194900 kb
Host smart-ac12b6f0-2342-4a04-8b37-adf0153d0cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950638650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.950638650
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.802157222
Short name T369
Test name
Test status
Simulation time 28138178 ps
CPU time 0.9 seconds
Started Aug 01 05:20:36 PM PDT 24
Finished Aug 01 05:20:37 PM PDT 24
Peak memory 197140 kb
Host smart-496c10c6-cd2e-4791-b57d-f4b1dc680718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802157222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.802157222
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1798140445
Short name T695
Test name
Test status
Simulation time 406674265 ps
CPU time 3.63 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 196784 kb
Host smart-6a1cea08-880a-44c2-aab0-cdfa8736c6a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798140445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1798140445
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4015808692
Short name T254
Test name
Test status
Simulation time 314905484 ps
CPU time 3.25 seconds
Started Aug 01 05:20:26 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 196404 kb
Host smart-f12c8e57-4c2e-42a8-b0b7-8cb6255b9ca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015808692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4015808692
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3254105888
Short name T211
Test name
Test status
Simulation time 55080919 ps
CPU time 0.7 seconds
Started Aug 01 05:20:34 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 195868 kb
Host smart-1fe39c07-8469-471e-a179-29e3b259e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254105888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3254105888
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3372876335
Short name T458
Test name
Test status
Simulation time 56898872 ps
CPU time 0.8 seconds
Started Aug 01 05:20:26 PM PDT 24
Finished Aug 01 05:20:27 PM PDT 24
Peak memory 195800 kb
Host smart-8e0caa1d-7dd3-473e-a74f-a9be256a91dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372876335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3372876335
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1824903728
Short name T698
Test name
Test status
Simulation time 59908443 ps
CPU time 1.07 seconds
Started Aug 01 05:20:34 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 197592 kb
Host smart-c2e66efe-b477-42b2-a30d-b3ffa82bfd13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824903728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1824903728
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1598542603
Short name T667
Test name
Test status
Simulation time 451929137 ps
CPU time 0.83 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 195640 kb
Host smart-0742b7ce-621a-4bd3-b077-3d4c21fc73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598542603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1598542603
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2245305761
Short name T612
Test name
Test status
Simulation time 43190607 ps
CPU time 0.99 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 196352 kb
Host smart-bae97ed0-5d2d-4087-8aef-853fbc07108d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245305761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2245305761
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2912490726
Short name T524
Test name
Test status
Simulation time 11428922559 ps
CPU time 143.1 seconds
Started Aug 01 05:20:35 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 198688 kb
Host smart-25d370bb-7afd-4012-971d-691748b022c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912490726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2912490726
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1727425487
Short name T63
Test name
Test status
Simulation time 80549721324 ps
CPU time 1527.54 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:45:59 PM PDT 24
Peak memory 198904 kb
Host smart-9ba05508-74f5-4a12-a003-ffbd1af1b05a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1727425487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1727425487
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.225266555
Short name T461
Test name
Test status
Simulation time 42601107 ps
CPU time 0.56 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 194460 kb
Host smart-f86f31a6-f751-4f7e-9edb-f4ea306d0fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225266555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.225266555
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4290095700
Short name T134
Test name
Test status
Simulation time 53431694 ps
CPU time 0.98 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 196256 kb
Host smart-a72edd42-775f-4270-b76c-060477500ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290095700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4290095700
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2852006090
Short name T123
Test name
Test status
Simulation time 4246998996 ps
CPU time 24.69 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:53 PM PDT 24
Peak memory 197268 kb
Host smart-06f23874-4094-4ad7-9284-1ceaaa4c96d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852006090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2852006090
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.206561487
Short name T230
Test name
Test status
Simulation time 17961021 ps
CPU time 0.63 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 194824 kb
Host smart-aa074762-7296-412f-8332-496515ff9978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206561487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.206561487
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3002141583
Short name T628
Test name
Test status
Simulation time 161411486 ps
CPU time 1.32 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 197608 kb
Host smart-f32b1896-f05d-424c-8fd5-a520517119f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002141583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3002141583
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2017746304
Short name T626
Test name
Test status
Simulation time 56983135 ps
CPU time 1.24 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:20:33 PM PDT 24
Peak memory 196744 kb
Host smart-c5e68009-5d83-4745-99d8-ac2b0db14723
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017746304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2017746304
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.430403331
Short name T685
Test name
Test status
Simulation time 436474362 ps
CPU time 3.16 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 197596 kb
Host smart-c8ade113-3f02-4e67-982c-8ac58799ffcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430403331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
430403331
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1341724831
Short name T690
Test name
Test status
Simulation time 162370639 ps
CPU time 0.95 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:20:33 PM PDT 24
Peak memory 196548 kb
Host smart-55a9f940-46a7-4ab6-b720-13fcea0d6c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341724831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1341724831
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3637504568
Short name T183
Test name
Test status
Simulation time 91197351 ps
CPU time 0.67 seconds
Started Aug 01 05:20:28 PM PDT 24
Finished Aug 01 05:20:29 PM PDT 24
Peak memory 194808 kb
Host smart-beee50e4-7b04-4d67-9452-8b311515a172
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637504568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3637504568
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3695371478
Short name T295
Test name
Test status
Simulation time 254501186 ps
CPU time 4.11 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 198508 kb
Host smart-14012ac2-273f-4961-8db8-8a68bd682ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695371478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3695371478
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2173825893
Short name T700
Test name
Test status
Simulation time 267998737 ps
CPU time 0.88 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 197564 kb
Host smart-52a6a860-74c4-4739-8f78-cee3ce354469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173825893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2173825893
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.155771091
Short name T379
Test name
Test status
Simulation time 160289639 ps
CPU time 1.24 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 197268 kb
Host smart-bf765a5f-0101-4d2a-a7d8-3e843bbc7c02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155771091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.155771091
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.612326790
Short name T159
Test name
Test status
Simulation time 7562146594 ps
CPU time 183.23 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:23:36 PM PDT 24
Peak memory 198712 kb
Host smart-ac0a4713-49e5-4e28-b90f-802f5a46da8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612326790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.612326790
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2414980925
Short name T434
Test name
Test status
Simulation time 24443648 ps
CPU time 0.62 seconds
Started Aug 01 05:20:27 PM PDT 24
Finished Aug 01 05:20:28 PM PDT 24
Peak memory 194420 kb
Host smart-98a7adec-7386-4526-aa1a-3333c46492ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414980925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2414980925
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2742919923
Short name T382
Test name
Test status
Simulation time 30817545 ps
CPU time 0.91 seconds
Started Aug 01 05:20:35 PM PDT 24
Finished Aug 01 05:20:36 PM PDT 24
Peak memory 196376 kb
Host smart-bf8b7905-4165-4372-ac1a-a5a6aeac90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742919923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2742919923
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1468567787
Short name T435
Test name
Test status
Simulation time 1228479794 ps
CPU time 15.37 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 196060 kb
Host smart-9a6cc407-17dc-42a2-9765-2b380e64d144
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468567787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1468567787
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2050565765
Short name T542
Test name
Test status
Simulation time 96564487 ps
CPU time 0.67 seconds
Started Aug 01 05:20:30 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 195652 kb
Host smart-fff1bb11-9d7e-4bf1-a2cc-a01fc3a04564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050565765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2050565765
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3516052401
Short name T389
Test name
Test status
Simulation time 124170525 ps
CPU time 0.98 seconds
Started Aug 01 05:20:38 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 197120 kb
Host smart-7aa91d08-029b-4df0-8211-d70b7c762ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516052401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3516052401
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2295382205
Short name T646
Test name
Test status
Simulation time 49890552 ps
CPU time 1.17 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:31 PM PDT 24
Peak memory 197852 kb
Host smart-9bb35b7f-75dd-47b9-94ca-37dbf71e24f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295382205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2295382205
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.587678017
Short name T291
Test name
Test status
Simulation time 323094236 ps
CPU time 1.4 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 196268 kb
Host smart-8ed19e69-cc73-4206-8275-98f988c63042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587678017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
587678017
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3556021618
Short name T156
Test name
Test status
Simulation time 255149600 ps
CPU time 1.19 seconds
Started Aug 01 05:20:26 PM PDT 24
Finished Aug 01 05:20:27 PM PDT 24
Peak memory 196376 kb
Host smart-fd017de8-56a5-4ed6-8a6e-10384bda49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556021618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3556021618
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.634812269
Short name T362
Test name
Test status
Simulation time 19084430 ps
CPU time 0.67 seconds
Started Aug 01 05:20:34 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 194780 kb
Host smart-4e6eda2a-1109-401b-b9ba-99312f5e3ab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634812269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.634812269
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.857293426
Short name T215
Test name
Test status
Simulation time 197792884 ps
CPU time 2.02 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:34 PM PDT 24
Peak memory 198524 kb
Host smart-1b75a908-a3d3-4c4e-ab3a-83f05d74fe60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857293426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.857293426
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3056982858
Short name T571
Test name
Test status
Simulation time 198164309 ps
CPU time 0.86 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 196932 kb
Host smart-e37e5794-de68-4a24-80aa-1e5caee66581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056982858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3056982858
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3644206911
Short name T558
Test name
Test status
Simulation time 41228185 ps
CPU time 0.91 seconds
Started Aug 01 05:20:31 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 195784 kb
Host smart-775733c8-a036-4e63-866d-16063ab76499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644206911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3644206911
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3373567810
Short name T706
Test name
Test status
Simulation time 2409236260 ps
CPU time 31.5 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198584 kb
Host smart-794a98fc-79a2-4069-b99f-538b19e8c5a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373567810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3373567810
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1147788473
Short name T62
Test name
Test status
Simulation time 96063922206 ps
CPU time 658.2 seconds
Started Aug 01 05:20:34 PM PDT 24
Finished Aug 01 05:31:33 PM PDT 24
Peak memory 198836 kb
Host smart-30b0456d-502b-4302-bdf6-7b0b6ed6bbca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1147788473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1147788473
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.587148866
Short name T197
Test name
Test status
Simulation time 37586167 ps
CPU time 0.59 seconds
Started Aug 01 05:20:40 PM PDT 24
Finished Aug 01 05:20:41 PM PDT 24
Peak memory 194660 kb
Host smart-a638c555-852e-471a-93ad-717d6a1003a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587148866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.587148866
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.816328190
Short name T386
Test name
Test status
Simulation time 21997005 ps
CPU time 0.62 seconds
Started Aug 01 05:20:32 PM PDT 24
Finished Aug 01 05:20:32 PM PDT 24
Peak memory 194468 kb
Host smart-fa5fcbff-1f53-4525-9ea8-2b0b832bcbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816328190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.816328190
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1701233421
Short name T133
Test name
Test status
Simulation time 271452845 ps
CPU time 5.55 seconds
Started Aug 01 05:20:40 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 197692 kb
Host smart-39f2bdf1-1df4-4e2f-86ab-693441f7541a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701233421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1701233421
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.901710045
Short name T51
Test name
Test status
Simulation time 25019187 ps
CPU time 0.63 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 194828 kb
Host smart-840ccfc0-36e8-4d5d-ae9f-7ce74bd2e9b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901710045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.901710045
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2259015309
Short name T344
Test name
Test status
Simulation time 37340658 ps
CPU time 1.11 seconds
Started Aug 01 05:20:37 PM PDT 24
Finished Aug 01 05:20:38 PM PDT 24
Peak memory 197168 kb
Host smart-b20486ce-c511-4e03-a36e-1cfcac8203a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259015309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2259015309
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2794407014
Short name T614
Test name
Test status
Simulation time 70531683 ps
CPU time 2.91 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:45 PM PDT 24
Peak memory 198648 kb
Host smart-44094fe4-4477-496d-90ec-0dc971601bac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794407014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2794407014
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3820261508
Short name T703
Test name
Test status
Simulation time 254376117 ps
CPU time 3.7 seconds
Started Aug 01 05:20:37 PM PDT 24
Finished Aug 01 05:20:41 PM PDT 24
Peak memory 196924 kb
Host smart-69f9220f-1a26-4cd4-b532-218e76b50b53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820261508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3820261508
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3800317723
Short name T566
Test name
Test status
Simulation time 37602560 ps
CPU time 0.88 seconds
Started Aug 01 05:20:29 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 196392 kb
Host smart-7fc162da-57bf-403e-b6de-5cef7a1afc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800317723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3800317723
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1783792923
Short name T24
Test name
Test status
Simulation time 137004320 ps
CPU time 1.23 seconds
Started Aug 01 05:20:33 PM PDT 24
Finished Aug 01 05:20:35 PM PDT 24
Peak memory 197516 kb
Host smart-8b45b123-8057-47dd-8220-7bec37fcc1ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783792923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1783792923
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.497655509
Short name T361
Test name
Test status
Simulation time 74856466 ps
CPU time 1.14 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 198468 kb
Host smart-02e7d4ce-ad10-4d9f-8678-14a7258dfe7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497655509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.497655509
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2317207972
Short name T126
Test name
Test status
Simulation time 142697705 ps
CPU time 0.87 seconds
Started Aug 01 05:20:35 PM PDT 24
Finished Aug 01 05:20:36 PM PDT 24
Peak memory 195808 kb
Host smart-723a2096-d775-4a6b-a9d0-5c44a2c6c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317207972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2317207972
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1450921467
Short name T338
Test name
Test status
Simulation time 106315035 ps
CPU time 0.86 seconds
Started Aug 01 05:20:27 PM PDT 24
Finished Aug 01 05:20:28 PM PDT 24
Peak memory 197560 kb
Host smart-c74069b2-2155-4b34-8876-67176f7741bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450921467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1450921467
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3395737926
Short name T548
Test name
Test status
Simulation time 6438766394 ps
CPU time 165.32 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:23:27 PM PDT 24
Peak memory 198764 kb
Host smart-535d344b-2682-482b-81d3-df4fbd7c2215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395737926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3395737926
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3245053675
Short name T406
Test name
Test status
Simulation time 48592293 ps
CPU time 0.6 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 194668 kb
Host smart-302c8b69-f410-4390-a9fb-69549a18e8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245053675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3245053675
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3859679403
Short name T597
Test name
Test status
Simulation time 66649695 ps
CPU time 0.97 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 196396 kb
Host smart-3d8eefc5-a5a8-4a00-986a-77a2fe5e624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859679403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3859679403
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1947316241
Short name T181
Test name
Test status
Simulation time 100158767 ps
CPU time 3.66 seconds
Started Aug 01 05:20:40 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 196452 kb
Host smart-1fee53b3-6d55-4eee-8daa-bac84c216ed7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947316241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1947316241
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2478199032
Short name T479
Test name
Test status
Simulation time 177426668 ps
CPU time 0.81 seconds
Started Aug 01 05:20:40 PM PDT 24
Finished Aug 01 05:20:41 PM PDT 24
Peak memory 196368 kb
Host smart-7dd4f952-bb51-45a7-b799-446b6f460cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478199032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2478199032
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.281387019
Short name T552
Test name
Test status
Simulation time 89306540 ps
CPU time 1.47 seconds
Started Aug 01 05:20:40 PM PDT 24
Finished Aug 01 05:20:41 PM PDT 24
Peak memory 196292 kb
Host smart-baaf01e6-b02f-4d61-8ae4-4f0d7806ac60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281387019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.281387019
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.793322766
Short name T443
Test name
Test status
Simulation time 472688696 ps
CPU time 3.54 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:20:43 PM PDT 24
Peak memory 198424 kb
Host smart-85e8d957-0639-4943-a741-d54b9389bb1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793322766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.793322766
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2861294935
Short name T397
Test name
Test status
Simulation time 95836262 ps
CPU time 2.33 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 197044 kb
Host smart-ab555029-a1dd-4b65-83e6-a88f14d6dea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861294935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2861294935
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1735780530
Short name T157
Test name
Test status
Simulation time 133562645 ps
CPU time 1.29 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:43 PM PDT 24
Peak memory 197012 kb
Host smart-7441e899-452f-4c61-993e-333899c3ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735780530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1735780530
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2809009222
Short name T610
Test name
Test status
Simulation time 148012916 ps
CPU time 0.83 seconds
Started Aug 01 05:20:46 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 195944 kb
Host smart-635790f2-01ec-4343-a3a8-5437b7a9ee4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809009222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2809009222
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3275038480
Short name T10
Test name
Test status
Simulation time 896949896 ps
CPU time 4.88 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 198396 kb
Host smart-e0b6ee81-a00c-4964-8b5c-852180e898d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275038480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3275038480
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3328257191
Short name T331
Test name
Test status
Simulation time 22138263 ps
CPU time 0.7 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:41 PM PDT 24
Peak memory 194624 kb
Host smart-3ab21d2c-e75d-4404-8fd2-e0dffe77a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328257191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3328257191
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2926876242
Short name T352
Test name
Test status
Simulation time 52013694 ps
CPU time 1.03 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 196964 kb
Host smart-d6f3b461-f909-4659-ac47-b38d816c2594
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926876242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2926876242
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3049685384
Short name T500
Test name
Test status
Simulation time 11275910348 ps
CPU time 134.55 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:22:54 PM PDT 24
Peak memory 198628 kb
Host smart-1f3f169a-763f-4820-893c-aaf7b48d4c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049685384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3049685384
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.787960168
Short name T656
Test name
Test status
Simulation time 38412196 ps
CPU time 0.55 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:19:52 PM PDT 24
Peak memory 194440 kb
Host smart-dcda8d03-db37-422c-857b-29dd235c3059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787960168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.787960168
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.368705727
Short name T283
Test name
Test status
Simulation time 106897612 ps
CPU time 0.82 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:53 PM PDT 24
Peak memory 195904 kb
Host smart-8779c7f5-e400-40fa-85be-559a498c5e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368705727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.368705727
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1299181787
Short name T691
Test name
Test status
Simulation time 1467704772 ps
CPU time 22.9 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:20:14 PM PDT 24
Peak memory 198476 kb
Host smart-2fc13f36-3e1f-49c9-8c99-5b50c4323f9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299181787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1299181787
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1313245888
Short name T527
Test name
Test status
Simulation time 177996867 ps
CPU time 1.1 seconds
Started Aug 01 05:19:56 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 198292 kb
Host smart-d64152e5-22f6-4370-a370-ee4a697002af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313245888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1313245888
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.811333546
Short name T619
Test name
Test status
Simulation time 193427924 ps
CPU time 0.94 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 196424 kb
Host smart-45cd2fb8-e412-4eb3-9533-8c8d0b56f286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811333546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.811333546
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2178144678
Short name T144
Test name
Test status
Simulation time 71539826 ps
CPU time 1.55 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196820 kb
Host smart-dbecc7b0-873b-4feb-b898-0c2aaa1ba847
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178144678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2178144678
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2411032407
Short name T535
Test name
Test status
Simulation time 58622403 ps
CPU time 1.55 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196560 kb
Host smart-04356669-cc66-42af-ad05-e25694b7a5a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411032407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2411032407
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.329586606
Short name T57
Test name
Test status
Simulation time 63732273 ps
CPU time 0.7 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:53 PM PDT 24
Peak memory 194668 kb
Host smart-b5c505b4-71f1-4387-b627-f073ad63f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329586606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.329586606
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.133724315
Short name T707
Test name
Test status
Simulation time 57374609 ps
CPU time 1.32 seconds
Started Aug 01 05:20:00 PM PDT 24
Finished Aug 01 05:20:01 PM PDT 24
Peak memory 197004 kb
Host smart-31ec3748-9e2a-4e5d-833d-c977f075ce13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133724315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.133724315
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3584257824
Short name T376
Test name
Test status
Simulation time 45957189 ps
CPU time 1.84 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 198404 kb
Host smart-22c241b0-441b-4b93-9c00-fde2118e1eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584257824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3584257824
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1420142812
Short name T37
Test name
Test status
Simulation time 38356923 ps
CPU time 0.79 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 215132 kb
Host smart-4caa15d6-8965-4085-a306-7e12f90ff820
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420142812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1420142812
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.941908783
Short name T507
Test name
Test status
Simulation time 43738386 ps
CPU time 1.28 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 197144 kb
Host smart-404561de-f64b-436a-b127-59cdb511a7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941908783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.941908783
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1288570581
Short name T444
Test name
Test status
Simulation time 121525550 ps
CPU time 1.21 seconds
Started Aug 01 05:19:57 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 196024 kb
Host smart-a063ffc1-dcf5-4a81-bc66-a644c800f88a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288570581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1288570581
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4281818686
Short name T392
Test name
Test status
Simulation time 11650980668 ps
CPU time 77.03 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:21:09 PM PDT 24
Peak memory 198716 kb
Host smart-115f1a0b-8e49-40c4-b0dd-a568f7b6796a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281818686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4281818686
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2621378934
Short name T391
Test name
Test status
Simulation time 123245831 ps
CPU time 0.59 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 194580 kb
Host smart-6a3e817c-6895-4f02-8ce7-e247f6f5f9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621378934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2621378934
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.25905754
Short name T189
Test name
Test status
Simulation time 27449277 ps
CPU time 0.74 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 196416 kb
Host smart-8d32ba12-2222-483a-8641-75237d673c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25905754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.25905754
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1642083745
Short name T174
Test name
Test status
Simulation time 646606087 ps
CPU time 23.22 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:21:05 PM PDT 24
Peak memory 197488 kb
Host smart-9e11b47b-e226-43f9-b4c3-0c585b867f31
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642083745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1642083745
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1420658083
Short name T480
Test name
Test status
Simulation time 69228417 ps
CPU time 0.59 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 194468 kb
Host smart-c4ba5ee2-0bcf-4789-8545-7ffd19eb86c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420658083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1420658083
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3212357642
Short name T186
Test name
Test status
Simulation time 64685187 ps
CPU time 0.67 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 194748 kb
Host smart-17db8c2f-ad5e-4dd5-89c3-ce66abd020bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212357642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3212357642
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2972335651
Short name T280
Test name
Test status
Simulation time 324089084 ps
CPU time 3.14 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:45 PM PDT 24
Peak memory 198664 kb
Host smart-6900f339-b220-46f1-a351-319685de8f49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972335651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2972335651
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2133929479
Short name T662
Test name
Test status
Simulation time 198894922 ps
CPU time 3.03 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 197628 kb
Host smart-97e086a6-f68d-43a3-a587-39c55b802cd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133929479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2133929479
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4189120816
Short name T368
Test name
Test status
Simulation time 162525763 ps
CPU time 1.02 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:43 PM PDT 24
Peak memory 196552 kb
Host smart-f8f440ac-2615-4af6-a06c-4aad3aa53db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189120816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4189120816
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2688074532
Short name T405
Test name
Test status
Simulation time 73157407 ps
CPU time 1.24 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 197480 kb
Host smart-14c13985-4b20-439c-962c-6364ebee7661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688074532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2688074532
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3286208297
Short name T177
Test name
Test status
Simulation time 68502260 ps
CPU time 1.54 seconds
Started Aug 01 05:20:38 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 198384 kb
Host smart-ac1a71d3-3dc8-4ef3-9513-954d47b38757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286208297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3286208297
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3848383218
Short name T137
Test name
Test status
Simulation time 121321205 ps
CPU time 1.27 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 196704 kb
Host smart-5129c2ed-1f42-4184-8088-5ce850bb2671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848383218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3848383218
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3284624812
Short name T162
Test name
Test status
Simulation time 316813249 ps
CPU time 1.33 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:43 PM PDT 24
Peak memory 197308 kb
Host smart-5da80909-3dd4-4033-af17-ec22a3e5bbb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284624812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3284624812
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2629134336
Short name T318
Test name
Test status
Simulation time 4310373145 ps
CPU time 52.4 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 198676 kb
Host smart-4a2829fa-ff33-42d9-b011-61b079ac710d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629134336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2629134336
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.507729421
Short name T387
Test name
Test status
Simulation time 22335844 ps
CPU time 0.58 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 195028 kb
Host smart-804ed083-922b-4ae5-b917-bfe9268a7039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507729421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.507729421
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2148710640
Short name T446
Test name
Test status
Simulation time 40144156 ps
CPU time 0.97 seconds
Started Aug 01 05:20:46 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 196940 kb
Host smart-52acd54d-ad70-4e8d-a198-ec059faf93ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148710640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2148710640
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.113964988
Short name T364
Test name
Test status
Simulation time 170067524 ps
CPU time 8.23 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:50 PM PDT 24
Peak memory 196820 kb
Host smart-cd7147a9-90aa-4226-805f-72cbf9e1cfc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113964988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.113964988
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2391350077
Short name T231
Test name
Test status
Simulation time 180213447 ps
CPU time 0.82 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 196444 kb
Host smart-368723b1-ab5d-4224-9ec4-a91effa93df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391350077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2391350077
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1073622982
Short name T356
Test name
Test status
Simulation time 37514901 ps
CPU time 1.08 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 197284 kb
Host smart-94ef4c2b-fc3e-4021-8fb1-2d825c82f26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073622982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1073622982
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1613167428
Short name T339
Test name
Test status
Simulation time 64812153 ps
CPU time 1.44 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:43 PM PDT 24
Peak memory 197052 kb
Host smart-f18f3235-8d78-4961-89bf-c2f91c4237ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613167428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1613167428
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.36220915
Short name T682
Test name
Test status
Simulation time 1423806647 ps
CPU time 1.82 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:45 PM PDT 24
Peak memory 196664 kb
Host smart-b660cd1e-7c4f-43f6-a9ce-6a4e7b6a0892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36220915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.36220915
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1705399340
Short name T307
Test name
Test status
Simulation time 25527352 ps
CPU time 0.78 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:20:42 PM PDT 24
Peak memory 196688 kb
Host smart-1976f765-a323-452d-9998-7e5c64a4f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705399340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1705399340
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3735026118
Short name T139
Test name
Test status
Simulation time 120993710 ps
CPU time 0.83 seconds
Started Aug 01 05:20:46 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 196688 kb
Host smart-73c5b1f9-44e7-4d74-90f9-4354dc707b38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735026118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3735026118
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1141297910
Short name T385
Test name
Test status
Simulation time 1035745332 ps
CPU time 3.55 seconds
Started Aug 01 05:20:42 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 198512 kb
Host smart-de678521-ee3a-4c1e-94d0-4289a9483bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141297910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1141297910
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2673188317
Short name T235
Test name
Test status
Simulation time 50493876 ps
CPU time 0.94 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 196768 kb
Host smart-ef3f40e2-9a26-4dcf-a2b3-4bcf791d5797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673188317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2673188317
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4083007117
Short name T11
Test name
Test status
Simulation time 88977976 ps
CPU time 0.86 seconds
Started Aug 01 05:20:46 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 196484 kb
Host smart-f745edc9-4833-405a-ad8b-28956e54b2df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083007117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4083007117
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1114410385
Short name T654
Test name
Test status
Simulation time 3736842117 ps
CPU time 55.06 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:21:37 PM PDT 24
Peak memory 198644 kb
Host smart-64dd9fbc-b546-4c95-a101-0d630c7935b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114410385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1114410385
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1491824910
Short name T65
Test name
Test status
Simulation time 161245988748 ps
CPU time 1908.4 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:52:31 PM PDT 24
Peak memory 198748 kb
Host smart-c11064d1-7e51-4e36-9c03-01a9afe67a34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1491824910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1491824910
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4056570664
Short name T584
Test name
Test status
Simulation time 21622305 ps
CPU time 0.57 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:56 PM PDT 24
Peak memory 195380 kb
Host smart-2ba74299-6b5e-4f08-ba22-a9d14a6e809e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056570664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4056570664
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1144117156
Short name T708
Test name
Test status
Simulation time 95689316 ps
CPU time 0.79 seconds
Started Aug 01 05:20:45 PM PDT 24
Finished Aug 01 05:20:45 PM PDT 24
Peak memory 195836 kb
Host smart-7319e1fe-26b8-47ac-8c6b-7e5ef52009e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144117156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1144117156
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.786559629
Short name T408
Test name
Test status
Simulation time 661586383 ps
CPU time 24.69 seconds
Started Aug 01 05:20:41 PM PDT 24
Finished Aug 01 05:21:06 PM PDT 24
Peak memory 197240 kb
Host smart-f1ea10c6-3b9c-4d79-9e2b-d2d67371534a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786559629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.786559629
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.555785262
Short name T472
Test name
Test status
Simulation time 95001051 ps
CPU time 0.73 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 195808 kb
Host smart-25aca793-46b1-4d9b-893a-2cdc88b3a703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555785262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.555785262
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2433837774
Short name T337
Test name
Test status
Simulation time 50278520 ps
CPU time 0.82 seconds
Started Aug 01 05:20:47 PM PDT 24
Finished Aug 01 05:20:48 PM PDT 24
Peak memory 195828 kb
Host smart-f22642c9-fc57-4cc3-8c35-e123a471ec48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433837774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2433837774
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1074898324
Short name T250
Test name
Test status
Simulation time 93688807 ps
CPU time 2.01 seconds
Started Aug 01 05:20:47 PM PDT 24
Finished Aug 01 05:20:49 PM PDT 24
Peak memory 198612 kb
Host smart-422da0e5-72e2-4d85-9117-e7c196dd7578
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074898324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1074898324
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1912376139
Short name T245
Test name
Test status
Simulation time 194086155 ps
CPU time 0.96 seconds
Started Aug 01 05:20:47 PM PDT 24
Finished Aug 01 05:20:48 PM PDT 24
Peak memory 194756 kb
Host smart-5aaad616-eef8-417d-87f5-947d05f3afa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912376139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1912376139
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.74801862
Short name T218
Test name
Test status
Simulation time 16976157 ps
CPU time 0.74 seconds
Started Aug 01 05:20:44 PM PDT 24
Finished Aug 01 05:20:44 PM PDT 24
Peak memory 195928 kb
Host smart-b4651210-b7d1-4304-b052-cbcb9167fdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74801862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.74801862
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.824279270
Short name T237
Test name
Test status
Simulation time 357261125 ps
CPU time 1.43 seconds
Started Aug 01 05:20:46 PM PDT 24
Finished Aug 01 05:20:47 PM PDT 24
Peak memory 198480 kb
Host smart-feeaf295-65f1-4cec-afce-eeba5638e7e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824279270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.824279270
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.44920741
Short name T553
Test name
Test status
Simulation time 611651998 ps
CPU time 4.85 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198408 kb
Host smart-b9141418-ab4b-480e-988b-6604749ac0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44920741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand
om_long_reg_writes_reg_reads.44920741
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2851555491
Short name T13
Test name
Test status
Simulation time 79577090 ps
CPU time 1.31 seconds
Started Aug 01 05:20:43 PM PDT 24
Finished Aug 01 05:20:45 PM PDT 24
Peak memory 197312 kb
Host smart-210a034b-6b3a-48c5-a73e-d1ade1c5ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851555491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2851555491
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2066367411
Short name T456
Test name
Test status
Simulation time 127267893 ps
CPU time 1.19 seconds
Started Aug 01 05:20:39 PM PDT 24
Finished Aug 01 05:20:40 PM PDT 24
Peak memory 196224 kb
Host smart-e5eabadb-28bf-4d63-8cbe-c3f98c7fcc64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066367411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2066367411
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3667552957
Short name T474
Test name
Test status
Simulation time 2452104786 ps
CPU time 32.45 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 198580 kb
Host smart-539f7e83-9e85-4f69-ae44-86d5c6721194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667552957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3667552957
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1150210697
Short name T710
Test name
Test status
Simulation time 25372253 ps
CPU time 0.57 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 194376 kb
Host smart-661759b2-6cc3-4a72-ade4-0fe2dd4e264e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150210697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1150210697
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3282624153
Short name T580
Test name
Test status
Simulation time 108844795 ps
CPU time 0.86 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 195684 kb
Host smart-6493b77f-d9c5-4a00-827f-976683941b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282624153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3282624153
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2619609739
Short name T537
Test name
Test status
Simulation time 335117755 ps
CPU time 10.98 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:09 PM PDT 24
Peak memory 197508 kb
Host smart-be0ee700-d5db-44b1-8386-6e780c425ace
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619609739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2619609739
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.956252328
Short name T611
Test name
Test status
Simulation time 21508156 ps
CPU time 0.65 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 195680 kb
Host smart-ece8f398-b55e-45dc-b3f0-9e6362237ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956252328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.956252328
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3753862896
Short name T688
Test name
Test status
Simulation time 43230176 ps
CPU time 0.95 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 196248 kb
Host smart-2d00ff91-f60a-44c0-8691-3885b84011b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753862896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3753862896
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1581134751
Short name T248
Test name
Test status
Simulation time 71408791 ps
CPU time 1.64 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 197068 kb
Host smart-e69e19e0-eaae-4959-b7a8-a8c7fa57a097
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581134751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1581134751
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2464263118
Short name T355
Test name
Test status
Simulation time 105345908 ps
CPU time 2.27 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 197436 kb
Host smart-9c7a43ba-5afa-422c-b3a5-fba99ca578f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464263118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2464263118
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2075019555
Short name T488
Test name
Test status
Simulation time 1046450506 ps
CPU time 1.24 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 197544 kb
Host smart-c56b9ebe-3de5-42ca-be32-7af3279f3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075019555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2075019555
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2590890277
Short name T618
Test name
Test status
Simulation time 18305069 ps
CPU time 0.79 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 195908 kb
Host smart-8223bbf2-dcaa-4401-8f88-c678610d7221
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590890277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2590890277
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2804482167
Short name T605
Test name
Test status
Simulation time 212311679 ps
CPU time 3.75 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198464 kb
Host smart-6a081943-89a8-483d-93c8-b70d70888527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804482167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2804482167
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2588033230
Short name T477
Test name
Test status
Simulation time 305000347 ps
CPU time 1.14 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 196048 kb
Host smart-b292429e-706e-4c15-bd7a-ea8ae7b39542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588033230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2588033230
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1265654920
Short name T210
Test name
Test status
Simulation time 49794970 ps
CPU time 0.98 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 196252 kb
Host smart-61a8ad03-19d2-4887-bdbe-9bf84143ec52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265654920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1265654920
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3534558161
Short name T543
Test name
Test status
Simulation time 1427726552 ps
CPU time 43.3 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:43 PM PDT 24
Peak memory 198516 kb
Host smart-5c0254c1-f4ce-40b5-877b-111c17fba86c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534558161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3534558161
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2102937420
Short name T366
Test name
Test status
Simulation time 47599705 ps
CPU time 0.61 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 194608 kb
Host smart-878e0e25-4de0-476d-8a2c-f934861d1ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102937420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2102937420
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3860536812
Short name T430
Test name
Test status
Simulation time 26981983 ps
CPU time 0.77 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 196428 kb
Host smart-97ffd37c-45a7-4597-a91d-da9b317e5674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860536812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3860536812
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3157896654
Short name T683
Test name
Test status
Simulation time 533341480 ps
CPU time 9.18 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:07 PM PDT 24
Peak memory 197296 kb
Host smart-59b94f95-d8cb-463c-ae3f-ac80978fc2c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157896654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3157896654
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1411778802
Short name T517
Test name
Test status
Simulation time 122766478 ps
CPU time 0.94 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 196324 kb
Host smart-0668d020-eaa8-4e5f-b503-0a3e82ec6255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411778802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1411778802
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2059043665
Short name T696
Test name
Test status
Simulation time 38347610 ps
CPU time 0.81 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 195992 kb
Host smart-0c1a6973-2750-442e-b1d1-d44a86a74b12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059043665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2059043665
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.783795812
Short name T672
Test name
Test status
Simulation time 254744299 ps
CPU time 2.4 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 196936 kb
Host smart-038e416c-30f1-48c7-a2ea-e058141df9fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783795812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.783795812
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1856268581
Short name T135
Test name
Test status
Simulation time 37921016 ps
CPU time 1.13 seconds
Started Aug 01 05:21:01 PM PDT 24
Finished Aug 01 05:21:02 PM PDT 24
Peak memory 196624 kb
Host smart-b65ebbb0-36f9-493b-889f-061b2cea2651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856268581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1856268581
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2158644132
Short name T151
Test name
Test status
Simulation time 19906982 ps
CPU time 0.84 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 197000 kb
Host smart-ae6236bc-90d3-498a-8b3d-716cf85beaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158644132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2158644132
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2100578968
Short name T109
Test name
Test status
Simulation time 204334521 ps
CPU time 1.39 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198532 kb
Host smart-a24d522a-a36c-40fb-b3cc-f939bada247e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100578968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2100578968
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1133434327
Short name T424
Test name
Test status
Simulation time 184480857 ps
CPU time 2.94 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198504 kb
Host smart-e222a426-a258-4636-ae60-cd48e234f048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133434327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1133434327
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1182949855
Short name T453
Test name
Test status
Simulation time 43481659 ps
CPU time 0.88 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 195728 kb
Host smart-6bf6f6f0-cfee-4b5d-ac58-1777eeb46535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182949855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1182949855
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2362316046
Short name T609
Test name
Test status
Simulation time 65828397 ps
CPU time 1.34 seconds
Started Aug 01 05:21:00 PM PDT 24
Finished Aug 01 05:21:02 PM PDT 24
Peak memory 197012 kb
Host smart-85e3350c-ff5a-45fc-9374-5494106456f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362316046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2362316046
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1170455087
Short name T525
Test name
Test status
Simulation time 4747767429 ps
CPU time 53.2 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 198736 kb
Host smart-5f4dbdeb-85cf-4b72-9e6f-462885ea0c20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170455087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1170455087
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.15683802
Short name T306
Test name
Test status
Simulation time 54564509 ps
CPU time 0.64 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 194584 kb
Host smart-76838902-1a05-4132-b680-4a7a738ce992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15683802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.15683802
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2821291345
Short name T484
Test name
Test status
Simulation time 40214328 ps
CPU time 0.8 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 195836 kb
Host smart-bf9855b1-79a8-4f20-9617-ccdfb04ecc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821291345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2821291345
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2872413418
Short name T473
Test name
Test status
Simulation time 981989728 ps
CPU time 17.28 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 198468 kb
Host smart-84999665-8be7-4334-a421-aac350ec8f81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872413418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2872413418
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3107106804
Short name T705
Test name
Test status
Simulation time 26421810 ps
CPU time 0.63 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 195676 kb
Host smart-1aa74be3-643b-4adb-a8b6-5f465acde215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107106804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3107106804
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2146838084
Short name T293
Test name
Test status
Simulation time 75342798 ps
CPU time 1.15 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 197356 kb
Host smart-fa7fa992-a33f-4e80-9c56-181fd0dcc7a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146838084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2146838084
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3383163081
Short name T313
Test name
Test status
Simulation time 874556939 ps
CPU time 3.24 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:02 PM PDT 24
Peak memory 198580 kb
Host smart-8969fc4c-953e-4836-9870-21547c37ddb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383163081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3383163081
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3518020266
Short name T256
Test name
Test status
Simulation time 378623419 ps
CPU time 3.06 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 198580 kb
Host smart-593b4f44-062b-4362-ac87-2ad4242c40da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518020266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3518020266
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.689451134
Short name T173
Test name
Test status
Simulation time 134127790 ps
CPU time 0.9 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 196504 kb
Host smart-12572f44-6421-4f1c-896f-366b6257d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689451134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.689451134
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.52988796
Short name T627
Test name
Test status
Simulation time 25428000 ps
CPU time 0.8 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 195932 kb
Host smart-4f07fb9c-889f-4946-a522-61578ebce2b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52988796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_
pulldown.52988796
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3859918585
Short name T345
Test name
Test status
Simulation time 442695970 ps
CPU time 3.67 seconds
Started Aug 01 05:21:01 PM PDT 24
Finished Aug 01 05:21:04 PM PDT 24
Peak memory 198372 kb
Host smart-df0f781c-1de9-4b82-a283-50920837196f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859918585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3859918585
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2626354132
Short name T228
Test name
Test status
Simulation time 36866183 ps
CPU time 1.18 seconds
Started Aug 01 05:20:55 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 196164 kb
Host smart-bfb49ef8-048c-4a09-bcf1-c6022ddfdc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626354132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2626354132
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1897292799
Short name T520
Test name
Test status
Simulation time 292998951 ps
CPU time 1.3 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 197396 kb
Host smart-d0eb0170-cd84-45b8-8595-58fd88f87942
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897292799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1897292799
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3162597952
Short name T518
Test name
Test status
Simulation time 13512551748 ps
CPU time 186.61 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 198648 kb
Host smart-6ce53391-bde6-42e1-b178-57078e786637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162597952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3162597952
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3360540176
Short name T203
Test name
Test status
Simulation time 42291406 ps
CPU time 0.53 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 194372 kb
Host smart-43ba82cb-09d4-4c80-86c7-a8d6b180f72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360540176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3360540176
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2151186047
Short name T586
Test name
Test status
Simulation time 99042716 ps
CPU time 0.93 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 196424 kb
Host smart-30e7f14e-571d-4c9d-a230-b5e22021274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151186047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2151186047
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.31749668
Short name T678
Test name
Test status
Simulation time 889843748 ps
CPU time 23.15 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:22 PM PDT 24
Peak memory 197224 kb
Host smart-39332e60-bd7e-4e8e-92e7-b18f849cc356
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31749668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stress
.31749668
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3421379478
Short name T403
Test name
Test status
Simulation time 134457689 ps
CPU time 1.05 seconds
Started Aug 01 05:20:59 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 197564 kb
Host smart-cd3a905e-5bc8-4e85-b036-9be963f09e1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421379478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3421379478
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1826773400
Short name T141
Test name
Test status
Simulation time 93297558 ps
CPU time 0.92 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 198060 kb
Host smart-a070d8e6-0aa0-423f-970c-f33aacb82317
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826773400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1826773400
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4175991250
Short name T327
Test name
Test status
Simulation time 279193322 ps
CPU time 3.03 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:01 PM PDT 24
Peak memory 198572 kb
Host smart-c0f1f393-199b-43f2-adfa-aa3d66590c54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175991250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4175991250
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3586025384
Short name T697
Test name
Test status
Simulation time 97153609 ps
CPU time 2.07 seconds
Started Aug 01 05:21:01 PM PDT 24
Finished Aug 01 05:21:03 PM PDT 24
Peak memory 196332 kb
Host smart-45b9a9ad-6f81-4ac7-b4a9-89fb25d075a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586025384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3586025384
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3699123844
Short name T689
Test name
Test status
Simulation time 94845047 ps
CPU time 0.74 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:20:58 PM PDT 24
Peak memory 196560 kb
Host smart-08f279b3-7d73-43cb-8f7a-508747d3d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699123844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3699123844
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1111530266
Short name T341
Test name
Test status
Simulation time 87497309 ps
CPU time 0.76 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 196408 kb
Host smart-c59db56b-dac5-49c6-bb3c-ee019d1a1c0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111530266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1111530266
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.576197389
Short name T433
Test name
Test status
Simulation time 118347317 ps
CPU time 2.96 seconds
Started Aug 01 05:20:57 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 198520 kb
Host smart-8d7656f7-bfaa-493b-a050-0bb91bba09e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576197389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.576197389
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.4250411097
Short name T587
Test name
Test status
Simulation time 75254965 ps
CPU time 1.46 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:21:00 PM PDT 24
Peak memory 197380 kb
Host smart-201c9866-3466-485e-b94b-eb94ca8d4042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250411097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.4250411097
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1574038249
Short name T127
Test name
Test status
Simulation time 322383888 ps
CPU time 0.95 seconds
Started Aug 01 05:20:58 PM PDT 24
Finished Aug 01 05:20:59 PM PDT 24
Peak memory 196712 kb
Host smart-711c60ed-d3cc-4148-9e68-848730f07f03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574038249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1574038249
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3905563167
Short name T76
Test name
Test status
Simulation time 18185243327 ps
CPU time 178.16 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 198752 kb
Host smart-de0a0443-b466-4565-a1e9-ffaed265517e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905563167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3905563167
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1926509276
Short name T72
Test name
Test status
Simulation time 21619648 ps
CPU time 0.67 seconds
Started Aug 01 05:21:15 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 196148 kb
Host smart-0b721029-5528-40d5-818f-5422c1da9352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926509276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1926509276
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2881914187
Short name T384
Test name
Test status
Simulation time 188174190 ps
CPU time 0.9 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:14 PM PDT 24
Peak memory 197184 kb
Host smart-7d10fd76-aec4-4141-bbac-a18c9e993809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881914187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2881914187
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1731949012
Short name T330
Test name
Test status
Simulation time 884335480 ps
CPU time 12.3 seconds
Started Aug 01 05:21:09 PM PDT 24
Finished Aug 01 05:21:21 PM PDT 24
Peak memory 197228 kb
Host smart-cce27311-46c6-4bb6-8e9d-cfb60249282f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731949012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1731949012
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1336748754
Short name T234
Test name
Test status
Simulation time 332692263 ps
CPU time 1.01 seconds
Started Aug 01 05:21:09 PM PDT 24
Finished Aug 01 05:21:10 PM PDT 24
Peak memory 196860 kb
Host smart-c9482533-012c-4979-a424-dc745efcfdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336748754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1336748754
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2528200752
Short name T74
Test name
Test status
Simulation time 121035109 ps
CPU time 1.01 seconds
Started Aug 01 05:21:16 PM PDT 24
Finished Aug 01 05:21:17 PM PDT 24
Peak memory 196368 kb
Host smart-4e1247b5-93f9-43de-9ade-dcf0f19f19fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528200752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2528200752
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3730847810
Short name T353
Test name
Test status
Simulation time 341923232 ps
CPU time 3.41 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:18 PM PDT 24
Peak memory 198700 kb
Host smart-ff39a418-122c-4817-bb0d-3018406b4315
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730847810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3730847810
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.376655021
Short name T21
Test name
Test status
Simulation time 212664924 ps
CPU time 1.18 seconds
Started Aug 01 05:21:16 PM PDT 24
Finished Aug 01 05:21:17 PM PDT 24
Peak memory 195876 kb
Host smart-e3019dc8-4a7d-4be6-883d-5483bd50ff18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376655021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
376655021
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.207163741
Short name T570
Test name
Test status
Simulation time 78040516 ps
CPU time 0.9 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 196568 kb
Host smart-aa2e5049-6ff6-4cae-a541-ef4edfe5f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207163741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.207163741
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2534393611
Short name T604
Test name
Test status
Simulation time 82366856 ps
CPU time 0.71 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 196452 kb
Host smart-bd356da3-4e2d-4486-8654-e3f168ef500e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534393611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2534393611
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1630050376
Short name T625
Test name
Test status
Simulation time 1085098132 ps
CPU time 6.27 seconds
Started Aug 01 05:21:09 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 198356 kb
Host smart-17561d18-34fc-42e1-bd9b-afe8dfa4749e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630050376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1630050376
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3882145053
Short name T335
Test name
Test status
Simulation time 140135643 ps
CPU time 0.8 seconds
Started Aug 01 05:20:56 PM PDT 24
Finished Aug 01 05:20:57 PM PDT 24
Peak memory 195804 kb
Host smart-cd4e8d46-a3a5-4071-a9bc-257ea85cbcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882145053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3882145053
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3951287335
Short name T220
Test name
Test status
Simulation time 68110117 ps
CPU time 1.14 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 196048 kb
Host smart-50fb46cc-8028-41ef-9b3f-c4049b5cb12c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951287335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3951287335
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.258159722
Short name T2
Test name
Test status
Simulation time 15571016209 ps
CPU time 95.17 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:22:46 PM PDT 24
Peak memory 198672 kb
Host smart-78588024-9468-4f26-9ade-ca61b5a75f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258159722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.258159722
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3436365979
Short name T33
Test name
Test status
Simulation time 52333273163 ps
CPU time 240.61 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 198836 kb
Host smart-8249efab-80e7-4837-8b93-bee833371525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3436365979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3436365979
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2135741128
Short name T258
Test name
Test status
Simulation time 22757519 ps
CPU time 0.57 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:10 PM PDT 24
Peak memory 194352 kb
Host smart-da0dcc17-a2c7-44e2-affb-72c7166e331f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135741128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2135741128
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2758973913
Short name T23
Test name
Test status
Simulation time 19772029 ps
CPU time 0.68 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:10 PM PDT 24
Peak memory 195188 kb
Host smart-3325eb52-1a93-4726-93c7-b9538c74a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758973913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2758973913
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2488809121
Short name T594
Test name
Test status
Simulation time 589413636 ps
CPU time 6.89 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:18 PM PDT 24
Peak memory 196084 kb
Host smart-1e0ceb60-fd34-4bb3-a96d-a1f20d753d07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488809121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2488809121
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.690619302
Short name T509
Test name
Test status
Simulation time 275471836 ps
CPU time 0.88 seconds
Started Aug 01 05:21:08 PM PDT 24
Finished Aug 01 05:21:09 PM PDT 24
Peak memory 198152 kb
Host smart-6c79c7c1-8c2e-43bf-b5c2-00a3ec5a392e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690619302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.690619302
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.632821189
Short name T311
Test name
Test status
Simulation time 61092135 ps
CPU time 1.04 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 196420 kb
Host smart-dedc5918-5d6d-4833-9f6c-ce80b0355c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632821189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.632821189
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.820014073
Short name T309
Test name
Test status
Simulation time 52136821 ps
CPU time 2.18 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 198652 kb
Host smart-acb4ab05-7965-4bbb-9d5f-7a57067f5eaa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820014073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.820014073
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.101681286
Short name T634
Test name
Test status
Simulation time 44648063 ps
CPU time 1.17 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 196976 kb
Host smart-6f11a31a-1d72-4992-9159-c3cb195c80ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101681286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
101681286
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3871971639
Short name T632
Test name
Test status
Simulation time 214861157 ps
CPU time 1.22 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 196336 kb
Host smart-c7552ce0-69ec-41f8-8a88-60c237f45433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871971639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3871971639
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.661157605
Short name T166
Test name
Test status
Simulation time 52477451 ps
CPU time 1.04 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 196512 kb
Host smart-2f2e6571-dd15-49ea-a72b-26379657a965
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661157605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.661157605
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.655654804
Short name T161
Test name
Test status
Simulation time 1646631135 ps
CPU time 3.93 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:17 PM PDT 24
Peak memory 198544 kb
Host smart-03621110-c8c6-4b87-8a93-9f0777a50493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655654804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.655654804
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3812228646
Short name T184
Test name
Test status
Simulation time 108433169 ps
CPU time 1.54 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 197292 kb
Host smart-34b6a021-0146-4c9b-b313-19fc6ee83519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812228646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3812228646
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1357741359
Short name T702
Test name
Test status
Simulation time 316777141 ps
CPU time 1.18 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 196312 kb
Host smart-9f66a01b-01cd-4fa1-8670-205ac0939b54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357741359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1357741359
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3862386871
Short name T9
Test name
Test status
Simulation time 21508576741 ps
CPU time 106.95 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:23:00 PM PDT 24
Peak memory 198724 kb
Host smart-9d293693-badf-44e9-8877-8a5b0b79640c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862386871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3862386871
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1893997697
Short name T294
Test name
Test status
Simulation time 49357822 ps
CPU time 0.58 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 195276 kb
Host smart-d4d5f54c-cfba-47b6-8c1d-1abb950bfc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893997697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1893997697
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2110059847
Short name T233
Test name
Test status
Simulation time 159104401 ps
CPU time 0.85 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:11 PM PDT 24
Peak memory 197020 kb
Host smart-293d4440-ee6a-482a-9037-b3cabf4677c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110059847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2110059847
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2908423863
Short name T529
Test name
Test status
Simulation time 187643552 ps
CPU time 9.42 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:19 PM PDT 24
Peak memory 198776 kb
Host smart-9861a36b-0888-4565-ac8b-fa3d6454ef1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908423863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2908423863
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3679027104
Short name T407
Test name
Test status
Simulation time 17373502 ps
CPU time 0.6 seconds
Started Aug 01 05:21:15 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 194916 kb
Host smart-53967b12-1e59-4a2a-9166-dfcc3105cd52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679027104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3679027104
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.592894289
Short name T388
Test name
Test status
Simulation time 153701823 ps
CPU time 1.36 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 197112 kb
Host smart-57e11dfd-6002-46e5-a7b8-6581fc35df3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592894289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.592894289
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.459600001
Short name T526
Test name
Test status
Simulation time 236996881 ps
CPU time 3.34 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 198528 kb
Host smart-e711286f-1c5a-41a3-8cd3-577680e60d41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459600001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.459600001
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.443994910
Short name T22
Test name
Test status
Simulation time 139227257 ps
CPU time 2.25 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 197364 kb
Host smart-b9ce1188-3496-4035-8ba3-22a3100af5ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443994910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
443994910
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1229304718
Short name T556
Test name
Test status
Simulation time 94197355 ps
CPU time 0.83 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:11 PM PDT 24
Peak memory 196724 kb
Host smart-62077043-e7e7-4e7b-ad89-6dca28b9b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229304718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1229304718
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3727865476
Short name T214
Test name
Test status
Simulation time 111088438 ps
CPU time 1.1 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 197028 kb
Host smart-324e45b1-7930-4beb-83fd-3efbadb66559
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727865476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3727865476
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1539258091
Short name T546
Test name
Test status
Simulation time 130027408 ps
CPU time 2.12 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 198560 kb
Host smart-4f700dbc-7e6b-4ebe-a2f4-a2072aca53f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539258091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1539258091
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1165850313
Short name T560
Test name
Test status
Simulation time 104003658 ps
CPU time 1.16 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:14 PM PDT 24
Peak memory 196308 kb
Host smart-4d6f220e-832e-48ea-b06f-704adf27cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165850313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1165850313
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2399303520
Short name T343
Test name
Test status
Simulation time 139174802 ps
CPU time 1.16 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:14 PM PDT 24
Peak memory 196936 kb
Host smart-83968edd-faf1-4821-ba1f-159c778a33c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399303520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2399303520
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1432689789
Short name T457
Test name
Test status
Simulation time 9034954459 ps
CPU time 95.9 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:22:48 PM PDT 24
Peak memory 198588 kb
Host smart-f38dbaf6-f3ad-49eb-9521-10fe22490892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432689789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1432689789
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2295580383
Short name T551
Test name
Test status
Simulation time 12746582 ps
CPU time 0.56 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:53 PM PDT 24
Peak memory 194392 kb
Host smart-561ad589-7300-4f6a-a4dc-ff71fe2b8e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295580383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2295580383
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2920514170
Short name T699
Test name
Test status
Simulation time 79623629 ps
CPU time 0.78 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 194584 kb
Host smart-bedc3878-50b5-41f5-b121-0f91bb6941a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920514170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2920514170
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.939901440
Short name T310
Test name
Test status
Simulation time 1393193664 ps
CPU time 18.02 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:20:12 PM PDT 24
Peak memory 197400 kb
Host smart-de4ddad4-e908-45f0-99cf-6af8e53f72a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939901440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.939901440
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3950222937
Short name T3
Test name
Test status
Simulation time 91686076 ps
CPU time 0.91 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 197468 kb
Host smart-a24d998f-b16c-4651-9c77-a63451f7419a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950222937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3950222937
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.4049483656
Short name T58
Test name
Test status
Simulation time 377247570 ps
CPU time 1.44 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:19:52 PM PDT 24
Peak memory 197040 kb
Host smart-e77299e7-a583-42f7-83d6-023ff350c6d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049483656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.4049483656
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.843192894
Short name T225
Test name
Test status
Simulation time 483635655 ps
CPU time 2.95 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 198544 kb
Host smart-d34806ec-e1d9-4825-9796-64683d541efa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843192894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.843192894
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3079597628
Short name T629
Test name
Test status
Simulation time 390008079 ps
CPU time 2.85 seconds
Started Aug 01 05:19:51 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 196268 kb
Host smart-d071b9e9-2b8c-40ab-8c07-ad0948f0c160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079597628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3079597628
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4242246365
Short name T501
Test name
Test status
Simulation time 86883181 ps
CPU time 0.83 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196504 kb
Host smart-b6ecca47-31cf-4459-bcbc-1d19e369491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242246365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4242246365
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1322979435
Short name T296
Test name
Test status
Simulation time 30672134 ps
CPU time 0.8 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 195872 kb
Host smart-0b3b3b8f-e261-465f-87b8-20016c80492b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322979435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1322979435
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.46316637
Short name T427
Test name
Test status
Simulation time 43138985 ps
CPU time 1.89 seconds
Started Aug 01 05:19:57 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 198524 kb
Host smart-019cc033-4d2e-415e-b7f4-906ac699583a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46316637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rando
m_long_reg_writes_reg_reads.46316637
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.2075996716
Short name T153
Test name
Test status
Simulation time 38656489 ps
CPU time 1.1 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 196148 kb
Host smart-28b53a87-c530-41c6-bc80-020957609c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075996716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2075996716
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3201269173
Short name T270
Test name
Test status
Simulation time 54941717 ps
CPU time 0.93 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 195980 kb
Host smart-1d3ba354-f296-41c8-8124-1345326a6641
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201269173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3201269173
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2533234113
Short name T429
Test name
Test status
Simulation time 20725324245 ps
CPU time 143.67 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:22:16 PM PDT 24
Peak memory 192692 kb
Host smart-0f1ed5c1-a49e-4e9d-b8e8-11e2be497986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533234113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2533234113
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.751704095
Short name T205
Test name
Test status
Simulation time 34103735 ps
CPU time 0.57 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 195084 kb
Host smart-ef150eda-be73-458f-be1d-a3cbc260431d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751704095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.751704095
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1168612488
Short name T375
Test name
Test status
Simulation time 169437896 ps
CPU time 0.68 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 195376 kb
Host smart-ba6ac63a-fa91-487b-b612-7e32f4e81442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168612488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1168612488
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2508629635
Short name T200
Test name
Test status
Simulation time 806261710 ps
CPU time 23.73 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 198512 kb
Host smart-30e471b7-18b0-4556-9462-ed1a946d4222
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508629635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2508629635
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3871347507
Short name T206
Test name
Test status
Simulation time 341419933 ps
CPU time 0.69 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 195252 kb
Host smart-b27b0a2f-6000-4db7-9be1-f8a5a62311ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871347507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3871347507
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3384648969
Short name T666
Test name
Test status
Simulation time 104086470 ps
CPU time 0.92 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 196568 kb
Host smart-c380387f-e2e3-4ac1-8b5c-9c6c653bb692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384648969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3384648969
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3999339735
Short name T289
Test name
Test status
Simulation time 43806565 ps
CPU time 1.78 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 198552 kb
Host smart-28c5d97f-ded0-4d44-83c2-46eb4b943974
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999339735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3999339735
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2953793201
Short name T496
Test name
Test status
Simulation time 81766333 ps
CPU time 0.95 seconds
Started Aug 01 05:21:15 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 196120 kb
Host smart-49dce786-4861-4158-8946-600b67229bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953793201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2953793201
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4196397915
Short name T530
Test name
Test status
Simulation time 80131068 ps
CPU time 0.89 seconds
Started Aug 01 05:21:10 PM PDT 24
Finished Aug 01 05:21:11 PM PDT 24
Peak memory 197244 kb
Host smart-4b4cd39e-0d4a-4fec-89da-44cde6ce1832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196397915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4196397915
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3496350684
Short name T547
Test name
Test status
Simulation time 63418667 ps
CPU time 1.18 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:14 PM PDT 24
Peak memory 196268 kb
Host smart-4d876888-5819-4b1b-96c9-4c9e786e58d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496350684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3496350684
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3940426373
Short name T431
Test name
Test status
Simulation time 874383222 ps
CPU time 3.63 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 198472 kb
Host smart-40727098-bb1c-432c-a5fb-21650e43558b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940426373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3940426373
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3592640655
Short name T55
Test name
Test status
Simulation time 148714409 ps
CPU time 0.85 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:21:12 PM PDT 24
Peak memory 196912 kb
Host smart-d43d0d23-e519-4336-98d5-5af3028a270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592640655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3592640655
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2447582972
Short name T287
Test name
Test status
Simulation time 31368529 ps
CPU time 0.76 seconds
Started Aug 01 05:21:13 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 195408 kb
Host smart-4799d335-28eb-4841-a080-72f228b8757f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447582972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2447582972
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.500496227
Short name T29
Test name
Test status
Simulation time 14536647862 ps
CPU time 96.16 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:22:49 PM PDT 24
Peak memory 198628 kb
Host smart-f4a11339-e1ee-44a9-8d71-81d3fd524420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500496227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.500496227
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3208549269
Short name T66
Test name
Test status
Simulation time 112917467268 ps
CPU time 2266.88 seconds
Started Aug 01 05:21:11 PM PDT 24
Finished Aug 01 05:58:58 PM PDT 24
Peak memory 198776 kb
Host smart-1e1b7f2f-6f0a-48f0-bb88-b56ba1b217e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3208549269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3208549269
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2648085366
Short name T508
Test name
Test status
Simulation time 13767698 ps
CPU time 0.58 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 194660 kb
Host smart-1dd186b7-47aa-4667-bb01-c4cd420968c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648085366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2648085366
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.882274994
Short name T223
Test name
Test status
Simulation time 104952304 ps
CPU time 0.68 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 194556 kb
Host smart-f7baf565-8bff-4e8b-996d-94a83fc66f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882274994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.882274994
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.468144279
Short name T273
Test name
Test status
Simulation time 428803704 ps
CPU time 19.42 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:33 PM PDT 24
Peak memory 197488 kb
Host smart-52e82bb9-7317-4e79-99ce-ad0240b17923
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468144279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.468144279
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2503357814
Short name T347
Test name
Test status
Simulation time 75381394 ps
CPU time 0.9 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 197036 kb
Host smart-fbe9d1dc-f094-4537-9b0d-6684ac88284b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503357814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2503357814
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4270274960
Short name T213
Test name
Test status
Simulation time 70073534 ps
CPU time 0.72 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 195980 kb
Host smart-5c052be0-3d32-4768-90fd-55b8e36ede15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270274960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4270274960
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4291119585
Short name T613
Test name
Test status
Simulation time 72976901 ps
CPU time 2.97 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 198500 kb
Host smart-7cce298f-1d2e-4bb6-bafd-7a42ef23be39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291119585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4291119585
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.459031721
Short name T602
Test name
Test status
Simulation time 408219070 ps
CPU time 2.11 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 196548 kb
Host smart-c0751200-567d-47c4-b22c-1194717b9041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459031721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
459031721
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2801365553
Short name T495
Test name
Test status
Simulation time 65918302 ps
CPU time 1.21 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:14 PM PDT 24
Peak memory 197568 kb
Host smart-7299eaee-00e2-4598-8729-980a60d15840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801365553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2801365553
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4265875803
Short name T53
Test name
Test status
Simulation time 31800174 ps
CPU time 1.18 seconds
Started Aug 01 05:21:12 PM PDT 24
Finished Aug 01 05:21:13 PM PDT 24
Peak memory 196480 kb
Host smart-9be8722f-2ab5-4997-b577-c6d5c2be8533
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265875803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4265875803
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.402417653
Short name T402
Test name
Test status
Simulation time 288080938 ps
CPU time 3.16 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:17 PM PDT 24
Peak memory 198428 kb
Host smart-c2c72355-5543-4eb1-b012-ae16eca7f6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402417653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.402417653
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1964397257
Short name T359
Test name
Test status
Simulation time 39285215 ps
CPU time 0.72 seconds
Started Aug 01 05:21:16 PM PDT 24
Finished Aug 01 05:21:17 PM PDT 24
Peak memory 195172 kb
Host smart-1734bfe3-0a3f-44c5-8e01-b6fe31eb53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964397257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1964397257
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2110043646
Short name T555
Test name
Test status
Simulation time 68243255 ps
CPU time 1.21 seconds
Started Aug 01 05:21:14 PM PDT 24
Finished Aug 01 05:21:16 PM PDT 24
Peak memory 196716 kb
Host smart-30d9f9c1-f2d9-47cd-8614-e3fa3342293c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110043646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2110043646
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2519051364
Short name T202
Test name
Test status
Simulation time 5141400279 ps
CPU time 126.03 seconds
Started Aug 01 05:21:15 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 198692 kb
Host smart-bc5c88c0-82c5-4abd-bf44-f5ccb0955338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519051364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2519051364
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.837064316
Short name T199
Test name
Test status
Simulation time 15767548 ps
CPU time 0.58 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:21 PM PDT 24
Peak memory 194384 kb
Host smart-8b458009-b69b-41ff-9d34-a1abd3896554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837064316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.837064316
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3959459396
Short name T463
Test name
Test status
Simulation time 37202895 ps
CPU time 0.73 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 194580 kb
Host smart-53d3c6d7-8206-4acd-bc6d-4cb1cd58475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959459396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3959459396
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1664685100
Short name T128
Test name
Test status
Simulation time 1051979934 ps
CPU time 8.95 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:33 PM PDT 24
Peak memory 197308 kb
Host smart-c95ac46a-b1aa-4f0a-8ff7-e1868a06589c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664685100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1664685100
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3602798717
Short name T188
Test name
Test status
Simulation time 591292090 ps
CPU time 1.05 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:23 PM PDT 24
Peak memory 196900 kb
Host smart-4bc9f314-3184-4050-a9f9-e522db92b258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602798717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3602798717
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1634481519
Short name T541
Test name
Test status
Simulation time 29417880 ps
CPU time 0.85 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 196920 kb
Host smart-f3f689ea-4829-4913-ae01-825a8a0e01b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634481519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1634481519
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2284193770
Short name T651
Test name
Test status
Simulation time 70319690 ps
CPU time 2.37 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:23 PM PDT 24
Peak memory 196840 kb
Host smart-559dd8ef-d09c-4267-9cb0-928fc8dfc640
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284193770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2284193770
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.417722275
Short name T304
Test name
Test status
Simulation time 159109753 ps
CPU time 0.94 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 196840 kb
Host smart-0cfb1177-113c-4fe8-ad17-6d9aca7291b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417722275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
417722275
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2442657934
Short name T622
Test name
Test status
Simulation time 18411906 ps
CPU time 0.77 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 197120 kb
Host smart-8715cdbe-63d2-489a-9b22-6997526bd517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442657934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2442657934
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3798173118
Short name T486
Test name
Test status
Simulation time 30478950 ps
CPU time 1.06 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 196392 kb
Host smart-d8b36261-918d-43b5-9621-83cb62dda75b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798173118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3798173118
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2112667369
Short name T340
Test name
Test status
Simulation time 138976527 ps
CPU time 1.75 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 198432 kb
Host smart-3c0c688f-3328-4bc5-9623-eba5ac0b2c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112667369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2112667369
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3587805699
Short name T120
Test name
Test status
Simulation time 103213317 ps
CPU time 1.16 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:22 PM PDT 24
Peak memory 196100 kb
Host smart-437f2391-6b8f-4378-9d77-b96b48bfe1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587805699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3587805699
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1276046087
Short name T78
Test name
Test status
Simulation time 283338627 ps
CPU time 1.17 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 196328 kb
Host smart-71e48e45-8e1e-4b2c-b70a-c9fc3106040a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276046087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1276046087
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1786035477
Short name T328
Test name
Test status
Simulation time 13673042378 ps
CPU time 201.46 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:24:45 PM PDT 24
Peak memory 198504 kb
Host smart-98208df3-cb02-408f-925d-172f270f8519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786035477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1786035477
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3249589433
Short name T644
Test name
Test status
Simulation time 42335837262 ps
CPU time 261.91 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:25:47 PM PDT 24
Peak memory 198820 kb
Host smart-e69740cb-fe08-4e75-8a01-cb9aeed31a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3249589433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3249589433
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.329058533
Short name T275
Test name
Test status
Simulation time 84056253 ps
CPU time 0.6 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 194312 kb
Host smart-c1936fa4-e38b-4536-9f30-48472282e051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329058533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.329058533
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.81412789
Short name T447
Test name
Test status
Simulation time 61716659 ps
CPU time 0.81 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 195668 kb
Host smart-c18c1a72-ba59-4f1f-a410-f9ff02e86252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81412789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.81412789
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2516583282
Short name T590
Test name
Test status
Simulation time 3300674905 ps
CPU time 21.04 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 197608 kb
Host smart-8a209249-39b6-4979-8b3f-8a479542cf73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516583282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2516583282
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1481092101
Short name T320
Test name
Test status
Simulation time 48045126 ps
CPU time 0.82 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 196408 kb
Host smart-0b2fd848-67d0-4bd6-b836-89ab246bc10a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481092101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1481092101
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.750901113
Short name T426
Test name
Test status
Simulation time 1542974116 ps
CPU time 1.2 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 196288 kb
Host smart-c6b9a4c9-64a3-4099-891b-e069e302182e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750901113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.750901113
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2606547557
Short name T192
Test name
Test status
Simulation time 331284335 ps
CPU time 2.28 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 198556 kb
Host smart-69d886b2-7d0b-46ac-9dcb-4192f8c94183
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606547557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2606547557
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1052087492
Short name T346
Test name
Test status
Simulation time 79391303 ps
CPU time 1.75 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 196236 kb
Host smart-f6212cb1-fb44-4300-8004-0834ac850d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052087492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1052087492
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1437602427
Short name T325
Test name
Test status
Simulation time 16161068 ps
CPU time 0.73 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:22 PM PDT 24
Peak memory 195940 kb
Host smart-16eb3f63-ca1c-427f-b71b-4b07d10652e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437602427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1437602427
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4139329108
Short name T620
Test name
Test status
Simulation time 151276509 ps
CPU time 1.03 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 196476 kb
Host smart-99126756-1642-4c34-a6bc-61771241e2dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139329108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4139329108
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4145409451
Short name T640
Test name
Test status
Simulation time 122552037 ps
CPU time 5.31 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 198500 kb
Host smart-55e37c1e-de19-4312-abfd-c0280ebd49ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145409451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4145409451
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.550800263
Short name T193
Test name
Test status
Simulation time 352559652 ps
CPU time 1.44 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 198528 kb
Host smart-adced0ec-175c-4575-af4f-d4d2f717cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550800263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.550800263
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.437754422
Short name T122
Test name
Test status
Simulation time 53168460 ps
CPU time 1.05 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:23 PM PDT 24
Peak memory 196276 kb
Host smart-8b6635dc-8d2a-4da2-a0fa-7f4fe7ab9376
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437754422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.437754422
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.293446427
Short name T653
Test name
Test status
Simulation time 45147959065 ps
CPU time 138.4 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:23:42 PM PDT 24
Peak memory 198728 kb
Host smart-79926cd1-7f5a-4b57-a28c-755834de849d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293446427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.293446427
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1722023587
Short name T521
Test name
Test status
Simulation time 22865912 ps
CPU time 0.57 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 194588 kb
Host smart-e8941d27-37e0-4395-bf7a-5bf4253b5318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722023587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1722023587
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3333087122
Short name T592
Test name
Test status
Simulation time 59702345 ps
CPU time 0.64 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:23 PM PDT 24
Peak memory 195140 kb
Host smart-19842715-07d8-4bf2-993e-64fabc012429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333087122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3333087122
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1405641870
Short name T292
Test name
Test status
Simulation time 1044152179 ps
CPU time 17.08 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:40 PM PDT 24
Peak memory 197440 kb
Host smart-991b21a0-7642-4874-9a3e-460bb430c3b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405641870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1405641870
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1774008366
Short name T247
Test name
Test status
Simulation time 66385212 ps
CPU time 1.02 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 196904 kb
Host smart-4f92773f-00fc-4cf9-a9b8-fb6076805231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774008366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1774008366
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1896882233
Short name T588
Test name
Test status
Simulation time 90721593 ps
CPU time 1.04 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 196556 kb
Host smart-ccd95cf7-7d2b-442b-9d9f-14434dec6bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896882233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1896882233
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1692211218
Short name T448
Test name
Test status
Simulation time 89268323 ps
CPU time 3.7 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 198772 kb
Host smart-a080fddd-4bca-4797-ad45-071017952d8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692211218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1692211218
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.515617355
Short name T383
Test name
Test status
Simulation time 33433314 ps
CPU time 0.88 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:22 PM PDT 24
Peak memory 194772 kb
Host smart-85f2427c-b46f-4b25-9140-2c32833793c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515617355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
515617355
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.516357159
Short name T641
Test name
Test status
Simulation time 43193886 ps
CPU time 0.98 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:23 PM PDT 24
Peak memory 197300 kb
Host smart-3db1ce5a-0f99-4e16-beb8-7e155d5c0c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516357159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.516357159
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.118621091
Short name T298
Test name
Test status
Simulation time 31144895 ps
CPU time 1.09 seconds
Started Aug 01 05:21:27 PM PDT 24
Finished Aug 01 05:21:28 PM PDT 24
Peak memory 196524 kb
Host smart-526c6afd-1ebf-4dc2-88f0-0492dfb89476
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118621091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.118621091
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2197496622
Short name T8
Test name
Test status
Simulation time 280447873 ps
CPU time 2.22 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 198452 kb
Host smart-db1aadfe-aebc-4f7d-9199-df772993ed97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197496622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2197496622
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2937786752
Short name T615
Test name
Test status
Simulation time 56803636 ps
CPU time 0.7 seconds
Started Aug 01 05:21:21 PM PDT 24
Finished Aug 01 05:21:21 PM PDT 24
Peak memory 194708 kb
Host smart-587c187e-2c6c-4e1c-b14e-5f1df03e210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937786752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2937786752
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3535090700
Short name T163
Test name
Test status
Simulation time 22364892 ps
CPU time 0.72 seconds
Started Aug 01 05:21:23 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 195604 kb
Host smart-3c566c19-3043-43cc-b75b-0eabcfba7279
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535090700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3535090700
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4239890307
Short name T129
Test name
Test status
Simulation time 45410319177 ps
CPU time 140.1 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:23:44 PM PDT 24
Peak memory 198728 kb
Host smart-1e4a2a40-caed-40e7-9aa9-caa3ea7e2c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239890307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4239890307
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3791886721
Short name T107
Test name
Test status
Simulation time 50598850404 ps
CPU time 406.85 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 198784 kb
Host smart-e08996bb-6f95-4759-ab36-e5ae01540df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3791886721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3791886721
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2620977445
Short name T150
Test name
Test status
Simulation time 15243111 ps
CPU time 0.62 seconds
Started Aug 01 05:21:31 PM PDT 24
Finished Aug 01 05:21:32 PM PDT 24
Peak memory 195096 kb
Host smart-72fc58c3-35d9-427c-8299-14fb27e7fe5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620977445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2620977445
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3647320279
Short name T663
Test name
Test status
Simulation time 84869965 ps
CPU time 0.76 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 195904 kb
Host smart-785c35c8-120c-4a6e-9afa-83948c22f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647320279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3647320279
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2112370354
Short name T142
Test name
Test status
Simulation time 396275139 ps
CPU time 13.95 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 197548 kb
Host smart-51709684-d49e-4779-a1a5-e0da2f8206fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112370354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2112370354
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2679903352
Short name T26
Test name
Test status
Simulation time 66155062 ps
CPU time 0.68 seconds
Started Aug 01 05:21:30 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 195060 kb
Host smart-bbbd00dd-d8a0-49db-a88c-2dd767ab39ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679903352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2679903352
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.4098316575
Short name T539
Test name
Test status
Simulation time 54161147 ps
CPU time 1.35 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 198512 kb
Host smart-08d6de25-aff0-47d6-b9f5-a5c9b026cc44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098316575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.4098316575
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2883712312
Short name T585
Test name
Test status
Simulation time 28679977 ps
CPU time 1.24 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 197256 kb
Host smart-0bcb699c-0867-4a57-922f-b2a36a44e0d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883712312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2883712312
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2995806399
Short name T261
Test name
Test status
Simulation time 69064701 ps
CPU time 2.28 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 197556 kb
Host smart-85c64e24-ae99-4f5f-b5cf-7252bd354135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995806399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2995806399
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3269229170
Short name T658
Test name
Test status
Simulation time 29165193 ps
CPU time 0.82 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:21:25 PM PDT 24
Peak memory 195868 kb
Host smart-38714ac0-3499-4a1b-80a7-63b4196c9f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269229170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3269229170
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.495571632
Short name T172
Test name
Test status
Simulation time 62939999 ps
CPU time 0.64 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 195484 kb
Host smart-7e8057fb-11d1-485c-a2ba-575fd93449b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495571632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.495571632
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.893998454
Short name T358
Test name
Test status
Simulation time 355287061 ps
CPU time 5.8 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 198484 kb
Host smart-7317fa9a-1c8b-4937-bae1-32339ae68ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893998454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.893998454
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3943468768
Short name T630
Test name
Test status
Simulation time 199300418 ps
CPU time 0.96 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 196704 kb
Host smart-19d2ce41-6c23-4742-af74-405104ce8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943468768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3943468768
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2520750852
Short name T374
Test name
Test status
Simulation time 696798532 ps
CPU time 1.43 seconds
Started Aug 01 05:21:22 PM PDT 24
Finished Aug 01 05:21:24 PM PDT 24
Peak memory 196840 kb
Host smart-6dc034e0-e181-42c3-8e41-74bd39e7b6cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520750852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2520750852
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3615639375
Short name T647
Test name
Test status
Simulation time 6194040559 ps
CPU time 134.75 seconds
Started Aug 01 05:21:24 PM PDT 24
Finished Aug 01 05:23:39 PM PDT 24
Peak memory 198680 kb
Host smart-b63c0841-a4d7-492d-a050-fd9dff9127f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615639375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3615639375
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3086155466
Short name T643
Test name
Test status
Simulation time 242211439490 ps
CPU time 1253.8 seconds
Started Aug 01 05:21:30 PM PDT 24
Finished Aug 01 05:42:24 PM PDT 24
Peak memory 198808 kb
Host smart-d4844360-43ec-4096-95f5-8788357345c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3086155466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3086155466
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2482866676
Short name T39
Test name
Test status
Simulation time 16947789 ps
CPU time 0.57 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:26 PM PDT 24
Peak memory 195076 kb
Host smart-b2dbf605-6963-43dc-bfcf-07dde125edca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482866676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2482866676
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1835699664
Short name T244
Test name
Test status
Simulation time 16794539 ps
CPU time 0.68 seconds
Started Aug 01 05:21:27 PM PDT 24
Finished Aug 01 05:21:28 PM PDT 24
Peak memory 195296 kb
Host smart-3021c560-0370-4af4-9080-309d0569b7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835699664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1835699664
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2332580683
Short name T421
Test name
Test status
Simulation time 3329998585 ps
CPU time 14.47 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 197332 kb
Host smart-128b1007-df2e-48fb-8877-33a1b12b1f6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332580683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2332580683
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3251884158
Short name T168
Test name
Test status
Simulation time 80792023 ps
CPU time 0.97 seconds
Started Aug 01 05:21:29 PM PDT 24
Finished Aug 01 05:21:30 PM PDT 24
Peak memory 197132 kb
Host smart-5b337470-0480-40ee-8ce6-3ae1929ac837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251884158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3251884158
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.336106539
Short name T349
Test name
Test status
Simulation time 73335676 ps
CPU time 1.31 seconds
Started Aug 01 05:21:29 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 197304 kb
Host smart-df95d641-f310-4cf6-a7a0-94e0f6fae35a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336106539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.336106539
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1926137180
Short name T246
Test name
Test status
Simulation time 261839024 ps
CPU time 2.2 seconds
Started Aug 01 05:21:25 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 198488 kb
Host smart-e6a02448-cea7-4b77-ab23-98666f8b4701
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926137180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1926137180
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2659425528
Short name T314
Test name
Test status
Simulation time 291250298 ps
CPU time 1.57 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 196328 kb
Host smart-b4d10afc-e345-4788-b76d-3501968f970f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659425528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2659425528
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1860074910
Short name T239
Test name
Test status
Simulation time 50398142 ps
CPU time 0.76 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 196036 kb
Host smart-d236ee2d-16c2-435c-be35-61222a38664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860074910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1860074910
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3022995611
Short name T439
Test name
Test status
Simulation time 71960631 ps
CPU time 0.83 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 197136 kb
Host smart-b647ed97-e72f-4a2b-a6d2-e1a6373d843d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022995611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3022995611
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.541090557
Short name T544
Test name
Test status
Simulation time 1370889629 ps
CPU time 5.18 seconds
Started Aug 01 05:21:29 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 198500 kb
Host smart-eb4ff988-cfb1-4db7-8cad-4a4eb5a74111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541090557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.541090557
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3727614989
Short name T300
Test name
Test status
Simulation time 537148607 ps
CPU time 1.62 seconds
Started Aug 01 05:21:30 PM PDT 24
Finished Aug 01 05:21:32 PM PDT 24
Peak memory 197324 kb
Host smart-bc102314-3a3e-4ad2-b1d1-599509f33a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727614989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3727614989
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3325996119
Short name T363
Test name
Test status
Simulation time 49991834 ps
CPU time 0.92 seconds
Started Aug 01 05:21:30 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 196572 kb
Host smart-2084d485-5aee-4eab-83f5-793c2d1ffe4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325996119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3325996119
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.107643059
Short name T82
Test name
Test status
Simulation time 5435744779 ps
CPU time 28.03 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:55 PM PDT 24
Peak memory 198776 kb
Host smart-4d94c040-6a90-49f7-8235-3d9d3491467f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107643059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.107643059
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3711267323
Short name T263
Test name
Test status
Simulation time 15778030 ps
CPU time 0.58 seconds
Started Aug 01 05:21:36 PM PDT 24
Finished Aug 01 05:21:37 PM PDT 24
Peak memory 195084 kb
Host smart-fb857ad7-dbbf-4e88-9668-02b94fcf2bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711267323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3711267323
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3134596648
Short name T423
Test name
Test status
Simulation time 17218603 ps
CPU time 0.71 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 194532 kb
Host smart-5e8c5c38-fe68-4227-b3fe-296529e9cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134596648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3134596648
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.58257771
Short name T573
Test name
Test status
Simulation time 208099005 ps
CPU time 10.49 seconds
Started Aug 01 05:21:29 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 198420 kb
Host smart-9923e4c0-5c45-4e70-8160-10b3ba017567
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58257771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.58257771
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1647798109
Short name T303
Test name
Test status
Simulation time 168725380 ps
CPU time 0.85 seconds
Started Aug 01 05:21:40 PM PDT 24
Finished Aug 01 05:21:41 PM PDT 24
Peak memory 197096 kb
Host smart-dacd74b2-c213-4ccd-9151-a43c7f4bdaae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647798109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1647798109
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1401886383
Short name T467
Test name
Test status
Simulation time 166652617 ps
CPU time 0.94 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 197632 kb
Host smart-d873c560-90d4-4548-a242-ec7ffe18bf7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401886383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1401886383
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2562798277
Short name T316
Test name
Test status
Simulation time 97798568 ps
CPU time 3.56 seconds
Started Aug 01 05:21:29 PM PDT 24
Finished Aug 01 05:21:33 PM PDT 24
Peak memory 198528 kb
Host smart-a00a72f6-762d-472c-8492-019ebfa4704c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562798277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2562798277
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.586042927
Short name T170
Test name
Test status
Simulation time 149383968 ps
CPU time 1.42 seconds
Started Aug 01 05:21:27 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 196584 kb
Host smart-336dcd48-d53f-4321-9d16-c31bfefa8881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586042927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
586042927
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3666015740
Short name T432
Test name
Test status
Simulation time 67081518 ps
CPU time 1.19 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 196452 kb
Host smart-4f455074-3cdb-4e65-8a14-aa1a217905ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666015740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3666015740
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.139578307
Short name T165
Test name
Test status
Simulation time 255193682 ps
CPU time 0.84 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 196948 kb
Host smart-9e0b5f47-4545-443c-a44c-a2d855ffbb06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139578307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.139578307
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3975822868
Short name T607
Test name
Test status
Simulation time 382002090 ps
CPU time 5.98 seconds
Started Aug 01 05:21:28 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 198364 kb
Host smart-f8cb65e8-88d1-451c-a047-f92e0fa973ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975822868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3975822868
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.510611633
Short name T265
Test name
Test status
Simulation time 75253830 ps
CPU time 1.33 seconds
Started Aug 01 05:21:27 PM PDT 24
Finished Aug 01 05:21:29 PM PDT 24
Peak memory 197108 kb
Host smart-bfb8f87a-d979-4c7a-8b5d-18958f93c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510611633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.510611633
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1653392992
Short name T684
Test name
Test status
Simulation time 69843583 ps
CPU time 1.27 seconds
Started Aug 01 05:21:26 PM PDT 24
Finished Aug 01 05:21:27 PM PDT 24
Peak memory 197420 kb
Host smart-ea590211-7b4c-420c-9534-c5993d8f65fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653392992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1653392992
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3179011896
Short name T466
Test name
Test status
Simulation time 6010891958 ps
CPU time 158.66 seconds
Started Aug 01 05:21:32 PM PDT 24
Finished Aug 01 05:24:11 PM PDT 24
Peak memory 192644 kb
Host smart-f52ff3a2-151c-4286-8aa1-4a74686bbc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179011896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3179011896
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3862499783
Short name T519
Test name
Test status
Simulation time 28064267 ps
CPU time 0.57 seconds
Started Aug 01 05:21:36 PM PDT 24
Finished Aug 01 05:21:37 PM PDT 24
Peak memory 194592 kb
Host smart-f2897bc3-04ed-4ad8-b505-48627dfe6433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862499783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3862499783
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4042013265
Short name T178
Test name
Test status
Simulation time 52567515 ps
CPU time 0.9 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 196456 kb
Host smart-b8a04950-b66a-4f12-ab5c-a35c6cd23bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042013265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4042013265
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3118601056
Short name T333
Test name
Test status
Simulation time 241327035 ps
CPU time 7.28 seconds
Started Aug 01 05:21:35 PM PDT 24
Finished Aug 01 05:21:42 PM PDT 24
Peak memory 197052 kb
Host smart-4800fccb-18b0-487e-b824-6785222ddc8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118601056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3118601056
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2816098336
Short name T145
Test name
Test status
Simulation time 682781212 ps
CPU time 1.01 seconds
Started Aug 01 05:21:39 PM PDT 24
Finished Aug 01 05:21:40 PM PDT 24
Peak memory 196732 kb
Host smart-cee77500-3f8c-4ba9-8170-7e29b382cc73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816098336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2816098336
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1420039014
Short name T631
Test name
Test status
Simulation time 51006428 ps
CPU time 1.28 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 198532 kb
Host smart-6ca40df5-f40d-493c-92b7-56a6be2a2aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420039014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1420039014
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.276689697
Short name T652
Test name
Test status
Simulation time 226471290 ps
CPU time 3.48 seconds
Started Aug 01 05:21:32 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 198492 kb
Host smart-6a70beb4-492c-4d98-9b7f-f9d0d2a372fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276689697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.276689697
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1263240013
Short name T511
Test name
Test status
Simulation time 180127198 ps
CPU time 3.42 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 197548 kb
Host smart-02ecfad3-2ee2-45e1-a4c9-62dd7eeba6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263240013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1263240013
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1537703345
Short name T523
Test name
Test status
Simulation time 37405692 ps
CPU time 0.7 seconds
Started Aug 01 05:21:37 PM PDT 24
Finished Aug 01 05:21:38 PM PDT 24
Peak memory 196552 kb
Host smart-201ef57a-77f8-4a34-ad0f-6d3141ecded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537703345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1537703345
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1156806726
Short name T438
Test name
Test status
Simulation time 185807917 ps
CPU time 1.03 seconds
Started Aug 01 05:21:37 PM PDT 24
Finished Aug 01 05:21:38 PM PDT 24
Peak memory 196996 kb
Host smart-b4df033c-0532-46cf-bccc-2f24b52771d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156806726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1156806726
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2728310828
Short name T279
Test name
Test status
Simulation time 758135540 ps
CPU time 3.46 seconds
Started Aug 01 05:21:41 PM PDT 24
Finished Aug 01 05:21:45 PM PDT 24
Peak memory 197644 kb
Host smart-c1930cf8-6f84-430d-a0ae-8624c547b408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728310828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2728310828
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3986485774
Short name T257
Test name
Test status
Simulation time 52253968 ps
CPU time 0.91 seconds
Started Aug 01 05:21:35 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 196748 kb
Host smart-cde201fe-47e0-40fd-a828-0a228e154589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986485774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3986485774
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3304936348
Short name T676
Test name
Test status
Simulation time 59812203 ps
CPU time 1.11 seconds
Started Aug 01 05:21:40 PM PDT 24
Finished Aug 01 05:21:41 PM PDT 24
Peak memory 196140 kb
Host smart-a0b2a368-a678-4d8e-97cc-b97fd38ae32b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304936348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3304936348
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.472115104
Short name T670
Test name
Test status
Simulation time 38821500638 ps
CPU time 217.98 seconds
Started Aug 01 05:21:40 PM PDT 24
Finished Aug 01 05:25:18 PM PDT 24
Peak memory 198676 kb
Host smart-b22ed852-ffba-4419-9b56-1c249290b3db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472115104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.472115104
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2479688140
Short name T436
Test name
Test status
Simulation time 12415036 ps
CPU time 0.56 seconds
Started Aug 01 05:21:41 PM PDT 24
Finished Aug 01 05:21:41 PM PDT 24
Peak memory 195040 kb
Host smart-d33ba3c9-245c-47fc-8e0d-fb05fd95ff7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479688140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2479688140
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1634428624
Short name T269
Test name
Test status
Simulation time 207241102 ps
CPU time 0.88 seconds
Started Aug 01 05:21:40 PM PDT 24
Finished Aug 01 05:21:41 PM PDT 24
Peak memory 197000 kb
Host smart-4c317fac-2273-4095-94d3-2e01f199f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634428624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1634428624
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1322128975
Short name T704
Test name
Test status
Simulation time 7187889035 ps
CPU time 24.15 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:22:10 PM PDT 24
Peak memory 198032 kb
Host smart-9afc4cc6-6860-4c98-bb21-f403169fc52b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322128975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1322128975
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2071589309
Short name T350
Test name
Test status
Simulation time 596570745 ps
CPU time 0.83 seconds
Started Aug 01 05:21:38 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 196192 kb
Host smart-a56892e0-a799-4679-acb6-150d2a8600c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071589309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2071589309
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3103092218
Short name T56
Test name
Test status
Simulation time 321182218 ps
CPU time 1.44 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 198544 kb
Host smart-db7bf31d-8e4d-4757-b63b-1ad1ac71679b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103092218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3103092218
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.425805514
Short name T77
Test name
Test status
Simulation time 88377159 ps
CPU time 3.64 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 198748 kb
Host smart-bf4c8edf-d346-443b-8852-622751b22c63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425805514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.425805514
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.197305311
Short name T650
Test name
Test status
Simulation time 234912211 ps
CPU time 3.62 seconds
Started Aug 01 05:21:32 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 198620 kb
Host smart-e6dfd9a6-4202-4367-8781-971101982ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197305311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
197305311
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4230650792
Short name T79
Test name
Test status
Simulation time 57098334 ps
CPU time 0.88 seconds
Started Aug 01 05:21:35 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 197324 kb
Host smart-2280a9d1-18a6-460f-8d82-90656b6f4cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230650792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4230650792
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1819517374
Short name T655
Test name
Test status
Simulation time 70487852 ps
CPU time 1.38 seconds
Started Aug 01 05:21:37 PM PDT 24
Finished Aug 01 05:21:38 PM PDT 24
Peak memory 198528 kb
Host smart-af9a36b3-6d47-4cfd-9805-da53ae5df690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819517374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1819517374
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1833155559
Short name T482
Test name
Test status
Simulation time 330159439 ps
CPU time 3.04 seconds
Started Aug 01 05:21:32 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 198540 kb
Host smart-6f658549-0679-4aa9-a55a-6285c5dad6eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833155559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1833155559
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2039606459
Short name T595
Test name
Test status
Simulation time 130562852 ps
CPU time 1.16 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 196824 kb
Host smart-cb612c7e-c278-43b9-954a-6398cd49b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039606459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2039606459
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2441075543
Short name T671
Test name
Test status
Simulation time 37901853 ps
CPU time 1.19 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 197064 kb
Host smart-c4f279eb-73db-4684-9de3-2017b0240090
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441075543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2441075543
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2467376391
Short name T665
Test name
Test status
Simulation time 1714750940 ps
CPU time 43.39 seconds
Started Aug 01 05:21:44 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 198648 kb
Host smart-830b8148-af55-4244-acff-66616630eab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467376391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2467376391
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2398777254
Short name T400
Test name
Test status
Simulation time 22928771 ps
CPU time 0.58 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 195344 kb
Host smart-90787fbf-132e-42e9-990b-13d4c52bad9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398777254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2398777254
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.433355194
Short name T401
Test name
Test status
Simulation time 101638351 ps
CPU time 0.9 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:20:00 PM PDT 24
Peak memory 197020 kb
Host smart-3c3a1247-850b-48e0-82a4-6e8f747f6f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433355194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.433355194
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1404460739
Short name T661
Test name
Test status
Simulation time 764747839 ps
CPU time 9.75 seconds
Started Aug 01 05:19:56 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 197464 kb
Host smart-1d18b694-75a4-4e71-8bf4-5a31dc798dd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404460739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1404460739
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.409160707
Short name T483
Test name
Test status
Simulation time 70553675 ps
CPU time 0.73 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:19:59 PM PDT 24
Peak memory 195968 kb
Host smart-ef49f808-efae-4bc5-89e0-371401a6b928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409160707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.409160707
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1709426698
Short name T633
Test name
Test status
Simulation time 378923984 ps
CPU time 1.08 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:54 PM PDT 24
Peak memory 196260 kb
Host smart-c4a3caca-f973-44da-8608-dc12c727d739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709426698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1709426698
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3700025354
Short name T180
Test name
Test status
Simulation time 100824458 ps
CPU time 2.17 seconds
Started Aug 01 05:19:52 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 198668 kb
Host smart-30c4c72c-8eec-4e2b-9b9b-1d46bf83e8e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700025354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3700025354
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2222324566
Short name T187
Test name
Test status
Simulation time 52353401 ps
CPU time 1.46 seconds
Started Aug 01 05:19:53 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196348 kb
Host smart-0dd5c577-60ca-40c8-9669-58336a119f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222324566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2222324566
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3739929764
Short name T160
Test name
Test status
Simulation time 33933510 ps
CPU time 0.95 seconds
Started Aug 01 05:19:55 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 197752 kb
Host smart-bda318ee-29a5-4b1b-84cf-b0cd2bfb8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739929764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3739929764
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.322318857
Short name T503
Test name
Test status
Simulation time 50338564 ps
CPU time 1.28 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 197332 kb
Host smart-0ee5672a-e130-49e3-bd8e-55a2eb81a0e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322318857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.322318857
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.834528147
Short name T494
Test name
Test status
Simulation time 264630202 ps
CPU time 4.34 seconds
Started Aug 01 05:19:58 PM PDT 24
Finished Aug 01 05:20:03 PM PDT 24
Peak memory 198328 kb
Host smart-e1706c49-4a22-4d18-abb2-e1cd5983ff2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834528147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.834528147
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3365696400
Short name T50
Test name
Test status
Simulation time 204109426 ps
CPU time 0.81 seconds
Started Aug 01 05:19:57 PM PDT 24
Finished Aug 01 05:19:58 PM PDT 24
Peak memory 214344 kb
Host smart-d0e05943-7607-4068-ac2a-f88ed935f007
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365696400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3365696400
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.74874511
Short name T288
Test name
Test status
Simulation time 141107801 ps
CPU time 0.79 seconds
Started Aug 01 05:19:55 PM PDT 24
Finished Aug 01 05:19:56 PM PDT 24
Peak memory 195748 kb
Host smart-b3d8c33d-db33-427f-8512-b429e4d8c191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74874511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.74874511
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3157108004
Short name T249
Test name
Test status
Simulation time 39917359 ps
CPU time 1.15 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:19:55 PM PDT 24
Peak memory 196264 kb
Host smart-e7e5848a-e6f3-4d02-9877-d0f376444f7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157108004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3157108004
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3381653951
Short name T146
Test name
Test status
Simulation time 22434806967 ps
CPU time 169.06 seconds
Started Aug 01 05:19:54 PM PDT 24
Finished Aug 01 05:22:43 PM PDT 24
Peak memory 198744 kb
Host smart-197c95f0-9b33-47b7-9301-bd040b23e199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381653951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3381653951
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.386462650
Short name T504
Test name
Test status
Simulation time 20903712 ps
CPU time 0.55 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 194584 kb
Host smart-6aef1f8c-9a08-44bf-8605-06e15427f983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386462650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.386462650
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4017791453
Short name T449
Test name
Test status
Simulation time 46619934 ps
CPU time 0.94 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 196904 kb
Host smart-a8fef420-8777-4116-b9d2-dc4194294d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017791453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4017791453
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3463326921
Short name T372
Test name
Test status
Simulation time 2904935277 ps
CPU time 10.93 seconds
Started Aug 01 05:21:39 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 197404 kb
Host smart-9f4081a6-2a0d-43f1-a820-58ad6485b985
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463326921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3463326921
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.589408988
Short name T317
Test name
Test status
Simulation time 58568501 ps
CPU time 1.03 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 197080 kb
Host smart-a828dc32-4a31-4761-95c9-4ceaa31f5f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589408988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.589408988
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1370094067
Short name T277
Test name
Test status
Simulation time 32524055 ps
CPU time 0.96 seconds
Started Aug 01 05:21:38 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 197212 kb
Host smart-7e262810-fdf8-4ff3-8ff0-1aa8ec9da62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370094067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1370094067
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.843743477
Short name T264
Test name
Test status
Simulation time 1139470838 ps
CPU time 2.68 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:48 PM PDT 24
Peak memory 198744 kb
Host smart-01a8532b-18eb-4afe-be49-bd41ca94ffef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843743477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.843743477
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3591667715
Short name T686
Test name
Test status
Simulation time 255035223 ps
CPU time 1.75 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 196552 kb
Host smart-e6054a00-4d0a-49c0-929b-913265c8146f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591667715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3591667715
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3104002032
Short name T528
Test name
Test status
Simulation time 57499405 ps
CPU time 1.2 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 196396 kb
Host smart-ac86d0b4-4d5d-4823-9375-955eee1de556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104002032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3104002032
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3352462799
Short name T639
Test name
Test status
Simulation time 186487372 ps
CPU time 1.29 seconds
Started Aug 01 05:21:38 PM PDT 24
Finished Aug 01 05:21:39 PM PDT 24
Peak memory 197352 kb
Host smart-3b71e173-f7a9-473b-be44-4d4b943f9ab7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352462799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3352462799
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.918390113
Short name T19
Test name
Test status
Simulation time 80304352 ps
CPU time 3.42 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 198552 kb
Host smart-6dd0f65a-ed15-4a3b-aead-3058c5d2ab97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918390113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.918390113
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2646850463
Short name T319
Test name
Test status
Simulation time 77673710 ps
CPU time 1.46 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 197280 kb
Host smart-51d789fe-bc57-41a5-8a34-7a8920df0f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646850463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2646850463
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2503090161
Short name T502
Test name
Test status
Simulation time 440549394 ps
CPU time 0.76 seconds
Started Aug 01 05:21:37 PM PDT 24
Finished Aug 01 05:21:38 PM PDT 24
Peak memory 195572 kb
Host smart-c89d8324-cbb9-4b75-b8c5-6dac6cd855c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503090161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2503090161
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4154317575
Short name T616
Test name
Test status
Simulation time 30089160148 ps
CPU time 78.29 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:23:03 PM PDT 24
Peak memory 198728 kb
Host smart-0a73effa-00b1-40ee-99db-85bfec5fe5ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154317575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4154317575
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1391478952
Short name T623
Test name
Test status
Simulation time 35598510 ps
CPU time 0.59 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 194376 kb
Host smart-7f93eb44-5ec2-4dc6-8f6a-d743f856eb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391478952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1391478952
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.853474370
Short name T515
Test name
Test status
Simulation time 16419314 ps
CPU time 0.59 seconds
Started Aug 01 05:21:32 PM PDT 24
Finished Aug 01 05:21:33 PM PDT 24
Peak memory 194488 kb
Host smart-d5d99089-1490-4e5f-9f9d-f781bc9435e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853474370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.853474370
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.88099984
Short name T499
Test name
Test status
Simulation time 2302386622 ps
CPU time 12.49 seconds
Started Aug 01 05:21:57 PM PDT 24
Finished Aug 01 05:22:10 PM PDT 24
Peak memory 197280 kb
Host smart-7cbc980c-571b-49d0-8784-9d5d00ce38ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88099984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stress
.88099984
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.4227964619
Short name T578
Test name
Test status
Simulation time 95699598 ps
CPU time 1.07 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 197052 kb
Host smart-6e063841-acba-41ca-8dd5-b2c3108b5c73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227964619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.4227964619
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3797657722
Short name T621
Test name
Test status
Simulation time 228943004 ps
CPU time 0.84 seconds
Started Aug 01 05:21:57 PM PDT 24
Finished Aug 01 05:21:58 PM PDT 24
Peak memory 196668 kb
Host smart-ae744f91-1ce2-40d6-9fa7-3ea304389107
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797657722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3797657722
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1498272422
Short name T216
Test name
Test status
Simulation time 862405902 ps
CPU time 3.19 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 198456 kb
Host smart-7724a6df-d1ad-4d56-9e57-30e5d60960cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498272422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1498272422
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.302741027
Short name T660
Test name
Test status
Simulation time 52214032 ps
CPU time 1.67 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:48 PM PDT 24
Peak memory 196256 kb
Host smart-d48c0373-e7ff-48a7-ab96-4f856c7e9a57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302741027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
302741027
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.261185948
Short name T59
Test name
Test status
Simulation time 87708024 ps
CPU time 0.71 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 195896 kb
Host smart-1a95c80d-6d39-45a6-ac3e-0df1d5e4a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261185948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.261185948
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2250244158
Short name T117
Test name
Test status
Simulation time 23536876 ps
CPU time 0.71 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:34 PM PDT 24
Peak memory 195836 kb
Host smart-cf26ce59-55c9-4429-86e1-e2189bc04b7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250244158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2250244158
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4227499887
Short name T342
Test name
Test status
Simulation time 152481955 ps
CPU time 3.87 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:52 PM PDT 24
Peak memory 198472 kb
Host smart-d1df4fb7-453a-446d-9beb-c3e3ab931c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227499887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4227499887
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1273432884
Short name T381
Test name
Test status
Simulation time 117409145 ps
CPU time 0.94 seconds
Started Aug 01 05:21:34 PM PDT 24
Finished Aug 01 05:21:36 PM PDT 24
Peak memory 196168 kb
Host smart-d312f417-1016-461d-8ff5-794b011d1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273432884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1273432884
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3050250141
Short name T232
Test name
Test status
Simulation time 66343320 ps
CPU time 1.12 seconds
Started Aug 01 05:21:33 PM PDT 24
Finished Aug 01 05:21:35 PM PDT 24
Peak memory 196232 kb
Host smart-814d3244-0b86-492e-a3da-3c68f479abb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050250141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3050250141
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1310007034
Short name T416
Test name
Test status
Simulation time 6553137208 ps
CPU time 87.99 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:23:17 PM PDT 24
Peak memory 198652 kb
Host smart-4c2911f6-1735-4507-b4cc-234f36345cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310007034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1310007034
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3345397423
Short name T687
Test name
Test status
Simulation time 51519292957 ps
CPU time 336.27 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:27:26 PM PDT 24
Peak memory 198772 kb
Host smart-911c582d-e9df-4136-a6c7-c03f2b646750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3345397423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3345397423
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.776884292
Short name T17
Test name
Test status
Simulation time 60353529 ps
CPU time 0.58 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:48 PM PDT 24
Peak memory 194560 kb
Host smart-e83860ab-f1fa-4ca2-a205-ba70ce363e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776884292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.776884292
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4118663427
Short name T241
Test name
Test status
Simulation time 99487511 ps
CPU time 0.9 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:48 PM PDT 24
Peak memory 196416 kb
Host smart-93a7733e-4ae5-40a1-bf6b-ce82ff0d89e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118663427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4118663427
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.983958473
Short name T468
Test name
Test status
Simulation time 761695373 ps
CPU time 9.73 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:55 PM PDT 24
Peak memory 197292 kb
Host smart-3f7d117a-54af-477d-af17-8342602323d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983958473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.983958473
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2001047752
Short name T399
Test name
Test status
Simulation time 82435638 ps
CPU time 0.76 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 196260 kb
Host smart-2683b8cb-42d7-4b3f-a5fc-d1e0657c3b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001047752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2001047752
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3665435109
Short name T419
Test name
Test status
Simulation time 81885256 ps
CPU time 0.88 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 197668 kb
Host smart-b2fa91ea-4a94-444d-abeb-93b29b1a493b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665435109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3665435109
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.473290394
Short name T709
Test name
Test status
Simulation time 152815490 ps
CPU time 3.06 seconds
Started Aug 01 05:21:50 PM PDT 24
Finished Aug 01 05:21:53 PM PDT 24
Peak memory 198700 kb
Host smart-c96bda67-87a9-47ac-a472-ba2c9a053892
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473290394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.473290394
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.468143263
Short name T404
Test name
Test status
Simulation time 326315953 ps
CPU time 1.58 seconds
Started Aug 01 05:21:57 PM PDT 24
Finished Aug 01 05:21:59 PM PDT 24
Peak memory 196544 kb
Host smart-9d40f586-94cc-4e6e-8842-f55dbaa3416e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468143263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
468143263
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2726256599
Short name T534
Test name
Test status
Simulation time 34447979 ps
CPU time 0.72 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 195780 kb
Host smart-42bb461b-c288-4ada-b0c5-29c7c1407a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726256599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2726256599
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.972623087
Short name T459
Test name
Test status
Simulation time 160230827 ps
CPU time 1.44 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 197428 kb
Host smart-ebbfa698-5e20-4b63-b38d-990e346044c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972623087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.972623087
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3222726191
Short name T516
Test name
Test status
Simulation time 568409387 ps
CPU time 4.9 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:53 PM PDT 24
Peak memory 198480 kb
Host smart-910539f1-bdb7-41e0-9e97-007637f77043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222726191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3222726191
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3859220332
Short name T299
Test name
Test status
Simulation time 63870087 ps
CPU time 1.25 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 196896 kb
Host smart-acf513c2-5a67-4b78-9133-20cb9bf67a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859220332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3859220332
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1535979194
Short name T70
Test name
Test status
Simulation time 78583481 ps
CPU time 1.27 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 196212 kb
Host smart-a73c7e25-4a52-4dc7-94a1-fd5e348cc0f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535979194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1535979194
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2000208656
Short name T596
Test name
Test status
Simulation time 4643216460 ps
CPU time 132.21 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 198672 kb
Host smart-373e0ed9-b5f8-4133-9eb2-678c461246d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000208656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2000208656
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2997761361
Short name T31
Test name
Test status
Simulation time 50831583161 ps
CPU time 1319.66 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:43:48 PM PDT 24
Peak memory 198868 kb
Host smart-a8723b0c-6326-45a0-b7b7-e97e236c0558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2997761361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2997761361
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.603416696
Short name T357
Test name
Test status
Simulation time 52398090 ps
CPU time 0.59 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 195364 kb
Host smart-ee11407b-5005-41a8-b0ff-e601cd7f3b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603416696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.603416696
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1100800980
Short name T80
Test name
Test status
Simulation time 25459935 ps
CPU time 0.7 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:45 PM PDT 24
Peak memory 195272 kb
Host smart-cc91b409-aa7e-4f2a-8a1d-61ee6ba09bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100800980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1100800980
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2944323226
Short name T591
Test name
Test status
Simulation time 326566173 ps
CPU time 3.82 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 196016 kb
Host smart-0d2779c9-ce9e-4709-b30f-f314c3bdd1bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944323226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2944323226
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1334517531
Short name T680
Test name
Test status
Simulation time 103272343 ps
CPU time 1.18 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 197096 kb
Host smart-6a8701ba-5ab5-4dad-8490-b8448966eff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334517531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1334517531
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2782419759
Short name T624
Test name
Test status
Simulation time 70797058 ps
CPU time 0.86 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 196296 kb
Host smart-5cbb889d-a748-4a44-b34f-20f89980df03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782419759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2782419759
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1584275310
Short name T67
Test name
Test status
Simulation time 82286223 ps
CPU time 1.72 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 197024 kb
Host smart-2d1ae1f3-866d-4f6d-989b-ca471cce83e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584275310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1584275310
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2163338258
Short name T638
Test name
Test status
Simulation time 125214643 ps
CPU time 3.36 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:51 PM PDT 24
Peak memory 197636 kb
Host smart-2a9b9861-169b-4e72-9f8f-a77f5f044a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163338258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2163338258
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2449080862
Short name T367
Test name
Test status
Simulation time 43602813 ps
CPU time 1.02 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 196424 kb
Host smart-e8393731-e6f3-477d-9bad-fea96bf2be67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449080862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2449080862
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.331043838
Short name T260
Test name
Test status
Simulation time 94796151 ps
CPU time 0.83 seconds
Started Aug 01 05:21:57 PM PDT 24
Finished Aug 01 05:21:58 PM PDT 24
Peak memory 195904 kb
Host smart-b36f5e6a-2ce3-422b-bdc7-1e70997c1833
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331043838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.331043838
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1659063858
Short name T132
Test name
Test status
Simulation time 701994190 ps
CPU time 3.38 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:51 PM PDT 24
Peak memory 198516 kb
Host smart-ce82062a-0d9d-45e4-8101-46ed39ff4ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659063858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1659063858
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.645757656
Short name T155
Test name
Test status
Simulation time 43212490 ps
CPU time 1.29 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 198476 kb
Host smart-87bf058c-4192-4326-9a8e-74e056488dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645757656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.645757656
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1038307950
Short name T30
Test name
Test status
Simulation time 84167582 ps
CPU time 1.27 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 197060 kb
Host smart-7ecef121-76b1-4a7c-9fe4-c1762de59e55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038307950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1038307950
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2272109942
Short name T282
Test name
Test status
Simulation time 3612101188 ps
CPU time 79.76 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:23:06 PM PDT 24
Peak memory 197860 kb
Host smart-efe8a668-71cb-4712-bcf0-480c08c66800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272109942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2272109942
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2605690377
Short name T440
Test name
Test status
Simulation time 141631503 ps
CPU time 0.55 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:48 PM PDT 24
Peak memory 194408 kb
Host smart-37a6256e-f9e8-4f25-b5fa-2d42365762da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605690377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2605690377
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3312493565
Short name T326
Test name
Test status
Simulation time 23867465 ps
CPU time 0.67 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 194532 kb
Host smart-cc580e28-70a7-4ffc-bebf-3c1f6756d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312493565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3312493565
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.945140649
Short name T224
Test name
Test status
Simulation time 1066712604 ps
CPU time 10.83 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:58 PM PDT 24
Peak memory 197432 kb
Host smart-575f816e-d955-4870-8068-54772b13d3c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945140649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.945140649
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4084209552
Short name T370
Test name
Test status
Simulation time 287549024 ps
CPU time 1.02 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 198240 kb
Host smart-5a197de7-b4bf-47df-a5d1-381a1006ff89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084209552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4084209552
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3209426188
Short name T194
Test name
Test status
Simulation time 40304068 ps
CPU time 1.06 seconds
Started Aug 01 05:21:50 PM PDT 24
Finished Aug 01 05:21:51 PM PDT 24
Peak memory 196976 kb
Host smart-63ea1751-bfd5-4aed-85af-ed7ccac75d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209426188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3209426188
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2489765040
Short name T636
Test name
Test status
Simulation time 37541395 ps
CPU time 1.55 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:21:49 PM PDT 24
Peak memory 196800 kb
Host smart-6bb971c3-20f3-4cdb-9ca6-c8c329ebb712
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489765040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2489765040
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1093289962
Short name T533
Test name
Test status
Simulation time 94403948 ps
CPU time 2.27 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:51 PM PDT 24
Peak memory 197624 kb
Host smart-a8996e3a-ce37-42c3-abba-b150573f644f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093289962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1093289962
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3847900099
Short name T418
Test name
Test status
Simulation time 24324023 ps
CPU time 0.72 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:46 PM PDT 24
Peak memory 196508 kb
Host smart-684db765-2e7d-41b1-83bb-957d3e124c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847900099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3847900099
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1992446209
Short name T308
Test name
Test status
Simulation time 32844559 ps
CPU time 0.88 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 196220 kb
Host smart-e5e6e7e3-4cb6-44a7-be72-8f7dbe436bba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992446209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1992446209
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.599423182
Short name T149
Test name
Test status
Simulation time 118217007 ps
CPU time 1.63 seconds
Started Aug 01 05:21:45 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 198496 kb
Host smart-36330ca6-2427-49ae-9820-b9e8ba645e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599423182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.599423182
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1311739494
Short name T348
Test name
Test status
Simulation time 164456269 ps
CPU time 1.32 seconds
Started Aug 01 05:21:48 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 196060 kb
Host smart-b90df96b-0c69-4a32-be7e-c5f09d428235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311739494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1311739494
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2838137734
Short name T531
Test name
Test status
Simulation time 32584208 ps
CPU time 0.97 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 196664 kb
Host smart-836b3f64-12f2-43aa-bedf-575e07b9fc18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838137734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2838137734
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2635482869
Short name T322
Test name
Test status
Simulation time 8793216486 ps
CPU time 109.99 seconds
Started Aug 01 05:21:47 PM PDT 24
Finished Aug 01 05:23:38 PM PDT 24
Peak memory 198708 kb
Host smart-369201cd-5de1-4bdc-9746-1088687cd657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635482869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2635482869
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3936730948
Short name T371
Test name
Test status
Simulation time 28528756 ps
CPU time 0.53 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 194460 kb
Host smart-1ef012d9-ab66-45da-a119-130bb8b35b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936730948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3936730948
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2005685287
Short name T176
Test name
Test status
Simulation time 17870837 ps
CPU time 0.68 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 194480 kb
Host smart-3f5d49de-d2cf-4fb3-9c5d-b15f14d2be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005685287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2005685287
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.389619719
Short name T226
Test name
Test status
Simulation time 1221483273 ps
CPU time 20.6 seconds
Started Aug 01 05:22:02 PM PDT 24
Finished Aug 01 05:22:23 PM PDT 24
Peak memory 196068 kb
Host smart-59c2bfb2-a927-4535-909a-3983526703dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389619719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.389619719
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.937300580
Short name T564
Test name
Test status
Simulation time 1274197721 ps
CPU time 0.92 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197376 kb
Host smart-61968ddf-78e2-453d-bac8-5d6fbd05085d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937300580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.937300580
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4074293992
Short name T378
Test name
Test status
Simulation time 93094074 ps
CPU time 1.31 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 197556 kb
Host smart-eef2c8d7-b06e-47d9-b292-18d081e73037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074293992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4074293992
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2602052328
Short name T465
Test name
Test status
Simulation time 60450246 ps
CPU time 2.66 seconds
Started Aug 01 05:22:02 PM PDT 24
Finished Aug 01 05:22:05 PM PDT 24
Peak memory 198452 kb
Host smart-c141c0e9-f99e-42b0-9817-0b0d14a9be29
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602052328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2602052328
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2492332278
Short name T284
Test name
Test status
Simulation time 125871308 ps
CPU time 2.67 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 197512 kb
Host smart-0743ce5a-0d5c-4410-8e3f-4529ee400632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492332278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2492332278
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2779467133
Short name T354
Test name
Test status
Simulation time 96942703 ps
CPU time 1.05 seconds
Started Aug 01 05:21:57 PM PDT 24
Finished Aug 01 05:21:58 PM PDT 24
Peak memory 196372 kb
Host smart-3abe32c7-d3ab-4f1c-948c-89ccd7a1fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779467133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2779467133
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4025228613
Short name T425
Test name
Test status
Simulation time 159470638 ps
CPU time 1.03 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 197152 kb
Host smart-1739afe9-9a06-46ff-9c62-7269ddee52ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025228613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4025228613
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3707078933
Short name T332
Test name
Test status
Simulation time 184595975 ps
CPU time 2.79 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 198540 kb
Host smart-dc580d51-50fc-4cab-9b38-70edc8f2ebbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707078933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3707078933
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2635207320
Short name T505
Test name
Test status
Simulation time 32648183 ps
CPU time 1.03 seconds
Started Aug 01 05:21:46 PM PDT 24
Finished Aug 01 05:21:47 PM PDT 24
Peak memory 196300 kb
Host smart-b683eeb0-4ed1-45a0-8737-b1b1ab3ea828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635207320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2635207320
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.4172943945
Short name T437
Test name
Test status
Simulation time 140265818 ps
CPU time 1.2 seconds
Started Aug 01 05:21:49 PM PDT 24
Finished Aug 01 05:21:50 PM PDT 24
Peak memory 196944 kb
Host smart-5258467c-c21d-472d-bd35-5e0c95c2571a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172943945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.4172943945
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.297603553
Short name T115
Test name
Test status
Simulation time 10063000418 ps
CPU time 115.42 seconds
Started Aug 01 05:22:04 PM PDT 24
Finished Aug 01 05:24:00 PM PDT 24
Peak memory 198656 kb
Host smart-abb6362d-32b8-4272-88f9-4da8a4c296d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297603553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.297603553
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.527692607
Short name T40
Test name
Test status
Simulation time 22827882 ps
CPU time 0.56 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 194452 kb
Host smart-f6491334-037d-426f-a5d8-3e06c277aee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527692607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.527692607
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3943914671
Short name T608
Test name
Test status
Simulation time 30162647 ps
CPU time 0.67 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 194480 kb
Host smart-28882402-2b1d-4e39-8ed0-5c763117dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943914671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3943914671
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3260501750
Short name T281
Test name
Test status
Simulation time 6599588313 ps
CPU time 28.86 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 197516 kb
Host smart-9c2c5c30-5517-40e4-88ab-3f9f76bee440
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260501750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3260501750
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2617712521
Short name T451
Test name
Test status
Simulation time 257838008 ps
CPU time 0.92 seconds
Started Aug 01 05:22:04 PM PDT 24
Finished Aug 01 05:22:05 PM PDT 24
Peak memory 197632 kb
Host smart-3dd48c1c-a249-4730-912b-6f15650a688c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617712521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2617712521
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.764014698
Short name T398
Test name
Test status
Simulation time 53523661 ps
CPU time 0.7 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 194740 kb
Host smart-32651d3d-a282-4af2-b76f-7e1113236fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764014698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.764014698
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.962565886
Short name T637
Test name
Test status
Simulation time 71431619 ps
CPU time 3 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 198488 kb
Host smart-bd505984-2522-498f-b708-7273ca9a732d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962565886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.962565886
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3517240514
Short name T75
Test name
Test status
Simulation time 381032563 ps
CPU time 2.88 seconds
Started Aug 01 05:22:04 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 196336 kb
Host smart-1290dbdb-7c11-45d2-9d22-a35fd0e035e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517240514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3517240514
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.337237180
Short name T252
Test name
Test status
Simulation time 170268115 ps
CPU time 1.05 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 196624 kb
Host smart-611646e0-1465-4dd2-af55-ef471de5da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337237180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.337237180
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2749386929
Short name T659
Test name
Test status
Simulation time 53487094 ps
CPU time 1.2 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 196420 kb
Host smart-f5198583-1604-4f3a-a409-afc9d3cf2722
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749386929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2749386929
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4247221669
Short name T315
Test name
Test status
Simulation time 95471027 ps
CPU time 2.3 seconds
Started Aug 01 05:22:08 PM PDT 24
Finished Aug 01 05:22:10 PM PDT 24
Peak memory 198440 kb
Host smart-19c679d6-902b-4c4a-bf61-d8528d6c4581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247221669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4247221669
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3740312608
Short name T559
Test name
Test status
Simulation time 53937079 ps
CPU time 1.03 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:22:05 PM PDT 24
Peak memory 196972 kb
Host smart-b0f23b38-1fa8-4dbe-bcda-6dc84d33018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740312608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3740312608
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4270741737
Short name T236
Test name
Test status
Simulation time 55801022 ps
CPU time 0.95 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:22:04 PM PDT 24
Peak memory 197140 kb
Host smart-0e913111-7a6f-41c3-aea3-099097a8b340
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270741737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4270741737
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1805677845
Short name T417
Test name
Test status
Simulation time 45055664710 ps
CPU time 152.13 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 198680 kb
Host smart-bd44c9c9-d246-42d1-b583-77fdbc91caed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805677845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1805677845
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1198197884
Short name T73
Test name
Test status
Simulation time 23758302 ps
CPU time 0.57 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 194436 kb
Host smart-bb9593e4-b208-4c52-8608-f662dda438c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198197884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1198197884
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2729513628
Short name T69
Test name
Test status
Simulation time 19554849 ps
CPU time 0.74 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 196736 kb
Host smart-f441db24-b625-4128-9b3b-6f7567fe2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729513628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2729513628
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.535970311
Short name T538
Test name
Test status
Simulation time 5145641740 ps
CPU time 25.52 seconds
Started Aug 01 05:22:08 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 197508 kb
Host smart-bf5849d2-7ee8-4737-b0c3-46f54e0489b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535970311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.535970311
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.564004089
Short name T25
Test name
Test status
Simulation time 419425712 ps
CPU time 0.96 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 196456 kb
Host smart-0423538e-709d-45ae-b994-d26cfed149e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564004089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.564004089
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.542190820
Short name T191
Test name
Test status
Simulation time 239756338 ps
CPU time 1.03 seconds
Started Aug 01 05:22:04 PM PDT 24
Finished Aug 01 05:22:05 PM PDT 24
Peak memory 197244 kb
Host smart-7ffc519e-af19-41f3-a42e-02a84058e17b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542190820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.542190820
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2673495164
Short name T657
Test name
Test status
Simulation time 41220079 ps
CPU time 1.6 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 197212 kb
Host smart-3349a041-60e5-4698-9f82-1c2248da1c29
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673495164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2673495164
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1560379633
Short name T238
Test name
Test status
Simulation time 65130372 ps
CPU time 1.52 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197060 kb
Host smart-7a0d0076-8343-460a-8a2f-5ce0fa5e6da9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560379633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1560379633
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3130037303
Short name T677
Test name
Test status
Simulation time 75874683 ps
CPU time 1.45 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197808 kb
Host smart-861fc273-dc5f-4f8c-8e2b-300fd1802475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130037303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3130037303
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.524320039
Short name T169
Test name
Test status
Simulation time 77202860 ps
CPU time 1.03 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 196552 kb
Host smart-d4a61aa3-4239-4991-a102-6435b85deb14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524320039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.524320039
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1739097338
Short name T267
Test name
Test status
Simulation time 1318576944 ps
CPU time 4.99 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:12 PM PDT 24
Peak memory 198372 kb
Host smart-64eb112a-13ec-4845-b652-0115484f0caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739097338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1739097338
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1180647084
Short name T12
Test name
Test status
Simulation time 284270915 ps
CPU time 1.12 seconds
Started Aug 01 05:22:12 PM PDT 24
Finished Aug 01 05:22:13 PM PDT 24
Peak memory 196092 kb
Host smart-a27d9852-35ed-4049-96c1-d6bcfd2fd4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180647084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1180647084
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3792022293
Short name T167
Test name
Test status
Simulation time 69729832 ps
CPU time 1.26 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 197020 kb
Host smart-744aa2e8-389f-4c43-a4bf-355b5d29114f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792022293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3792022293
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2829250460
Short name T175
Test name
Test status
Simulation time 4550530292 ps
CPU time 62.32 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:23:05 PM PDT 24
Peak memory 198740 kb
Host smart-af48a38a-669d-451b-b788-0e0ec9963b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829250460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2829250460
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4151196688
Short name T445
Test name
Test status
Simulation time 14180801 ps
CPU time 0.59 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 195096 kb
Host smart-9065f170-ade5-4211-9d39-6a0bfe189645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151196688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4151196688
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3048435413
Short name T195
Test name
Test status
Simulation time 48537235 ps
CPU time 0.73 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 194556 kb
Host smart-0e231dbf-391d-48b1-b304-05d7a24f1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048435413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3048435413
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.237769210
Short name T593
Test name
Test status
Simulation time 2939436606 ps
CPU time 20.04 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 197272 kb
Host smart-3902fe8d-8c11-4f5b-92ad-bbaad9eb2dba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237769210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.237769210
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3380249795
Short name T324
Test name
Test status
Simulation time 158876454 ps
CPU time 1.04 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 196960 kb
Host smart-1d2236a8-bcd3-47cb-a856-6522ebe9fe64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380249795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3380249795
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3909141369
Short name T229
Test name
Test status
Simulation time 27586665 ps
CPU time 0.77 seconds
Started Aug 01 05:22:03 PM PDT 24
Finished Aug 01 05:22:04 PM PDT 24
Peak memory 195752 kb
Host smart-4dd4acaa-a0a8-4e35-8b4b-dafa1f4868f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909141369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3909141369
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4092967193
Short name T268
Test name
Test status
Simulation time 212636029 ps
CPU time 2.08 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 198540 kb
Host smart-6e4b5905-ddfc-4436-b9d7-804038ad1177
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092967193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4092967193
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2632735228
Short name T138
Test name
Test status
Simulation time 328461144 ps
CPU time 2.53 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 196308 kb
Host smart-2bb36008-bb10-475a-8e9f-95367bb55449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632735228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2632735228
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2055011994
Short name T286
Test name
Test status
Simulation time 43681257 ps
CPU time 0.99 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 196580 kb
Host smart-f19ecbaa-559a-440b-aefa-1331a301ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055011994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2055011994
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.532153010
Short name T441
Test name
Test status
Simulation time 52271339 ps
CPU time 0.94 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 196972 kb
Host smart-b6d9fa0e-df78-4f69-befc-e570a6661d44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532153010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.532153010
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_smoke.912382215
Short name T240
Test name
Test status
Simulation time 55613928 ps
CPU time 1.06 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197004 kb
Host smart-e60b4b7d-695b-4bee-8993-16e91c288450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912382215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.912382215
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.734493688
Short name T583
Test name
Test status
Simulation time 64649547 ps
CPU time 1.13 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 196172 kb
Host smart-8f555833-17c0-41b7-a9db-41e1c30aced0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734493688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.734493688
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3237247017
Short name T514
Test name
Test status
Simulation time 20240783401 ps
CPU time 88.29 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:23:34 PM PDT 24
Peak memory 192524 kb
Host smart-e755023d-afd5-4aa3-9400-9d9047fe3c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237247017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3237247017
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3975754464
Short name T207
Test name
Test status
Simulation time 93611163 ps
CPU time 0.6 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:06 PM PDT 24
Peak memory 195116 kb
Host smart-b249f93e-b935-4be5-9376-14f519ed85cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975754464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3975754464
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.444389267
Short name T242
Test name
Test status
Simulation time 213256277 ps
CPU time 0.85 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 196488 kb
Host smart-07152b7a-b6b5-4140-b24a-88447b4c582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444389267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.444389267
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2068497480
Short name T557
Test name
Test status
Simulation time 834733557 ps
CPU time 25.89 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 198512 kb
Host smart-5f0b9d2b-e9fc-4301-a6e3-470badf0b232
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068497480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2068497480
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3290515588
Short name T572
Test name
Test status
Simulation time 103377680 ps
CPU time 0.66 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 195116 kb
Host smart-6b72dbd8-d08f-4fcc-a0bd-67be503d3f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290515588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3290515588
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.487473702
Short name T297
Test name
Test status
Simulation time 29430942 ps
CPU time 0.81 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 196040 kb
Host smart-0062849c-c3a0-42fd-860a-3cb73b479f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487473702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.487473702
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.815886054
Short name T642
Test name
Test status
Simulation time 279359976 ps
CPU time 2.88 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:10 PM PDT 24
Peak memory 198592 kb
Host smart-0a55c465-6974-4574-93a8-b5b6ac730160
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815886054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.815886054
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3979911636
Short name T68
Test name
Test status
Simulation time 533895919 ps
CPU time 3.09 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:10 PM PDT 24
Peak memory 197856 kb
Host smart-73806e47-1e0b-4772-a3ab-e1d4274f2f29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979911636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3979911636
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1844479928
Short name T415
Test name
Test status
Simulation time 55682602 ps
CPU time 1.28 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197544 kb
Host smart-698269f4-f204-4880-b4ea-b6071420c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844479928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1844479928
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3263273938
Short name T598
Test name
Test status
Simulation time 60286407 ps
CPU time 1.19 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:08 PM PDT 24
Peak memory 196284 kb
Host smart-7f836a6f-ba4a-43c8-8dc6-1eeb6f349331
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263273938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3263273938
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1627539327
Short name T582
Test name
Test status
Simulation time 1852295212 ps
CPU time 4.23 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:11 PM PDT 24
Peak memory 198556 kb
Host smart-50edbe0c-16cc-4727-9b4f-74cb182946fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627539327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1627539327
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3489747120
Short name T492
Test name
Test status
Simulation time 59879972 ps
CPU time 1.21 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:22:07 PM PDT 24
Peak memory 197364 kb
Host smart-fa13e522-8b94-4d29-ad0e-116e6cd4b2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489747120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3489747120
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2846951062
Short name T158
Test name
Test status
Simulation time 465735216 ps
CPU time 1.2 seconds
Started Aug 01 05:22:08 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 196104 kb
Host smart-bc2f7d9b-1a33-40ca-b54a-ded6627a2620
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846951062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2846951062
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.642320521
Short name T481
Test name
Test status
Simulation time 30670387866 ps
CPU time 175.21 seconds
Started Aug 01 05:22:06 PM PDT 24
Finished Aug 01 05:25:01 PM PDT 24
Peak memory 198668 kb
Host smart-0defaee7-1dca-4ac0-9bac-9eb469a0db12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642320521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.642320521
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4088990165
Short name T208
Test name
Test status
Simulation time 18456369 ps
CPU time 0.61 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 194388 kb
Host smart-660d663d-9e86-4fde-ad72-5d1deb2354c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088990165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4088990165
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3830197566
Short name T271
Test name
Test status
Simulation time 97010426 ps
CPU time 0.76 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 195720 kb
Host smart-9d9c2ee1-d1a7-4068-a851-0b97b2a15a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830197566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3830197566
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.256869572
Short name T675
Test name
Test status
Simulation time 582984149 ps
CPU time 19.55 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:27 PM PDT 24
Peak memory 197384 kb
Host smart-f4e0cef6-8e2e-47a4-92d7-2828dc5fe467
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256869572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.256869572
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2547103583
Short name T442
Test name
Test status
Simulation time 46456668 ps
CPU time 0.74 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196276 kb
Host smart-ec83f16c-590a-48d7-a7f8-6068babd114e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547103583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2547103583
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3670332047
Short name T487
Test name
Test status
Simulation time 170932675 ps
CPU time 1.34 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 197176 kb
Host smart-5eb5b143-0f4b-4445-8f3f-2040c1542089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670332047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3670332047
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1661958805
Short name T485
Test name
Test status
Simulation time 280677045 ps
CPU time 2.83 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 198772 kb
Host smart-c00d7888-708e-49e2-9bfe-bf37e8c7ee5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661958805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1661958805
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2269619971
Short name T179
Test name
Test status
Simulation time 259995294 ps
CPU time 2.18 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 198576 kb
Host smart-87ab2263-13b6-4403-977f-dc6697e095b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269619971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2269619971
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.762822376
Short name T217
Test name
Test status
Simulation time 136048669 ps
CPU time 0.93 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 197024 kb
Host smart-c301fda7-1605-4b14-9986-19be84902aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762822376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.762822376
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1758512963
Short name T118
Test name
Test status
Simulation time 53873238 ps
CPU time 1.16 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 198600 kb
Host smart-60333290-c026-4c0f-9e2d-8940cd324287
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758512963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1758512963
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.4187295204
Short name T4
Test name
Test status
Simulation time 301202579 ps
CPU time 4.02 seconds
Started Aug 01 05:20:04 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 198268 kb
Host smart-71db1216-b3f0-49df-87f3-66274b3a8778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187295204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.4187295204
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.24457290
Short name T81
Test name
Test status
Simulation time 264119700 ps
CPU time 1.33 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 198500 kb
Host smart-06c9a291-eec4-487a-8c6f-9e82139f27df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24457290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.24457290
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1509922635
Short name T411
Test name
Test status
Simulation time 48473759 ps
CPU time 1.07 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 195956 kb
Host smart-1bf8751e-ec95-4851-87c1-47304c1dc4a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509922635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1509922635
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1143068499
Short name T152
Test name
Test status
Simulation time 12421846941 ps
CPU time 37.18 seconds
Started Aug 01 05:20:09 PM PDT 24
Finished Aug 01 05:20:46 PM PDT 24
Peak memory 198628 kb
Host smart-bef32174-5b9f-45b2-9424-6c0a376ecc61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143068499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1143068499
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1580107531
Short name T554
Test name
Test status
Simulation time 379309024013 ps
CPU time 2290.69 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:58:18 PM PDT 24
Peak memory 198816 kb
Host smart-900f6b40-c14c-45f2-8e2a-0dc3ab09e696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1580107531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1580107531
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3730270101
Short name T276
Test name
Test status
Simulation time 13351394 ps
CPU time 0.58 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 194400 kb
Host smart-fd6993af-6417-45e3-8f9e-878e289d9214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730270101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3730270101
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.312900820
Short name T131
Test name
Test status
Simulation time 36510794 ps
CPU time 0.76 seconds
Started Aug 01 05:20:04 PM PDT 24
Finished Aug 01 05:20:05 PM PDT 24
Peak memory 195516 kb
Host smart-849ab838-74f3-478c-83a4-5c3511039d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312900820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.312900820
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2014533458
Short name T599
Test name
Test status
Simulation time 708496458 ps
CPU time 23.75 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:29 PM PDT 24
Peak memory 195956 kb
Host smart-a949d716-12f3-4348-b14d-33df2c69c6ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014533458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2014533458
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3464675805
Short name T561
Test name
Test status
Simulation time 85204014 ps
CPU time 0.67 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 195744 kb
Host smart-0e2cd9a4-c98f-4c05-b2f4-93e0ec60762b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464675805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3464675805
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3486827934
Short name T116
Test name
Test status
Simulation time 257358052 ps
CPU time 1.33 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 196616 kb
Host smart-4469ee76-6c36-41ab-8f86-4f4919dc2c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486827934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3486827934
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1634343535
Short name T464
Test name
Test status
Simulation time 109168735 ps
CPU time 1.36 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196936 kb
Host smart-54fc63f3-8388-4669-9da1-83480e589a28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634343535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1634343535
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1897191035
Short name T413
Test name
Test status
Simulation time 44630388 ps
CPU time 1.19 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196316 kb
Host smart-f25d615d-4a86-401d-af3c-ba7ad48de381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897191035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1897191035
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1907282748
Short name T312
Test name
Test status
Simulation time 46334898 ps
CPU time 1.14 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 196596 kb
Host smart-a63e1e5b-74ac-4ef0-8ffc-ad669a2282a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907282748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1907282748
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3887118665
Short name T475
Test name
Test status
Simulation time 46925745 ps
CPU time 1.13 seconds
Started Aug 01 05:20:09 PM PDT 24
Finished Aug 01 05:20:11 PM PDT 24
Peak memory 196608 kb
Host smart-1dc71768-f0bc-4796-a5e6-103c5569cdaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887118665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3887118665
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1214454069
Short name T6
Test name
Test status
Simulation time 2220812067 ps
CPU time 3.91 seconds
Started Aug 01 05:20:04 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 198432 kb
Host smart-469d0cce-d495-4e0d-955e-a49da2677101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214454069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1214454069
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.145284364
Short name T673
Test name
Test status
Simulation time 190919700 ps
CPU time 1.1 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196000 kb
Host smart-99ca17fd-98eb-42ef-af8f-efbd6984c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145284364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.145284364
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1908683159
Short name T589
Test name
Test status
Simulation time 108621539 ps
CPU time 0.97 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:10 PM PDT 24
Peak memory 196708 kb
Host smart-0bd90132-ce46-43a5-9ed2-c737a10ad2e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908683159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1908683159
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2846820421
Short name T489
Test name
Test status
Simulation time 15399957294 ps
CPU time 82.76 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:21:31 PM PDT 24
Peak memory 198640 kb
Host smart-e5d6a020-91ee-4b25-a798-73a9ccb32434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846820421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2846820421
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1055973050
Short name T32
Test name
Test status
Simulation time 95956091999 ps
CPU time 560.56 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:29:28 PM PDT 24
Peak memory 198780 kb
Host smart-f57ac710-9d5e-4dda-8aea-b5ac59bd8d29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1055973050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1055973050
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2892902341
Short name T471
Test name
Test status
Simulation time 159210759 ps
CPU time 0.56 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 194332 kb
Host smart-875b59e2-dc08-4ad1-96c9-283710a02a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892902341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2892902341
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2535339988
Short name T302
Test name
Test status
Simulation time 19512824 ps
CPU time 0.69 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 195552 kb
Host smart-2a35237a-0e37-428e-ba0a-027e6b3ebd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535339988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2535339988
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.277678747
Short name T301
Test name
Test status
Simulation time 620514523 ps
CPU time 14.25 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 197600 kb
Host smart-1b93e695-b35d-475b-a62f-450010cccea3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277678747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.277678747
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.332353314
Short name T365
Test name
Test status
Simulation time 65356939 ps
CPU time 0.86 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 197124 kb
Host smart-2f8c368b-e07f-4264-a07f-fc8ea5e17998
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332353314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.332353314
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1511108638
Short name T478
Test name
Test status
Simulation time 112580751 ps
CPU time 0.8 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 196876 kb
Host smart-7df7429a-d7e0-4aa9-8bdd-9eab8e889e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511108638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1511108638
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1763532092
Short name T243
Test name
Test status
Simulation time 139699329 ps
CPU time 1.56 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:10 PM PDT 24
Peak memory 197168 kb
Host smart-f9e224c4-bdd7-4ece-8e18-ca371176004e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763532092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1763532092
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1867110440
Short name T694
Test name
Test status
Simulation time 309069030 ps
CPU time 1.66 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 196396 kb
Host smart-315f3e6d-de48-4bff-9f42-d58a935fd3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867110440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1867110440
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.223650251
Short name T52
Test name
Test status
Simulation time 162796998 ps
CPU time 0.8 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 196956 kb
Host smart-9aa7795e-5326-4762-adce-9c425cafbdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223650251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.223650251
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1209589822
Short name T512
Test name
Test status
Simulation time 47279019 ps
CPU time 0.8 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:05 PM PDT 24
Peak memory 195876 kb
Host smart-f1dcd26d-c0ec-4c76-b0b9-97f9c9f8777f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209589822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1209589822
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.251323377
Short name T20
Test name
Test status
Simulation time 678987825 ps
CPU time 4.06 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:10 PM PDT 24
Peak memory 198436 kb
Host smart-196a8517-0b01-4a3b-82e3-bde339bdd9a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251323377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.251323377
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2061307725
Short name T351
Test name
Test status
Simulation time 138150626 ps
CPU time 1.5 seconds
Started Aug 01 05:20:09 PM PDT 24
Finished Aug 01 05:20:11 PM PDT 24
Peak memory 198476 kb
Host smart-d523f359-9a1d-4fea-9896-da5bad23a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061307725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2061307725
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1008597860
Short name T581
Test name
Test status
Simulation time 42899739 ps
CPU time 1.2 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:10 PM PDT 24
Peak memory 197396 kb
Host smart-c7b79720-56cf-480a-aafb-f3407adc3a03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008597860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1008597860
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2135965033
Short name T395
Test name
Test status
Simulation time 18918773276 ps
CPU time 64.88 seconds
Started Aug 01 05:20:10 PM PDT 24
Finished Aug 01 05:21:15 PM PDT 24
Peak memory 198676 kb
Host smart-e1097b81-17da-4125-a719-3fd2234f342f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135965033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2135965033
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.895890483
Short name T60
Test name
Test status
Simulation time 57192013839 ps
CPU time 888.56 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:34:55 PM PDT 24
Peak memory 198836 kb
Host smart-3f12d68d-6ee3-4e54-b72e-120c0af5316f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=895890483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.895890483
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2207420875
Short name T209
Test name
Test status
Simulation time 15900812 ps
CPU time 0.59 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 194296 kb
Host smart-61aa975b-2ba8-4c0e-bcca-0ac2b809e336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207420875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2207420875
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3020135565
Short name T549
Test name
Test status
Simulation time 141473682 ps
CPU time 0.87 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196728 kb
Host smart-383f7b5d-181e-4a25-af03-01c79c77f3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020135565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3020135565
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.682208823
Short name T143
Test name
Test status
Simulation time 1263878126 ps
CPU time 22.94 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:30 PM PDT 24
Peak memory 195996 kb
Host smart-9e1ed7ff-9ec3-4a69-a0a0-62941b23a25a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682208823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.682208823
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4137045590
Short name T493
Test name
Test status
Simulation time 74135459 ps
CPU time 0.95 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 198500 kb
Host smart-3f18ec67-b277-4015-bebf-a679ba198f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137045590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4137045590
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1277500682
Short name T567
Test name
Test status
Simulation time 425316935 ps
CPU time 1.03 seconds
Started Aug 01 05:20:06 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 197200 kb
Host smart-946229d6-e8ff-4003-94b7-5815b887ce07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277500682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1277500682
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4070541193
Short name T701
Test name
Test status
Simulation time 331216041 ps
CPU time 2.68 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 198532 kb
Host smart-5e24f082-06b0-4639-86a8-506f9f21ce94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070541193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4070541193
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.637030857
Short name T562
Test name
Test status
Simulation time 63442803 ps
CPU time 1.17 seconds
Started Aug 01 05:20:05 PM PDT 24
Finished Aug 01 05:20:06 PM PDT 24
Peak memory 198528 kb
Host smart-54f4f0c9-9930-45b8-9a83-1bd1fc4b43b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637030857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.637030857
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3280193966
Short name T454
Test name
Test status
Simulation time 68443704 ps
CPU time 0.68 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:07 PM PDT 24
Peak memory 194756 kb
Host smart-84d34fe2-b723-41e5-aea8-4d54d8714c9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280193966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3280193966
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.756275871
Short name T380
Test name
Test status
Simulation time 129174635 ps
CPU time 2.02 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:09 PM PDT 24
Peak memory 198476 kb
Host smart-1a793499-6dd9-41ea-a73a-4015bb75dcae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756275871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.756275871
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.74910696
Short name T274
Test name
Test status
Simulation time 84391941 ps
CPU time 1.55 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 196016 kb
Host smart-9da309e2-7fcb-407f-8e3d-90a6c6e46188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74910696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.74910696
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.448808542
Short name T212
Test name
Test status
Simulation time 45740361 ps
CPU time 1.25 seconds
Started Aug 01 05:20:07 PM PDT 24
Finished Aug 01 05:20:08 PM PDT 24
Peak memory 197220 kb
Host smart-537aaa5d-e9e3-4472-9cf4-5cfb0a916120
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448808542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.448808542
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2066803492
Short name T390
Test name
Test status
Simulation time 1755059958 ps
CPU time 42.05 seconds
Started Aug 01 05:20:08 PM PDT 24
Finished Aug 01 05:20:50 PM PDT 24
Peak memory 198184 kb
Host smart-da68a932-8047-4d6c-8b4d-79bb9bbd1e3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066803492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2066803492
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.164664044
Short name T64
Test name
Test status
Simulation time 138958008541 ps
CPU time 1464.91 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:44:42 PM PDT 24
Peak memory 198864 kb
Host smart-26c66912-4309-444f-83bb-f09d7c53d7ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=164664044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.164664044
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4069347848
Short name T201
Test name
Test status
Simulation time 34102897 ps
CPU time 0.58 seconds
Started Aug 01 05:20:21 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 195196 kb
Host smart-ce18afc9-cf81-43a6-81cc-bfc5d50601c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069347848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4069347848
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1054140988
Short name T550
Test name
Test status
Simulation time 102920707 ps
CPU time 0.69 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 194624 kb
Host smart-e2b6e33a-a69b-4d0c-bf57-c0644238b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054140988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1054140988
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3447503329
Short name T334
Test name
Test status
Simulation time 713935514 ps
CPU time 20.11 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:36 PM PDT 24
Peak memory 197544 kb
Host smart-1199f1f6-7f5e-4cac-a35e-9b165408d40b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447503329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3447503329
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3841394924
Short name T124
Test name
Test status
Simulation time 140898792 ps
CPU time 0.97 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:21 PM PDT 24
Peak memory 196892 kb
Host smart-ad39f830-a126-46c0-8b1d-a233044ad51d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841394924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3841394924
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.57701828
Short name T285
Test name
Test status
Simulation time 357900808 ps
CPU time 1.48 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:19 PM PDT 24
Peak memory 198572 kb
Host smart-facafe83-cc1a-4e16-9f14-62bf492140f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57701828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.57701828
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4144972537
Short name T278
Test name
Test status
Simulation time 97335264 ps
CPU time 1.17 seconds
Started Aug 01 05:20:18 PM PDT 24
Finished Aug 01 05:20:20 PM PDT 24
Peak memory 197300 kb
Host smart-cade3506-070b-4a97-90ef-6ea6cbd59d70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144972537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4144972537
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1655826805
Short name T255
Test name
Test status
Simulation time 147446928 ps
CPU time 2.8 seconds
Started Aug 01 05:20:15 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 198504 kb
Host smart-b66e442e-ac87-409d-b462-30e89a153719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655826805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1655826805
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2168346779
Short name T606
Test name
Test status
Simulation time 222616633 ps
CPU time 1.16 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:21 PM PDT 24
Peak memory 197536 kb
Host smart-0e2b7d7b-892a-4fef-93bf-2c150cb02349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168346779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2168346779
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1185478728
Short name T290
Test name
Test status
Simulation time 49890788 ps
CPU time 1.04 seconds
Started Aug 01 05:20:16 PM PDT 24
Finished Aug 01 05:20:17 PM PDT 24
Peak memory 196264 kb
Host smart-f5243e85-bc05-4d38-b908-4ac218fd0c74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185478728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1185478728
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2387144762
Short name T7
Test name
Test status
Simulation time 159497043 ps
CPU time 2.06 seconds
Started Aug 01 05:20:19 PM PDT 24
Finished Aug 01 05:20:21 PM PDT 24
Peak memory 198444 kb
Host smart-63dca2eb-7efc-46b8-a109-995dcd978ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387144762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2387144762
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3286671236
Short name T668
Test name
Test status
Simulation time 125643251 ps
CPU time 0.86 seconds
Started Aug 01 05:20:17 PM PDT 24
Finished Aug 01 05:20:18 PM PDT 24
Peak memory 196612 kb
Host smart-aab32434-df3d-4ae5-81fa-6f0894ebc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286671236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3286671236
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2370013660
Short name T603
Test name
Test status
Simulation time 205771393 ps
CPU time 1.28 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:20:22 PM PDT 24
Peak memory 197372 kb
Host smart-10a1d229-d068-467a-babb-1e4205faca9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370013660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2370013660
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.904186185
Short name T569
Test name
Test status
Simulation time 15453102815 ps
CPU time 208.96 seconds
Started Aug 01 05:20:20 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 198604 kb
Host smart-82be0821-715d-4c75-bc36-65b62b782638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904186185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.904186185
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1978395499
Short name T928
Test name
Test status
Simulation time 213908047 ps
CPU time 1.22 seconds
Started Aug 01 05:19:22 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 196520 kb
Host smart-de40aef1-2413-4b15-b3f8-571ecf461bb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1978395499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1978395499
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.301350191
Short name T845
Test name
Test status
Simulation time 120425334 ps
CPU time 0.96 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 196700 kb
Host smart-22021fe0-c3c5-4a9e-b898-74becab2a101
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301350191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.301350191
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.473274213
Short name T861
Test name
Test status
Simulation time 39269998 ps
CPU time 0.89 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 196092 kb
Host smart-6b60d5af-adef-42a2-bb41-649c6ba1f903
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=473274213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.473274213
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1591618913
Short name T874
Test name
Test status
Simulation time 166028339 ps
CPU time 1.02 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 196736 kb
Host smart-9ec6701e-66eb-4b5e-b4c7-716cb20473a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591618913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1591618913
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1972058195
Short name T906
Test name
Test status
Simulation time 258793631 ps
CPU time 1.36 seconds
Started Aug 01 05:19:23 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 191648 kb
Host smart-2bab07b2-6bec-454b-b21f-d8f53e58ff7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1972058195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1972058195
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1412501493
Short name T851
Test name
Test status
Simulation time 36487756 ps
CPU time 0.81 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:19 PM PDT 24
Peak memory 196056 kb
Host smart-2fa31433-5165-478b-b046-7936656f0615
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412501493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1412501493
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.348870730
Short name T853
Test name
Test status
Simulation time 312314317 ps
CPU time 1.61 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:20 PM PDT 24
Peak memory 196588 kb
Host smart-a4655926-da60-4b4a-a8ce-6273b7580d4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=348870730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.348870730
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1713507481
Short name T908
Test name
Test status
Simulation time 92373129 ps
CPU time 1.25 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 196764 kb
Host smart-10197eed-0e3d-4ff3-8c69-ff3aa6515c87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713507481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1713507481
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.225648099
Short name T903
Test name
Test status
Simulation time 109969939 ps
CPU time 1.01 seconds
Started Aug 01 05:19:22 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 195804 kb
Host smart-bee4577c-a37e-4149-ae5c-f8449634b8e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=225648099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.225648099
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4243742701
Short name T901
Test name
Test status
Simulation time 35952693 ps
CPU time 1.07 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 195728 kb
Host smart-fe356a71-b746-4d28-8b8f-b67876718ec8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243742701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4243742701
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.114212151
Short name T854
Test name
Test status
Simulation time 54600108 ps
CPU time 1.11 seconds
Started Aug 01 05:19:24 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 196548 kb
Host smart-1cdcbbcb-f8e9-413b-8e9e-d11f6f52fe31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=114212151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.114212151
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.267066457
Short name T890
Test name
Test status
Simulation time 340340849 ps
CPU time 1.44 seconds
Started Aug 01 05:19:24 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 198004 kb
Host smart-d0ea5c84-32da-4323-8732-37423e5a0dce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267066457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.267066457
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3589277244
Short name T935
Test name
Test status
Simulation time 70718850 ps
CPU time 1.23 seconds
Started Aug 01 05:19:18 PM PDT 24
Finished Aug 01 05:19:19 PM PDT 24
Peak memory 197936 kb
Host smart-45438967-7728-4a16-8120-9d41bf1ee3d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3589277244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3589277244
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3541711297
Short name T923
Test name
Test status
Simulation time 58704897 ps
CPU time 1.17 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 197936 kb
Host smart-58fdda59-b6e2-41c5-85ca-68d4851b314f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541711297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3541711297
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.743585164
Short name T905
Test name
Test status
Simulation time 329901412 ps
CPU time 0.94 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 195592 kb
Host smart-b7630894-0304-4ece-b52d-2240b416f1c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=743585164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.743585164
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.41253937
Short name T883
Test name
Test status
Simulation time 79712987 ps
CPU time 1.21 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196588 kb
Host smart-413b7e96-a274-4205-9442-dd4cafcd4104
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.41253937
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1516259535
Short name T884
Test name
Test status
Simulation time 41434564 ps
CPU time 0.96 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196420 kb
Host smart-06b03809-9c34-4697-9fdd-c6807bed16b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1516259535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1516259535
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3522914678
Short name T888
Test name
Test status
Simulation time 42843409 ps
CPU time 0.85 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196384 kb
Host smart-933e80ff-3de0-40aa-a348-5ef884a9d49f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522914678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3522914678
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3620904270
Short name T885
Test name
Test status
Simulation time 233500529 ps
CPU time 0.96 seconds
Started Aug 01 05:19:29 PM PDT 24
Finished Aug 01 05:19:30 PM PDT 24
Peak memory 196620 kb
Host smart-0d788fa9-c08b-4413-a708-e5c530723aa8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3620904270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3620904270
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.980235144
Short name T912
Test name
Test status
Simulation time 70648149 ps
CPU time 1.21 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196524 kb
Host smart-47127f32-5d8a-43f0-8175-46444b880a00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980235144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.980235144
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1007398597
Short name T918
Test name
Test status
Simulation time 305302538 ps
CPU time 1.39 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196876 kb
Host smart-4796da09-517d-4e4c-8039-a182bbad4dcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1007398597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1007398597
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.870530595
Short name T914
Test name
Test status
Simulation time 158085296 ps
CPU time 1.24 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196884 kb
Host smart-7690530b-9806-4c5c-ad33-9250e45a208a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870530595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.870530595
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3965651711
Short name T847
Test name
Test status
Simulation time 37233991 ps
CPU time 0.9 seconds
Started Aug 01 05:19:39 PM PDT 24
Finished Aug 01 05:19:40 PM PDT 24
Peak memory 195424 kb
Host smart-b4b096fa-4a79-4dd1-b56a-e7a15fb01631
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3965651711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3965651711
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1265145338
Short name T892
Test name
Test status
Simulation time 84476778 ps
CPU time 0.91 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 195252 kb
Host smart-d59806e5-f679-4338-98bb-3c66053648d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265145338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1265145338
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2297301942
Short name T876
Test name
Test status
Simulation time 99003474 ps
CPU time 0.86 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 195336 kb
Host smart-5ee1e477-2e4b-4a63-8a5f-e6a6d042e202
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2297301942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2297301942
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3738640477
Short name T910
Test name
Test status
Simulation time 51167274 ps
CPU time 1.04 seconds
Started Aug 01 05:19:22 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 197968 kb
Host smart-43a26e88-db40-4fd8-bb2e-7dc110334964
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738640477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3738640477
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4213142739
Short name T855
Test name
Test status
Simulation time 34279599 ps
CPU time 0.97 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196364 kb
Host smart-46621ce6-03e1-41a5-a9ac-060d308e999d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4213142739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4213142739
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422142777
Short name T850
Test name
Test status
Simulation time 438478223 ps
CPU time 1.44 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196900 kb
Host smart-c928ae87-1f96-4fe1-b103-ceaa0e1c3d9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422142777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2422142777
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2864962136
Short name T880
Test name
Test status
Simulation time 138274517 ps
CPU time 0.83 seconds
Started Aug 01 05:19:29 PM PDT 24
Finished Aug 01 05:19:31 PM PDT 24
Peak memory 196204 kb
Host smart-56e303b7-4d7a-4fad-b320-e13dd7632ef7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2864962136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2864962136
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3449952948
Short name T877
Test name
Test status
Simulation time 68744661 ps
CPU time 1.15 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196712 kb
Host smart-479c2a0b-5ef2-4616-8d69-969ff8a8d5f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449952948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3449952948
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3826331503
Short name T872
Test name
Test status
Simulation time 133132141 ps
CPU time 1.01 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196388 kb
Host smart-b36396a2-65fe-47ed-9501-0a986e063dfc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3826331503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3826331503
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2273302722
Short name T838
Test name
Test status
Simulation time 327399193 ps
CPU time 1.21 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196500 kb
Host smart-f096641a-bf6b-4324-9457-ad4535717e20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273302722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2273302722
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2402049880
Short name T916
Test name
Test status
Simulation time 33800188 ps
CPU time 1 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 195704 kb
Host smart-f25b648c-d345-4de8-8ca5-856f7f9aea7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2402049880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2402049880
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099893336
Short name T896
Test name
Test status
Simulation time 43532961 ps
CPU time 0.72 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:31 PM PDT 24
Peak memory 195324 kb
Host smart-5471fee1-a946-48c3-b0bb-0e8b108a7e3c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099893336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2099893336
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3077683378
Short name T846
Test name
Test status
Simulation time 194645259 ps
CPU time 1.42 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196908 kb
Host smart-fdc12bda-688f-42aa-856d-8a445918fc10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3077683378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3077683378
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3996725116
Short name T867
Test name
Test status
Simulation time 165091043 ps
CPU time 1.41 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 195536 kb
Host smart-b6066d66-23b1-4ee9-b7d1-0b43980cf79e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996725116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3996725116
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1827463156
Short name T919
Test name
Test status
Simulation time 174315052 ps
CPU time 0.94 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196412 kb
Host smart-2b67c709-3bd5-4487-ba32-1338e4b25aed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1827463156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1827463156
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.202087768
Short name T873
Test name
Test status
Simulation time 343416846 ps
CPU time 1.15 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196656 kb
Host smart-d89317b8-bb06-4751-904d-317d976b1a89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202087768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.202087768
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1664830696
Short name T858
Test name
Test status
Simulation time 29127675 ps
CPU time 0.78 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 195204 kb
Host smart-26f6aa5b-114f-4532-935a-df9860f7c272
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1664830696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1664830696
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4029375110
Short name T878
Test name
Test status
Simulation time 65169355 ps
CPU time 0.9 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196200 kb
Host smart-0f2428b2-ae18-47f0-a648-ef11b19d8094
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029375110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4029375110
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2187035253
Short name T899
Test name
Test status
Simulation time 38619606 ps
CPU time 1.15 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196488 kb
Host smart-bc7247f5-7a58-4c51-a1e0-b854671887cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2187035253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2187035253
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325770641
Short name T921
Test name
Test status
Simulation time 203477946 ps
CPU time 1.52 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196468 kb
Host smart-4f756bc3-99fc-4b06-8dbc-3798001b8f33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325770641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.325770641
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4070238416
Short name T848
Test name
Test status
Simulation time 213066937 ps
CPU time 1.37 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:34 PM PDT 24
Peak memory 196604 kb
Host smart-7c4ddd94-d6b1-4ee9-8509-82dd3ec5acc3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4070238416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4070238416
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1772553327
Short name T902
Test name
Test status
Simulation time 74243290 ps
CPU time 1.33 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 196548 kb
Host smart-790f0fb1-3fa7-45ee-9e25-e51934fa8ca8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772553327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1772553327
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2218897226
Short name T868
Test name
Test status
Simulation time 285241342 ps
CPU time 1.27 seconds
Started Aug 01 05:19:31 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196524 kb
Host smart-a72bb753-1caf-4efe-98c3-eda4e159d05f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2218897226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2218897226
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1575119942
Short name T856
Test name
Test status
Simulation time 40375970 ps
CPU time 0.86 seconds
Started Aug 01 05:19:39 PM PDT 24
Finished Aug 01 05:19:40 PM PDT 24
Peak memory 195468 kb
Host smart-f0279d84-afc3-4708-b114-a8a99e1fd0fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575119942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1575119942
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2217932666
Short name T920
Test name
Test status
Simulation time 190163196 ps
CPU time 1.45 seconds
Started Aug 01 05:19:24 PM PDT 24
Finished Aug 01 05:19:25 PM PDT 24
Peak memory 197428 kb
Host smart-7a121a81-15e9-45eb-80dc-609d216d46e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2217932666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2217932666
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3374197048
Short name T904
Test name
Test status
Simulation time 384661035 ps
CPU time 1.35 seconds
Started Aug 01 05:19:23 PM PDT 24
Finished Aug 01 05:19:24 PM PDT 24
Peak memory 196728 kb
Host smart-25824bfc-00a9-49e7-b0d6-27d7f7295b75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374197048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3374197048
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3786987727
Short name T917
Test name
Test status
Simulation time 43869631 ps
CPU time 1.21 seconds
Started Aug 01 05:19:33 PM PDT 24
Finished Aug 01 05:19:35 PM PDT 24
Peak memory 195568 kb
Host smart-90478119-d70e-4b80-90e7-e50a58b9a638
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3786987727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3786987727
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1068502809
Short name T849
Test name
Test status
Simulation time 29600270 ps
CPU time 0.87 seconds
Started Aug 01 05:19:39 PM PDT 24
Finished Aug 01 05:19:40 PM PDT 24
Peak memory 195252 kb
Host smart-f1bc5bc6-3baa-475b-b49b-112161cb954c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068502809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1068502809
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4061305844
Short name T894
Test name
Test status
Simulation time 23693107 ps
CPU time 0.79 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 195300 kb
Host smart-66f28121-e4e3-44ef-80e9-accf637dc88a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4061305844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4061305844
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3584207711
Short name T897
Test name
Test status
Simulation time 59925013 ps
CPU time 1.13 seconds
Started Aug 01 05:19:30 PM PDT 24
Finished Aug 01 05:19:32 PM PDT 24
Peak memory 196520 kb
Host smart-9615e81e-df64-485f-a403-d1439b7afa45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584207711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3584207711
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2178877083
Short name T843
Test name
Test status
Simulation time 175882090 ps
CPU time 0.94 seconds
Started Aug 01 05:19:32 PM PDT 24
Finished Aug 01 05:19:33 PM PDT 24
Peak memory 197760 kb
Host smart-c2d66bdb-4e6e-4495-9c71-499158be7945
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2178877083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2178877083
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330857261
Short name T893
Test name
Test status
Simulation time 204539917 ps
CPU time 0.85 seconds
Started Aug 01 05:19:38 PM PDT 24
Finished Aug 01 05:19:39 PM PDT 24
Peak memory 195392 kb
Host smart-8307d8f8-28a2-4348-96e1-1d251d680399
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330857261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1330857261
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1568736899
Short name T889
Test name
Test status
Simulation time 172257829 ps
CPU time 1.01 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196244 kb
Host smart-616177ab-13b9-4457-9c3f-a79d599d5722
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1568736899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1568736899
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2451571384
Short name T864
Test name
Test status
Simulation time 140520841 ps
CPU time 0.85 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 195404 kb
Host smart-1d625141-5266-4b10-a516-978caf38b2ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451571384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2451571384
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1788009081
Short name T933
Test name
Test status
Simulation time 245543780 ps
CPU time 0.68 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 194284 kb
Host smart-4d08467a-a1bc-4901-a2a4-025dabd96a6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1788009081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1788009081
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1445961526
Short name T857
Test name
Test status
Simulation time 66919074 ps
CPU time 1 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 196840 kb
Host smart-b8b2b07c-e78c-4a56-bd9a-0a892512704b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445961526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1445961526
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3425721681
Short name T870
Test name
Test status
Simulation time 135986147 ps
CPU time 1.47 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196812 kb
Host smart-ac8c4eab-5706-4618-9e08-f6ac6fa587f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3425721681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3425721681
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1256644275
Short name T926
Test name
Test status
Simulation time 37199942 ps
CPU time 1.19 seconds
Started Aug 01 05:19:46 PM PDT 24
Finished Aug 01 05:19:47 PM PDT 24
Peak memory 196852 kb
Host smart-0097bc7f-28fa-4672-8321-e667e119a623
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256644275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1256644275
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1065363860
Short name T900
Test name
Test status
Simulation time 49812329 ps
CPU time 1 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196388 kb
Host smart-48c9e651-d74b-452d-89a6-c015abb8f2ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1065363860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1065363860
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873547117
Short name T930
Test name
Test status
Simulation time 382513293 ps
CPU time 0.89 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 196408 kb
Host smart-a2c74adb-3add-4a27-bb18-92773198ccdb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873547117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1873547117
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2013738625
Short name T929
Test name
Test status
Simulation time 362567949 ps
CPU time 1.22 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 195484 kb
Host smart-2eb43c9b-3c3f-4df9-bab9-6a6f094646aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2013738625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2013738625
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3701471571
Short name T932
Test name
Test status
Simulation time 252309798 ps
CPU time 1.27 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 197976 kb
Host smart-42e8d1ca-f161-49ed-b272-1d372b487302
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701471571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3701471571
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4109097785
Short name T882
Test name
Test status
Simulation time 117461197 ps
CPU time 1.24 seconds
Started Aug 01 05:19:46 PM PDT 24
Finished Aug 01 05:19:47 PM PDT 24
Peak memory 196648 kb
Host smart-55c24982-1b4d-450b-90cd-3684e1f74db6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4109097785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4109097785
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2540810687
Short name T895
Test name
Test status
Simulation time 167113539 ps
CPU time 1 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196468 kb
Host smart-444d7843-98ef-46b4-a525-dcac498c7101
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540810687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2540810687
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3442039017
Short name T871
Test name
Test status
Simulation time 199620178 ps
CPU time 1.35 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 196644 kb
Host smart-08746d27-4eb8-429b-b5d7-e4de079707e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3442039017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3442039017
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805729061
Short name T913
Test name
Test status
Simulation time 183088331 ps
CPU time 1.42 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 197348 kb
Host smart-6f6682cd-10fc-4399-a428-fd4306d74613
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805729061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3805729061
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.847020693
Short name T862
Test name
Test status
Simulation time 222752340 ps
CPU time 1.21 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 195808 kb
Host smart-e6bae271-8c55-44b8-981f-ded138b96831
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=847020693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.847020693
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454208469
Short name T922
Test name
Test status
Simulation time 78755529 ps
CPU time 1.22 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 196516 kb
Host smart-2602a627-b869-48f8-aefc-7640390742fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454208469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.454208469
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3567597443
Short name T863
Test name
Test status
Simulation time 49875022 ps
CPU time 1.39 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 197984 kb
Host smart-26867b02-6e56-44dc-858e-7fa8fcacc990
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3567597443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3567597443
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150111262
Short name T865
Test name
Test status
Simulation time 116152128 ps
CPU time 1.22 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 195872 kb
Host smart-64bbb9d5-2270-4dcb-94ea-136935f614ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150111262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.150111262
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3528930725
Short name T891
Test name
Test status
Simulation time 33898262 ps
CPU time 1.11 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:47 PM PDT 24
Peak memory 197652 kb
Host smart-635f9d2b-1d38-46f6-a6a0-5aea13223871
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3528930725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3528930725
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849369215
Short name T879
Test name
Test status
Simulation time 33568374 ps
CPU time 0.94 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 196568 kb
Host smart-f01d3830-29ab-421a-9f28-4f75c99b7615
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849369215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2849369215
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.599917548
Short name T909
Test name
Test status
Simulation time 194307564 ps
CPU time 1.11 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 195824 kb
Host smart-c412b900-b782-453c-9fa4-044ff89ff5a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=599917548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.599917548
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247660597
Short name T852
Test name
Test status
Simulation time 49302688 ps
CPU time 1.2 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 196868 kb
Host smart-ebf33580-6c90-4ef8-8240-aa599a1d1450
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247660597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2247660597
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2755835924
Short name T859
Test name
Test status
Simulation time 161132341 ps
CPU time 1.08 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 195836 kb
Host smart-a7aa9062-a0d9-4244-892b-d320372313cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2755835924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2755835924
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1979784600
Short name T898
Test name
Test status
Simulation time 36578739 ps
CPU time 1.18 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 196456 kb
Host smart-295e33bb-dfa6-419e-ab0b-28d8db773856
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979784600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1979784600
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.513738611
Short name T925
Test name
Test status
Simulation time 184932173 ps
CPU time 1.35 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 197936 kb
Host smart-eac22337-d88c-4973-84e4-f4361ffb136c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=513738611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.513738611
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101024086
Short name T936
Test name
Test status
Simulation time 27760983 ps
CPU time 0.84 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 196108 kb
Host smart-f028f3a1-4618-4a80-8533-6a8465d7c3d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101024086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1101024086
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.687831489
Short name T837
Test name
Test status
Simulation time 54059368 ps
CPU time 1.18 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 197520 kb
Host smart-32a51249-35eb-478d-ad2e-b6c92ea486c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=687831489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.687831489
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2848237539
Short name T860
Test name
Test status
Simulation time 54246452 ps
CPU time 1.06 seconds
Started Aug 01 05:19:47 PM PDT 24
Finished Aug 01 05:19:48 PM PDT 24
Peak memory 196592 kb
Host smart-3791976c-63fa-4750-975b-b87f97cc042e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848237539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2848237539
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3923422432
Short name T839
Test name
Test status
Simulation time 241586357 ps
CPU time 1.04 seconds
Started Aug 01 05:19:43 PM PDT 24
Finished Aug 01 05:19:44 PM PDT 24
Peak memory 196500 kb
Host smart-f2346e25-0403-4c0c-a120-30cf56ac7720
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3923422432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3923422432
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513213598
Short name T840
Test name
Test status
Simulation time 222556271 ps
CPU time 1.25 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 196948 kb
Host smart-c60e0e5f-e7f6-4cb3-963a-bc23c63623fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513213598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.513213598
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1078510419
Short name T911
Test name
Test status
Simulation time 150826226 ps
CPU time 1.11 seconds
Started Aug 01 05:19:44 PM PDT 24
Finished Aug 01 05:19:45 PM PDT 24
Peak memory 195776 kb
Host smart-c1aeb220-7184-4847-b675-e886a5f266ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1078510419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1078510419
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.275116266
Short name T866
Test name
Test status
Simulation time 74466702 ps
CPU time 1.21 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 196508 kb
Host smart-d101dd30-b58f-4498-a63c-db05c10cd397
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275116266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.275116266
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3916880526
Short name T924
Test name
Test status
Simulation time 353635154 ps
CPU time 1.26 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:42 PM PDT 24
Peak memory 196100 kb
Host smart-dd00a7e2-88b3-4161-8ba1-3652b7a47e03
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3916880526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3916880526
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2205390669
Short name T907
Test name
Test status
Simulation time 19820322 ps
CPU time 0.78 seconds
Started Aug 01 05:19:45 PM PDT 24
Finished Aug 01 05:19:46 PM PDT 24
Peak memory 195276 kb
Host smart-a20b31b0-21f8-40b4-9203-f6d364f5b1fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205390669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2205390669
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.363861906
Short name T844
Test name
Test status
Simulation time 54047152 ps
CPU time 1.01 seconds
Started Aug 01 05:19:42 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 197880 kb
Host smart-5ca3e7a3-ff14-42f3-a20e-3d0026563073
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=363861906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.363861906
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921047515
Short name T915
Test name
Test status
Simulation time 60005330 ps
CPU time 1.5 seconds
Started Aug 01 05:19:41 PM PDT 24
Finished Aug 01 05:19:43 PM PDT 24
Peak memory 197968 kb
Host smart-d8617e02-e9e8-4774-9d84-603c5f1e90a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921047515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2921047515
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2959364009
Short name T875
Test name
Test status
Simulation time 44686516 ps
CPU time 1.1 seconds
Started Aug 01 05:19:25 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 196792 kb
Host smart-a104e24a-6851-489f-be91-504592eee057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2959364009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2959364009
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3309676276
Short name T886
Test name
Test status
Simulation time 76067498 ps
CPU time 1.16 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 196720 kb
Host smart-bce523f1-b665-4c39-9b98-e07a7a8104de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309676276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3309676276
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1203355750
Short name T934
Test name
Test status
Simulation time 163816515 ps
CPU time 0.9 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:22 PM PDT 24
Peak memory 196560 kb
Host smart-2e118cee-4392-4ebe-b42b-39d3003fa47b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1203355750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1203355750
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2959585279
Short name T881
Test name
Test status
Simulation time 115416673 ps
CPU time 0.89 seconds
Started Aug 01 05:19:21 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 195916 kb
Host smart-722e2dac-28cc-4443-8eee-00c155c03cd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959585279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2959585279
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1299824269
Short name T887
Test name
Test status
Simulation time 58038634 ps
CPU time 1.38 seconds
Started Aug 01 05:19:25 PM PDT 24
Finished Aug 01 05:19:26 PM PDT 24
Peak memory 196612 kb
Host smart-840a14cb-2894-4181-b8c6-b0903de2b291
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1299824269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1299824269
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.265380616
Short name T869
Test name
Test status
Simulation time 57207494 ps
CPU time 1.06 seconds
Started Aug 01 05:19:20 PM PDT 24
Finished Aug 01 05:19:21 PM PDT 24
Peak memory 196188 kb
Host smart-d4a1d302-cd8a-4585-8019-93bea361932f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265380616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.265380616
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.175473420
Short name T931
Test name
Test status
Simulation time 46188455 ps
CPU time 1.2 seconds
Started Aug 01 05:19:19 PM PDT 24
Finished Aug 01 05:19:20 PM PDT 24
Peak memory 196568 kb
Host smart-7b102bc9-cebd-4d7d-9a89-9d41df5dce13
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=175473420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.175473420
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.960409129
Short name T842
Test name
Test status
Simulation time 200678093 ps
CPU time 0.8 seconds
Started Aug 01 05:19:25 PM PDT 24
Finished Aug 01 05:19:27 PM PDT 24
Peak memory 195440 kb
Host smart-1cf37f48-af8e-450a-b245-1dd86db81556
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960409129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.960409129
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.770640147
Short name T927
Test name
Test status
Simulation time 153090168 ps
CPU time 1.04 seconds
Started Aug 01 05:19:22 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 196476 kb
Host smart-3b985388-0b83-4347-8c8b-19738d1de335
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=770640147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.770640147
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.876415216
Short name T841
Test name
Test status
Simulation time 163229118 ps
CPU time 1.19 seconds
Started Aug 01 05:19:22 PM PDT 24
Finished Aug 01 05:19:23 PM PDT 24
Peak memory 196484 kb
Host smart-1a06a0ce-60fb-4a81-b66f-38b073240c2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876415216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.876415216
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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