Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4281218	1			T35	1		T36	1		T37	92
all_pins[1]	4281218	1			T35	1		T36	1		T37	92
all_pins[2]	4281218	1			T35	1		T36	1		T37	92
all_pins[3]	4281218	1			T35	1		T36	1		T37	92
all_pins[4]	4281218	1			T35	1		T36	1		T37	92
all_pins[5]	4281218	1			T35	1		T36	1		T37	92
all_pins[6]	4281218	1			T35	1		T36	1		T37	92
all_pins[7]	4281218	1			T35	1		T36	1		T37	92
all_pins[8]	4281218	1			T35	1		T36	1		T37	92
all_pins[9]	4281218	1			T35	1		T36	1		T37	92
all_pins[10]	4281218	1			T35	1		T36	1		T37	92
all_pins[11]	4281218	1			T35	1		T36	1		T37	92
all_pins[12]	4281218	1			T35	1		T36	1		T37	92
all_pins[13]	4281218	1			T35	1		T36	1		T37	92
all_pins[14]	4281218	1			T35	1		T36	1		T37	92
all_pins[15]	4281218	1			T35	1		T36	1		T37	92
all_pins[16]	4281218	1			T35	1		T36	1		T37	92
all_pins[17]	4281218	1			T35	1		T36	1		T37	92
all_pins[18]	4281218	1			T35	1		T36	1		T37	92
all_pins[19]	4281218	1			T35	1		T36	1		T37	92
all_pins[20]	4281218	1			T35	1		T36	1		T37	92
all_pins[21]	4281218	1			T35	1		T36	1		T37	92
all_pins[22]	4281218	1			T35	1		T36	1		T37	92
all_pins[23]	4281218	1			T35	1		T36	1		T37	92
all_pins[24]	4281218	1			T35	1		T36	1		T37	92
all_pins[25]	4281218	1			T35	1		T36	1		T37	92
all_pins[26]	4281218	1			T35	1		T36	1		T37	92
all_pins[27]	4281218	1			T35	1		T36	1		T37	92
all_pins[28]	4281218	1			T35	1		T36	1		T37	92
all_pins[29]	4281218	1			T35	1		T36	1		T37	92
all_pins[30]	4281218	1			T35	1		T36	1		T37	92
all_pins[31]	4281218	1			T35	1		T36	1		T37	92

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	85099805	1			T35	32		T36	32		T37	2572
values[0x1]	51899171	1			T37	372		T38	1072		T39	3025
transitions[0x0=>0x1]	31086067	1			T37	239		T38	514		T39	1774
transitions[0x1=>0x0]	31085895	1			T37	239		T38	514		T39	1773

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2658380	1			T35	1		T36	1		T37	72
all_pins[0]	values[0x1]	1622838	1			T37	20		T38	30		T39	66
all_pins[0]	transitions[0x0=>0x1]	1004688	1			T37	19		T38	14		T39	24
all_pins[0]	transitions[0x1=>0x0]	1004941	1			T37	1		T38	9		T39	81
all_pins[1]	values[0x0]	2659404	1			T35	1		T36	1		T37	83
all_pins[1]	values[0x1]	1621814	1			T37	9		T38	29		T39	93
all_pins[1]	transitions[0x0=>0x1]	968981	1			T37	2		T38	13		T39	71
all_pins[1]	transitions[0x1=>0x0]	970005	1			T37	13		T38	14		T39	44
all_pins[2]	values[0x0]	2658589	1			T35	1		T36	1		T37	83
all_pins[2]	values[0x1]	1622629	1			T37	9		T38	24		T39	89
all_pins[2]	transitions[0x0=>0x1]	970128	1			T37	9		T38	11		T39	48
all_pins[2]	transitions[0x1=>0x0]	969313	1			T37	9		T38	16		T39	52
all_pins[3]	values[0x0]	2656675	1			T35	1		T36	1		T37	83
all_pins[3]	values[0x1]	1624543	1			T37	9		T38	34		T39	102
all_pins[3]	transitions[0x0=>0x1]	969139	1			T37	7		T38	23		T39	65
all_pins[3]	transitions[0x1=>0x0]	967225	1			T37	7		T38	13		T39	52
all_pins[4]	values[0x0]	2660862	1			T35	1		T36	1		T37	76
all_pins[4]	values[0x1]	1620356	1			T37	16		T38	32		T39	89
all_pins[4]	transitions[0x0=>0x1]	969545	1			T37	7		T38	15		T39	36
all_pins[4]	transitions[0x1=>0x0]	973732	1			T38	17		T39	49		T42	7
all_pins[5]	values[0x0]	2656879	1			T35	1		T36	1		T37	79
all_pins[5]	values[0x1]	1624339	1			T37	13		T38	38		T39	85
all_pins[5]	transitions[0x0=>0x1]	971607	1			T37	6		T38	21		T39	66
all_pins[5]	transitions[0x1=>0x0]	967624	1			T37	9		T38	15		T39	70
all_pins[6]	values[0x0]	2664962	1			T35	1		T36	1		T37	76
all_pins[6]	values[0x1]	1616256	1			T37	16		T38	23		T39	90
all_pins[6]	transitions[0x0=>0x1]	967702	1			T37	5		T38	13		T39	48
all_pins[6]	transitions[0x1=>0x0]	975785	1			T37	2		T38	28		T39	43
all_pins[7]	values[0x0]	2662484	1			T35	1		T36	1		T37	81
all_pins[7]	values[0x1]	1618734	1			T37	11		T38	33		T39	90
all_pins[7]	transitions[0x0=>0x1]	971189	1			T37	2		T38	24		T39	46
all_pins[7]	transitions[0x1=>0x0]	968711	1			T37	7		T38	14		T39	46
all_pins[8]	values[0x0]	2663897	1			T35	1		T36	1		T37	83
all_pins[8]	values[0x1]	1617321	1			T37	9		T38	32		T39	89
all_pins[8]	transitions[0x0=>0x1]	968951	1			T37	7		T38	11		T39	58
all_pins[8]	transitions[0x1=>0x0]	970364	1			T37	9		T38	12		T39	59
all_pins[9]	values[0x0]	2659805	1			T35	1		T36	1		T37	86
all_pins[9]	values[0x1]	1621413	1			T37	6		T38	39		T39	102
all_pins[9]	transitions[0x0=>0x1]	970940	1			T37	6		T38	20		T39	65
all_pins[9]	transitions[0x1=>0x0]	966848	1			T37	9		T38	13		T39	52
all_pins[10]	values[0x0]	2664310	1			T35	1		T36	1		T37	76
all_pins[10]	values[0x1]	1616908	1			T37	16		T38	39		T39	63
all_pins[10]	transitions[0x0=>0x1]	968921	1			T37	14		T38	18		T39	36
all_pins[10]	transitions[0x1=>0x0]	973426	1			T37	4		T38	18		T39	75
all_pins[11]	values[0x0]	2658536	1			T35	1		T36	1		T37	77
all_pins[11]	values[0x1]	1622682	1			T37	15		T38	31		T39	103
all_pins[11]	transitions[0x0=>0x1]	974590	1			T37	8		T38	13		T39	72
all_pins[11]	transitions[0x1=>0x0]	968816	1			T37	9		T38	21		T39	32
all_pins[12]	values[0x0]	2658456	1			T35	1		T36	1		T37	81
all_pins[12]	values[0x1]	1622762	1			T37	11		T38	31		T39	103
all_pins[12]	transitions[0x0=>0x1]	971530	1			T37	6		T38	13		T39	63
all_pins[12]	transitions[0x1=>0x0]	971450	1			T37	10		T38	13		T39	63
all_pins[13]	values[0x0]	2654711	1			T35	1		T36	1		T37	76
all_pins[13]	values[0x1]	1626507	1			T37	16		T38	36		T39	96
all_pins[13]	transitions[0x0=>0x1]	975067	1			T37	8		T38	20		T39	53
all_pins[13]	transitions[0x1=>0x0]	971322	1			T37	3		T38	15		T39	60
all_pins[14]	values[0x0]	2657403	1			T35	1		T36	1		T37	79
all_pins[14]	values[0x1]	1623815	1			T37	13		T38	37		T39	114
all_pins[14]	transitions[0x0=>0x1]	968913	1			T37	9		T38	16		T39	60
all_pins[14]	transitions[0x1=>0x0]	971605	1			T37	12		T38	15		T39	42
all_pins[15]	values[0x0]	2654313	1			T35	1		T36	1		T37	77
all_pins[15]	values[0x1]	1626905	1			T37	15		T38	36		T39	79
all_pins[15]	transitions[0x0=>0x1]	975001	1			T37	6		T38	15		T39	43
all_pins[15]	transitions[0x1=>0x0]	971911	1			T37	4		T38	16		T39	78
all_pins[16]	values[0x0]	2651606	1			T35	1		T36	1		T37	75
all_pins[16]	values[0x1]	1629612	1			T37	17		T38	34		T39	100
all_pins[16]	transitions[0x0=>0x1]	973106	1			T37	9		T38	19		T39	53
all_pins[16]	transitions[0x1=>0x0]	970399	1			T37	7		T38	21		T39	32
all_pins[17]	values[0x0]	2656381	1			T35	1		T36	1		T37	80
all_pins[17]	values[0x1]	1624837	1			T37	12		T38	37		T39	82
all_pins[17]	transitions[0x0=>0x1]	970750	1			T37	7		T38	17		T39	45
all_pins[17]	transitions[0x1=>0x0]	975525	1			T37	12		T38	14		T39	63
all_pins[18]	values[0x0]	2661102	1			T35	1		T36	1		T37	80
all_pins[18]	values[0x1]	1620116	1			T37	12		T38	30		T39	102
all_pins[18]	transitions[0x0=>0x1]	968551	1			T37	6		T38	13		T39	64
all_pins[18]	transitions[0x1=>0x0]	973272	1			T37	6		T38	20		T39	44
all_pins[19]	values[0x0]	2659550	1			T35	1		T36	1		T37	90
all_pins[19]	values[0x1]	1621668	1			T37	2		T38	36		T39	92
all_pins[19]	transitions[0x0=>0x1]	968201	1			T38	22		T39	54		T42	10
all_pins[19]	transitions[0x1=>0x0]	966649	1			T37	10		T38	16		T39	64
all_pins[20]	values[0x0]	2662028	1			T35	1		T36	1		T37	81
all_pins[20]	values[0x1]	1619190	1			T37	11		T38	45		T39	95
all_pins[20]	transitions[0x0=>0x1]	970059	1			T37	11		T38	18		T39	54
all_pins[20]	transitions[0x1=>0x0]	972537	1			T37	2		T38	9		T39	51
all_pins[21]	values[0x0]	2661113	1			T35	1		T36	1		T37	78
all_pins[21]	values[0x1]	1620105	1			T37	14		T38	32		T39	87
all_pins[21]	transitions[0x0=>0x1]	969018	1			T37	11		T38	12		T39	58
all_pins[21]	transitions[0x1=>0x0]	968103	1			T37	8		T38	25		T39	66
all_pins[22]	values[0x0]	2656125	1			T35	1		T36	1		T37	80
all_pins[22]	values[0x1]	1625093	1			T37	12		T38	41		T39	123
all_pins[22]	transitions[0x0=>0x1]	972709	1			T37	10		T38	20		T39	92
all_pins[22]	transitions[0x1=>0x0]	967721	1			T37	12		T38	11		T39	56
all_pins[23]	values[0x0]	2660991	1			T35	1		T36	1		T37	77
all_pins[23]	values[0x1]	1620227	1			T37	15		T38	38		T39	85
all_pins[23]	transitions[0x0=>0x1]	967883	1			T37	12		T38	11		T39	46
all_pins[23]	transitions[0x1=>0x0]	972749	1			T37	9		T38	14		T39	84
all_pins[24]	values[0x0]	2663650	1			T35	1		T36	1		T37	85
all_pins[24]	values[0x1]	1617568	1			T37	7		T38	33		T39	109
all_pins[24]	transitions[0x0=>0x1]	968227	1			T37	5		T38	11		T39	63
all_pins[24]	transitions[0x1=>0x0]	970886	1			T37	13		T38	16		T39	39
all_pins[25]	values[0x0]	2660639	1			T35	1		T36	1		T37	76
all_pins[25]	values[0x1]	1620579	1			T37	16		T38	32		T39	87
all_pins[25]	transitions[0x0=>0x1]	972386	1			T37	14		T38	17		T39	47
all_pins[25]	transitions[0x1=>0x0]	969375	1			T37	5		T38	18		T39	69
all_pins[26]	values[0x0]	2661192	1			T35	1		T36	1		T37	80
all_pins[26]	values[0x1]	1620026	1			T37	12		T38	36		T39	127
all_pins[26]	transitions[0x0=>0x1]	968467	1			T37	6		T38	18		T39	76
all_pins[26]	transitions[0x1=>0x0]	969020	1			T37	10		T38	14		T39	36
all_pins[27]	values[0x0]	2659625	1			T35	1		T36	1		T37	87
all_pins[27]	values[0x1]	1621593	1			T37	5		T38	34		T39	92
all_pins[27]	transitions[0x0=>0x1]	971859	1			T37	2		T38	20		T39	36
all_pins[27]	transitions[0x1=>0x0]	970292	1			T37	9		T38	22		T39	71
all_pins[28]	values[0x0]	2658239	1			T35	1		T36	1		T37	84
all_pins[28]	values[0x1]	1622979	1			T37	8		T38	40		T39	72
all_pins[28]	transitions[0x0=>0x1]	969409	1			T37	6		T38	21		T39	47
all_pins[28]	transitions[0x1=>0x0]	968023	1			T37	3		T38	15		T39	67
all_pins[29]	values[0x0]	2659263	1			T35	1		T36	1		T37	86
all_pins[29]	values[0x1]	1621955	1			T37	6		T38	30		T39	97
all_pins[29]	transitions[0x0=>0x1]	968184	1			T37	6		T38	12		T39	55
all_pins[29]	transitions[0x1=>0x0]	969208	1			T37	8		T38	22		T39	30
all_pins[30]	values[0x0]	2660680	1			T35	1		T36	1		T37	75
all_pins[30]	values[0x1]	1620538	1			T37	17		T38	25		T39	98
all_pins[30]	transitions[0x0=>0x1]	969320	1			T37	11		T38	9		T39	51
all_pins[30]	transitions[0x1=>0x0]	970737	1			T38	14		T39	50		T42	13
all_pins[31]	values[0x0]	2657955	1			T35	1		T36	1		T37	90
all_pins[31]	values[0x1]	1623263	1			T37	2		T38	25		T39	124
all_pins[31]	transitions[0x0=>0x1]	971046	1			T37	2		T38	14		T39	79
all_pins[31]	transitions[0x1=>0x0]	968321	1			T37	17		T38	14		T39	53