Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14557480	1			T35	53		T36	57		T37	137
all_values[1]	14557480	1			T35	53		T36	57		T37	137
all_values[2]	14557480	1			T35	53		T36	57		T37	137
all_values[3]	14557480	1			T35	53		T36	57		T37	137
all_values[4]	14557480	1			T35	53		T36	57		T37	137
all_values[5]	14557480	1			T35	53		T36	57		T37	137
all_values[6]	14557480	1			T35	53		T36	57		T37	137
all_values[7]	14557480	1			T35	53		T36	57		T37	137
all_values[8]	14557480	1			T35	53		T36	57		T37	137
all_values[9]	14557480	1			T35	53		T36	57		T37	137
all_values[10]	14557480	1			T35	53		T36	57		T37	137
all_values[11]	14557480	1			T35	53		T36	57		T37	137
all_values[12]	14557480	1			T35	53		T36	57		T37	137
all_values[13]	14557480	1			T35	53		T36	57		T37	137
all_values[14]	14557480	1			T35	53		T36	57		T37	137
all_values[15]	14557480	1			T35	53		T36	57		T37	137
all_values[16]	14557480	1			T35	53		T36	57		T37	137
all_values[17]	14557480	1			T35	53		T36	57		T37	137
all_values[18]	14557480	1			T35	53		T36	57		T37	137
all_values[19]	14557480	1			T35	53		T36	57		T37	137
all_values[20]	14557480	1			T35	53		T36	57		T37	137
all_values[21]	14557480	1			T35	53		T36	57		T37	137
all_values[22]	14557480	1			T35	53		T36	57		T37	137
all_values[23]	14557480	1			T35	53		T36	57		T37	137
all_values[24]	14557480	1			T35	53		T36	57		T37	137
all_values[25]	14557480	1			T35	53		T36	57		T37	137
all_values[26]	14557480	1			T35	53		T36	57		T37	137
all_values[27]	14557480	1			T35	53		T36	57		T37	137
all_values[28]	14557480	1			T35	53		T36	57		T37	137
all_values[29]	14557480	1			T35	53		T36	57		T37	137
all_values[30]	14557480	1			T35	53		T36	57		T37	137
all_values[31]	14557480	1			T35	53		T36	57		T37	137

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271012349

1

T35

1696

T36

1824

T37

3486

auto[1]

194827011

1

T37

898

T39

6868

T54

2847

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113049712

1

T35

1696

T36

1824

T37

2840

auto[1]

352789648

1

T37

1544

T39

11120

T54

4919

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

460768252

1

T35

1696

T36

1824

T37

4145

auto[1]

5071108

1

T37

239

T18

63

T24

1157

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2946658	1			T35	53		T36	57		T37	68
all_values[0]	auto[0]	auto[0]	auto[1]	5463741	1			T37	20		T39	179		T54	76
all_values[0]	auto[0]	auto[1]	auto[0]	587341	1			T37	18		T39	48		T54	4
all_values[0]	auto[0]	auto[1]	auto[1]	5401671	1			T37	19		T39	126		T54	101
all_values[0]	auto[1]	auto[0]	auto[1]	78989	1			T37	9		T18	2		T24	13
all_values[0]	auto[1]	auto[1]	auto[1]	79080	1			T37	3		T24	19		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	2939636	1			T35	53		T36	57		T37	90
all_values[1]	auto[0]	auto[0]	auto[1]	5452323	1			T37	28		T39	192		T54	104
all_values[1]	auto[0]	auto[1]	auto[0]	584470	1			T37	4		T39	26		T54	17
all_values[1]	auto[0]	auto[1]	auto[1]	5422403	1			T37	6		T39	171		T54	55
all_values[1]	auto[1]	auto[0]	auto[1]	79460	1			T37	7		T18	2		T24	16
all_values[1]	auto[1]	auto[1]	auto[1]	79188	1			T37	2		T24	25		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	2946169	1			T35	53		T36	57		T37	71
all_values[2]	auto[0]	auto[0]	auto[1]	5429648	1			T37	35		T39	140		T54	89
all_values[2]	auto[0]	auto[1]	auto[0]	581259	1			T37	16		T39	50		T54	11
all_values[2]	auto[0]	auto[1]	auto[1]	5441942	1			T37	6		T39	163		T54	54
all_values[2]	auto[1]	auto[0]	auto[1]	79454	1			T37	8		T18	4		T24	31
all_values[2]	auto[1]	auto[1]	auto[1]	79008	1			T37	1		T24	9		T19	4
all_values[3]	auto[0]	auto[0]	auto[0]	2942243	1			T35	53		T36	57		T37	50
all_values[3]	auto[0]	auto[0]	auto[1]	5419264	1			T37	42		T39	150		T54	57
all_values[3]	auto[0]	auto[1]	auto[0]	588602	1			T37	26		T39	33		T54	27
all_values[3]	auto[0]	auto[1]	auto[1]	5448521	1			T37	11		T39	175		T54	78
all_values[3]	auto[1]	auto[0]	auto[1]	79708	1			T37	8		T18	2		T24	17
all_values[3]	auto[1]	auto[1]	auto[1]	79142	1			T24	20		T19	3		T1	7
all_values[4]	auto[0]	auto[0]	auto[0]	2945935	1			T35	53		T36	57		T37	80
all_values[4]	auto[0]	auto[0]	auto[1]	5446036	1			T37	23		T39	176		T54	83
all_values[4]	auto[0]	auto[1]	auto[0]	587095	1			T37	10		T39	41		T54	23
all_values[4]	auto[0]	auto[1]	auto[1]	5419900	1			T37	17		T39	173		T54	65
all_values[4]	auto[1]	auto[0]	auto[1]	79310	1			T37	6		T24	22		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	79204	1			T37	1		T24	9		T19	4
all_values[5]	auto[0]	auto[0]	auto[0]	2934705	1			T35	53		T36	57		T37	88
all_values[5]	auto[0]	auto[0]	auto[1]	5415070	1			T37	19		T39	137		T54	75
all_values[5]	auto[0]	auto[1]	auto[0]	585115	1			T37	10		T39	30		T54	33
all_values[5]	auto[0]	auto[1]	auto[1]	5463956	1			T37	13		T39	172		T54	66
all_values[5]	auto[1]	auto[0]	auto[1]	79682	1			T37	6		T18	1		T24	21
all_values[5]	auto[1]	auto[1]	auto[1]	78952	1			T37	1		T24	13		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	2938660	1			T35	53		T36	57		T37	74
all_values[6]	auto[0]	auto[0]	auto[1]	5474989	1			T37	24		T39	164		T54	111
all_values[6]	auto[0]	auto[1]	auto[0]	586075	1			T37	12		T39	52		T54	9
all_values[6]	auto[0]	auto[1]	auto[1]	5399678	1			T37	19		T39	166		T54	60
all_values[6]	auto[1]	auto[0]	auto[1]	79701	1			T37	7		T18	3		T24	15
all_values[6]	auto[1]	auto[1]	auto[1]	78377	1			T37	1		T24	18		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	2950129	1			T35	53		T36	57		T37	72
all_values[7]	auto[0]	auto[0]	auto[1]	5465195	1			T37	30		T39	152		T54	80
all_values[7]	auto[0]	auto[1]	auto[0]	579804	1			T37	18		T39	53		T156	185
all_values[7]	auto[0]	auto[1]	auto[1]	5404170	1			T37	9		T39	184		T54	88
all_values[7]	auto[1]	auto[0]	auto[1]	79038	1			T37	4		T18	2		T24	11
all_values[7]	auto[1]	auto[1]	auto[1]	79144	1			T37	4		T24	15		T1	6
all_values[8]	auto[0]	auto[0]	auto[0]	2949568	1			T35	53		T36	57		T37	89
all_values[8]	auto[0]	auto[0]	auto[1]	5443792	1			T37	12		T39	150		T54	84
all_values[8]	auto[0]	auto[1]	auto[0]	590973	1			T37	22		T39	37		T54	19
all_values[8]	auto[0]	auto[1]	auto[1]	5414744	1			T37	7		T39	190		T54	58
all_values[8]	auto[1]	auto[0]	auto[1]	79522	1			T37	5		T18	2		T24	12
all_values[8]	auto[1]	auto[1]	auto[1]	78881	1			T37	2		T24	25		T1	11
all_values[9]	auto[0]	auto[0]	auto[0]	2941211	1			T35	53		T36	57		T37	69
all_values[9]	auto[0]	auto[0]	auto[1]	5480859	1			T37	40		T39	126		T54	88
all_values[9]	auto[0]	auto[1]	auto[0]	587721	1			T37	12		T39	53		T156	111
all_values[9]	auto[0]	auto[1]	auto[1]	5389519	1			T37	9		T39	189		T54	91
all_values[9]	auto[1]	auto[0]	auto[1]	79430	1			T37	6		T18	2		T24	19
all_values[9]	auto[1]	auto[1]	auto[1]	78740	1			T37	1		T24	16		T19	2
all_values[10]	auto[0]	auto[0]	auto[0]	2950682	1			T35	53		T36	57		T37	62
all_values[10]	auto[0]	auto[0]	auto[1]	5455562	1			T37	34		T39	222		T54	48
all_values[10]	auto[0]	auto[1]	auto[0]	588173	1			T37	18		T39	33		T54	21
all_values[10]	auto[0]	auto[1]	auto[1]	5404596	1			T37	17		T39	129		T54	92
all_values[10]	auto[1]	auto[0]	auto[1]	80090	1			T37	5		T18	1		T24	17
all_values[10]	auto[1]	auto[1]	auto[1]	78377	1			T37	1		T18	1		T24	14
all_values[11]	auto[0]	auto[0]	auto[0]	2942996	1			T35	53		T36	57		T37	65
all_values[11]	auto[0]	auto[0]	auto[1]	5432796	1			T37	40		T39	170		T54	93
all_values[11]	auto[0]	auto[1]	auto[0]	587485	1			T37	11		T39	17		T54	7
all_values[11]	auto[0]	auto[1]	auto[1]	5435618	1			T37	11		T39	199		T54	64
all_values[11]	auto[1]	auto[0]	auto[1]	79612	1			T37	8		T18	2		T24	34
all_values[11]	auto[1]	auto[1]	auto[1]	78973	1			T37	2		T24	11		T19	2
all_values[12]	auto[0]	auto[0]	auto[0]	2940620	1			T35	53		T36	57		T37	84
all_values[12]	auto[0]	auto[0]	auto[1]	5427737	1			T37	17		T39	126		T54	81
all_values[12]	auto[0]	auto[1]	auto[0]	590815	1			T37	16		T39	35		T54	13
all_values[12]	auto[0]	auto[1]	auto[1]	5440090	1			T37	11		T39	199		T54	69
all_values[12]	auto[1]	auto[0]	auto[1]	79729	1			T37	8		T18	1		T24	20
all_values[12]	auto[1]	auto[1]	auto[1]	78489	1			T37	1		T24	13		T19	1
all_values[13]	auto[0]	auto[0]	auto[0]	2945452	1			T35	53		T36	57		T37	72
all_values[13]	auto[0]	auto[0]	auto[1]	5427289	1			T37	35		T39	143		T54	88
all_values[13]	auto[0]	auto[1]	auto[0]	588360	1			T37	9		T39	34		T54	11
all_values[13]	auto[0]	auto[1]	auto[1]	5437470	1			T37	16		T39	192		T54	69
all_values[13]	auto[1]	auto[0]	auto[1]	79822	1			T37	4		T18	3		T24	18
all_values[13]	auto[1]	auto[1]	auto[1]	79087	1			T37	1		T24	16		T19	4
all_values[14]	auto[0]	auto[0]	auto[0]	2945133	1			T35	53		T36	57		T37	67
all_values[14]	auto[0]	auto[0]	auto[1]	5431924	1			T37	32		T39	112		T54	95
all_values[14]	auto[0]	auto[1]	auto[0]	586822	1			T37	16		T39	44		T54	6
all_values[14]	auto[0]	auto[1]	auto[1]	5434820	1			T37	16		T39	236		T54	78
all_values[14]	auto[1]	auto[0]	auto[1]	79084	1			T37	5		T24	16		T1	6
all_values[14]	auto[1]	auto[1]	auto[1]	79697	1			T37	1		T18	1		T24	27
all_values[15]	auto[0]	auto[0]	auto[0]	2938250	1			T35	53		T36	57		T37	66
all_values[15]	auto[0]	auto[0]	auto[1]	5465381	1			T37	32		T39	190		T54	92
all_values[15]	auto[0]	auto[1]	auto[0]	584136	1			T37	18		T39	32		T54	15
all_values[15]	auto[0]	auto[1]	auto[1]	5411245	1			T37	17		T39	160		T54	56
all_values[15]	auto[1]	auto[0]	auto[1]	79173	1			T37	3		T18	2		T24	12
all_values[15]	auto[1]	auto[1]	auto[1]	79295	1			T37	1		T18	1		T24	21
all_values[16]	auto[0]	auto[0]	auto[0]	2935135	1			T35	53		T36	57		T37	81
all_values[16]	auto[0]	auto[0]	auto[1]	5440650	1			T37	26		T39	152		T54	89
all_values[16]	auto[0]	auto[1]	auto[0]	595421	1			T37	9		T39	19		T54	33
all_values[16]	auto[0]	auto[1]	auto[1]	5427722	1			T37	17		T39	199		T54	57
all_values[16]	auto[1]	auto[0]	auto[1]	79272	1			T37	4		T18	2		T24	19
all_values[16]	auto[1]	auto[1]	auto[1]	79280	1			T24	19		T19	1		T1	9
all_values[17]	auto[0]	auto[0]	auto[0]	2950057	1			T35	53		T36	57		T37	70
all_values[17]	auto[0]	auto[0]	auto[1]	5437085	1			T37	36		T39	170		T54	83
all_values[17]	auto[0]	auto[1]	auto[0]	582333	1			T37	8		T39	24		T54	12
all_values[17]	auto[0]	auto[1]	auto[1]	5429339	1			T37	16		T39	165		T54	89
all_values[17]	auto[1]	auto[0]	auto[1]	79205	1			T37	6		T18	2		T24	19
all_values[17]	auto[1]	auto[1]	auto[1]	79461	1			T37	1		T24	18		T19	2
all_values[18]	auto[0]	auto[0]	auto[0]	2943014	1			T35	53		T36	57		T37	67
all_values[18]	auto[0]	auto[0]	auto[1]	5460950	1			T37	37		T39	172		T54	99
all_values[18]	auto[0]	auto[1]	auto[0]	590313	1			T37	13		T39	30		T54	18
all_values[18]	auto[0]	auto[1]	auto[1]	5404766	1			T37	12		T39	194		T54	63
all_values[18]	auto[1]	auto[0]	auto[1]	79654	1			T37	7		T18	1		T24	20
all_values[18]	auto[1]	auto[1]	auto[1]	78783	1			T37	1		T18	1		T24	15
all_values[19]	auto[0]	auto[0]	auto[0]	2952199	1			T35	53		T36	57		T37	80
all_values[19]	auto[0]	auto[0]	auto[1]	5431436	1			T37	34		T39	169		T54	73
all_values[19]	auto[0]	auto[1]	auto[0]	593456	1			T37	16		T39	20		T54	12
all_values[19]	auto[0]	auto[1]	auto[1]	5422257	1			T37	2		T39	183		T54	77
all_values[19]	auto[1]	auto[0]	auto[1]	79199	1			T37	4		T18	2		T24	16
all_values[19]	auto[1]	auto[1]	auto[1]	78933	1			T37	1		T24	20		T19	4
all_values[20]	auto[0]	auto[0]	auto[0]	2940754	1			T35	53		T36	57		T37	56
all_values[20]	auto[0]	auto[0]	auto[1]	5453953	1			T37	41		T39	176		T54	97
all_values[20]	auto[0]	auto[1]	auto[0]	585180	1			T37	22		T39	42		T54	9
all_values[20]	auto[0]	auto[1]	auto[1]	5419139	1			T37	8		T39	169		T54	74
all_values[20]	auto[1]	auto[0]	auto[1]	79782	1			T37	9		T18	1		T24	16
all_values[20]	auto[1]	auto[1]	auto[1]	78672	1			T37	1		T18	1		T24	20
all_values[21]	auto[0]	auto[0]	auto[0]	2953282	1			T35	53		T36	57		T37	57
all_values[21]	auto[0]	auto[0]	auto[1]	5459352	1			T37	24		T39	202		T54	80
all_values[21]	auto[0]	auto[1]	auto[0]	587575	1			T37	33		T39	10		T54	18
all_values[21]	auto[0]	auto[1]	auto[1]	5399317	1			T37	13		T39	180		T54	74
all_values[21]	auto[1]	auto[0]	auto[1]	79175	1			T37	6		T18	1		T24	17
all_values[21]	auto[1]	auto[1]	auto[1]	78779	1			T37	4		T24	24		T19	1
all_values[22]	auto[0]	auto[0]	auto[0]	2949016	1			T35	53		T36	57		T37	84
all_values[22]	auto[0]	auto[0]	auto[1]	5462600	1			T37	26		T39	119		T54	72
all_values[22]	auto[0]	auto[1]	auto[0]	584941	1			T37	12		T39	37		T54	9
all_values[22]	auto[0]	auto[1]	auto[1]	5402563	1			T37	11		T39	223		T54	90
all_values[22]	auto[1]	auto[0]	auto[1]	79155	1			T37	4		T18	2		T24	25
all_values[22]	auto[1]	auto[1]	auto[1]	79205	1			T18	1		T24	12		T19	2
all_values[23]	auto[0]	auto[0]	auto[0]	2939149	1			T35	53		T36	57		T37	74
all_values[23]	auto[0]	auto[0]	auto[1]	5404612	1			T37	23		T39	215		T54	79
all_values[23]	auto[0]	auto[1]	auto[0]	597104	1			T37	14		T39	20		T54	20
all_values[23]	auto[0]	auto[1]	auto[1]	5457857	1			T37	14		T39	167		T54	65
all_values[23]	auto[1]	auto[0]	auto[1]	79847	1			T37	8		T24	18		T19	1
all_values[23]	auto[1]	auto[1]	auto[1]	78911	1			T37	4		T18	1		T24	15
all_values[24]	auto[0]	auto[0]	auto[0]	2959260	1			T35	53		T36	57		T37	76
all_values[24]	auto[0]	auto[0]	auto[1]	5413134	1			T37	26		T39	148		T54	68
all_values[24]	auto[0]	auto[1]	auto[0]	596000	1			T37	21		T39	53		T54	23
all_values[24]	auto[0]	auto[1]	auto[1]	5431242	1			T37	8		T39	194		T54	66
all_values[24]	auto[1]	auto[0]	auto[1]	79718	1			T37	6		T18	1		T24	20
all_values[24]	auto[1]	auto[1]	auto[1]	78126	1			T24	14		T19	3		T1	2
all_values[25]	auto[0]	auto[0]	auto[0]	2945998	1			T35	53		T36	57		T37	76
all_values[25]	auto[0]	auto[0]	auto[1]	5450107	1			T37	24		T39	176		T54	65
all_values[25]	auto[0]	auto[1]	auto[0]	585180	1			T37	15		T39	24		T54	32
all_values[25]	auto[0]	auto[1]	auto[1]	5417722	1			T37	16		T39	168		T54	81
all_values[25]	auto[1]	auto[0]	auto[1]	79272	1			T37	4		T18	3		T24	18
all_values[25]	auto[1]	auto[1]	auto[1]	79201	1			T37	2		T24	20		T19	3
all_values[26]	auto[0]	auto[0]	auto[0]	2939100	1			T35	53		T36	57		T37	92
all_values[26]	auto[0]	auto[0]	auto[1]	5454205	1			T37	18		T39	144		T54	68
all_values[26]	auto[0]	auto[1]	auto[0]	588764	1			T37	10		T39	26		T54	14
all_values[26]	auto[0]	auto[1]	auto[1]	5417003	1			T37	12		T39	229		T54	83
all_values[26]	auto[1]	auto[0]	auto[1]	79769	1			T37	3		T18	3		T24	19
all_values[26]	auto[1]	auto[1]	auto[1]	78639	1			T37	2		T24	27		T19	1
all_values[27]	auto[0]	auto[0]	auto[0]	2948653	1			T35	53		T36	57		T37	63
all_values[27]	auto[0]	auto[0]	auto[1]	5444122	1			T37	47		T39	215		T54	75
all_values[27]	auto[0]	auto[1]	auto[0]	581826	1			T37	15		T39	17		T54	12
all_values[27]	auto[0]	auto[1]	auto[1]	5424217	1			T37	3		T39	166		T54	83
all_values[27]	auto[1]	auto[0]	auto[1]	79679	1			T37	6		T24	23		T19	2
all_values[27]	auto[1]	auto[1]	auto[1]	78983	1			T37	3		T18	1		T24	17
all_values[28]	auto[0]	auto[0]	auto[0]	2947999	1			T35	53		T36	57		T37	74
all_values[28]	auto[0]	auto[0]	auto[1]	5443231	1			T37	32		T39	205		T54	96
all_values[28]	auto[0]	auto[1]	auto[0]	579520	1			T37	13		T39	22		T54	4
all_values[28]	auto[0]	auto[1]	auto[1]	5428036	1			T37	7		T39	155		T54	79
all_values[28]	auto[1]	auto[0]	auto[1]	79592	1			T37	9		T18	3		T24	12
all_values[28]	auto[1]	auto[1]	auto[1]	79102	1			T37	2		T18	1		T24	18
all_values[29]	auto[0]	auto[0]	auto[0]	2946982	1			T35	53		T36	57		T37	82
all_values[29]	auto[0]	auto[0]	auto[1]	5443170	1			T37	26		T39	175		T54	49
all_values[29]	auto[0]	auto[1]	auto[0]	600028	1			T37	17		T39	34		T54	43
all_values[29]	auto[0]	auto[1]	auto[1]	5408306	1			T37	5		T39	189		T54	77
all_values[29]	auto[1]	auto[0]	auto[1]	79689	1			T37	6		T18	2		T24	17
all_values[29]	auto[1]	auto[1]	auto[1]	79305	1			T37	1		T24	21		T1	6
all_values[30]	auto[0]	auto[0]	auto[0]	2949180	1			T35	53		T36	57		T37	83
all_values[30]	auto[0]	auto[0]	auto[1]	5428258	1			T37	15		T39	170		T54	71
all_values[30]	auto[0]	auto[1]	auto[0]	586769	1			T37	15		T39	22		T54	26
all_values[30]	auto[0]	auto[1]	auto[1]	5434295	1			T37	15		T39	191		T54	72
all_values[30]	auto[1]	auto[0]	auto[1]	79874	1			T37	8		T24	24		T19	3
all_values[30]	auto[1]	auto[1]	auto[1]	79104	1			T37	1		T18	1		T24	15
all_values[31]	auto[0]	auto[0]	auto[0]	2949121	1			T35	53		T36	57		T37	72
all_values[31]	auto[0]	auto[0]	auto[1]	5463382	1			T37	41		T39	146		T54	84
all_values[31]	auto[0]	auto[1]	auto[0]	584110	1			T37	17		T39	13		T54	19
all_values[31]	auto[0]	auto[1]	auto[1]	5402563	1			T37	3		T39	241		T54	53
all_values[31]	auto[1]	auto[0]	auto[1]	78864	1			T37	4		T24	14		T19	2
all_values[31]	auto[1]	auto[1]	auto[1]	79440	1			T18	1		T24	20		T1	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal