Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[1]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[2]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[3]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[4]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[5]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[6]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[7]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[8]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[9]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[10]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[11]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[12]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[13]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[14]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[15]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[16]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[17]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[18]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[19]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[20]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[21]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[22]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[23]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[24]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[25]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[26]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[27]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[28]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[29]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[30]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[31]	14369263	1			T35	107		T36	103		T37	223

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272145369

1

T35

700

T36

2506

T37

3676

auto[1]

187671047

1

T35

2724

T36

790

T37

3460

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369465210

1

T35

3049

T36

2596

T37

6645

auto[1]

90351206

1

T35

375

T36

700

T37

491

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

342829842

1

T35

1755

T36

2117

T37

5651

auto[1]

116986574

1

T35

1669

T36

1179

T37

1485

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5323342	1			T35	1		T36	35		T37	61
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3970457	1			T35	43		T36	9		T37	98
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1419771	1			T35	8		T36	23		T37	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1767727	1			T35	9		T36	17		T37	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	480050	1			T35	43		T36	5		T37	28
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1407916	1			T35	3		T36	14		T37	15
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5315859	1			T35	1		T36	69		T37	63
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3977614	1			T35	39		T36	12		T37	88
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1422398	1			T35	2		T37	2		T40	60
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1763109	1			T35	8		T36	19		T37	26
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	478567	1			T35	57		T36	1		T37	23
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1411716	1			T36	2		T37	21		T40	127
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5315723	1			T35	6		T36	22		T37	33
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3970513	1			T35	35		T36	13		T37	116
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1423631	1			T35	13		T36	8		T37	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1772764	1			T35	4		T36	43		T37	18
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	478044	1			T35	42		T36	9		T37	25
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1408588	1			T35	7		T36	8		T37	28
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5316613	1			T35	2		T36	37		T37	114
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3983613	1			T35	34		T36	15		T37	72
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1419499	1			T35	2		T36	7		T40	123
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1768006	1			T35	16		T36	30		T37	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	474723	1			T35	49		T37	14		T40	47
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1406809	1			T35	4		T36	14		T37	10
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5310677	1			T35	11		T36	44		T37	74
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3979838	1			T35	73		T36	10		T37	89
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1415855	1			T35	2		T36	15		T40	71
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1773351	1			T35	1		T36	19		T37	37
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	478722	1			T35	20		T36	7		T37	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1410820	1			T36	8		T37	12		T40	62
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5308822	1			T35	5		T36	47		T37	118
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3979835	1			T35	57		T36	9		T37	38
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1417959	1			T35	12		T36	36		T40	91
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1774615	1			T35	2		T36	11		T37	45
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	478552	1			T35	29		T37	11		T40	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1409480	1			T35	2		T37	11		T40	67
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5313157	1			T35	17		T36	46		T37	105
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3979967	1			T35	45		T36	9		T37	83
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1418609	1			T35	12		T36	2		T37	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1771946	1			T35	2		T36	40		T37	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	477570	1			T35	27		T36	4		T37	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1408014	1			T35	4		T36	2		T37	9
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5302827	1			T35	12		T36	37		T37	115
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3988997	1			T35	51		T36	5		T37	63
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1417584	1			T35	2		T37	10		T40	86
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1774914	1			T35	7		T36	45		T37	30
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	475268	1			T35	28		T36	4		T37	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1409673	1			T35	7		T36	12		T37	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5320978	1			T36	55		T37	77		T38	429
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3978662	1			T35	29		T36	10		T37	70
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1426070	1			T35	2		T36	4		T37	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1765897	1			T35	18		T36	7		T37	26
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	475533	1			T35	50		T36	7		T37	19
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1402123	1			T35	8		T36	20		T37	29
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5311748	1			T35	14		T36	64		T37	90
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3981223	1			T35	30		T36	6		T37	77
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1421970	1			T35	2		T36	18		T37	8
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1766849	1			T35	4		T36	10		T37	29
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	479312	1			T35	40		T36	2		T37	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1408161	1			T35	17		T36	3		T37	8
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5309808	1			T35	17		T36	67		T37	80
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3981059	1			T35	56		T36	18		T37	73
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1420931	1			T36	18		T37	5		T40	48
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1769136	1			T35	6		T37	29		T40	298
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	476138	1			T35	22		T37	24		T40	33
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1412191	1			T35	6		T37	12		T40	74
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5321490	1			T35	13		T36	25		T37	112
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3966142	1			T35	46		T36	11		T37	65
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1420281	1			T35	4		T36	6		T40	97
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1773405	1			T35	3		T36	32		T37	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	478289	1			T35	36		T36	9		T37	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1409656	1			T35	5		T36	20		T37	7
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5314328	1			T36	64		T37	84		T38	426
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3980276	1			T35	28		T36	18		T37	100
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1418756	1			T35	7		T36	21		T40	70
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1773214	1			T35	13		T37	25		T40	289
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	478326	1			T35	43		T37	7		T40	44
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1404363	1			T35	16		T37	7		T40	104
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5315226	1			T35	10		T36	54		T37	79
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3978210	1			T35	40		T36	12		T37	109
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1420574	1			T35	10		T36	10		T37	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1767790	1			T35	3		T36	13		T37	18
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	477873	1			T35	38		T36	1		T37	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1409590	1			T35	6		T36	13		T37	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5316746	1			T35	1		T36	71		T37	108
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3972295	1			T35	18		T36	9		T37	66
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1425154	1			T35	12		T36	8		T37	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1770125	1			T35	16		T36	7		T37	35
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	477976	1			T35	54		T37	4		T40	22
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1406967	1			T35	6		T36	8		T37	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5302922	1			T35	16		T36	60		T37	81
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3980118	1			T35	36		T36	10		T37	76
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1420706	1			T35	17		T36	6		T37	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1773660	1			T35	2		T36	24		T37	37
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	478706	1			T35	17		T36	1		T37	10
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1413151	1			T35	19		T36	2		T37	13
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5318573	1			T35	1		T36	39		T37	48
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3980888	1			T35	42		T36	12		T37	113
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1417954	1			T35	4		T36	15		T37	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1771654	1			T35	14		T36	16		T37	37
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	478947	1			T35	36		T36	9		T37	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1401247	1			T35	10		T36	12		T37	13
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5308394	1			T35	15		T36	45		T37	96
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3989840	1			T35	36		T36	17		T37	85
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1419178	1			T35	13		T36	10		T37	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1769960	1			T35	1		T36	24		T37	14
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	478744	1			T35	38		T36	2		T37	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1403147	1			T35	4		T36	5		T37	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5314803	1			T35	17		T36	45		T37	127
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3988872	1			T35	54		T36	25		T37	37
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1412884	1			T36	33		T37	6		T40	82
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1773219	1			T35	2		T37	41		T40	246
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	479648	1			T35	34		T37	4		T40	46
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1399837	1			T37	8		T40	85		T41	63
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5308785	1			T35	16		T36	7		T37	102
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3985233	1			T35	44		T36	6		T37	83
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1415642	1			T35	13		T37	3		T40	96
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1773391	1			T35	1		T36	66		T37	22
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	481608	1			T35	23		T36	6		T37	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1404604	1			T35	10		T36	18		T37	6
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5329473	1			T35	19		T36	49		T37	68
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3967236	1			T35	63		T36	9		T37	94
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1413268	1			T36	29		T37	1		T40	66
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1774485	1			T35	1		T36	12		T37	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	481931	1			T35	24		T36	2		T37	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1402870	1			T36	2		T37	24		T40	60
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5320973	1			T35	12		T36	7		T37	117
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3987317	1			T35	20		T36	6		T37	67
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1410806	1			T36	4		T37	8		T40	64
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1776654	1			T35	9		T36	44		T37	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	477023	1			T35	66		T36	12		T37	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1396490	1			T36	30		T37	8		T40	51
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5311414	1			T35	17		T36	48		T37	76
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3983540	1			T35	46		T36	8		T37	107
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1413353	1			T35	12		T36	10		T40	92
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1777796	1			T35	1		T36	24		T37	24
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	478520	1			T35	26		T36	2		T37	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1404640	1			T35	5		T36	11		T37	8
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5304754	1			T35	22		T36	52		T37	76
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3994945	1			T35	58		T36	10		T37	92
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1416480	1			T35	2		T36	10		T37	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1771972	1			T35	2		T36	31		T37	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	478148	1			T35	17		T37	24		T40	33
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1402964	1			T35	6		T37	9		T40	81
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5311685	1			T35	6		T36	25		T37	72
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3983281	1			T35	38		T36	10		T37	117
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1416516	1			T35	4		T36	16		T40	74
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1775865	1			T35	12		T36	40		T37	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	479618	1			T35	39		T36	8		T37	11
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1402298	1			T35	8		T36	4		T37	8
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5303039	1			T35	3		T36	62		T37	95
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3995606	1			T35	29		T36	9		T37	105
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1414565	1			T35	8		T36	4		T37	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1777287	1			T35	12		T36	14		T37	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	480351	1			T35	40		T37	2		T40	50
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1398415	1			T35	15		T36	14		T37	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5319166	1			T35	1		T36	54		T37	71
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3978361	1			T35	15		T36	17		T37	74
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1417423	1			T35	6		T36	28		T37	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1772024	1			T35	12		T36	4		T37	42
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	478216	1			T35	73		T37	9		T40	34
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1404073	1			T37	15		T40	83		T41	106
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5325258	1			T35	3		T36	33		T37	102
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3977910	1			T35	17		T36	10		T37	99
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1414146	1			T36	15		T37	2		T40	94
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1771352	1			T35	10		T36	29		T37	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	479342	1			T35	71		T36	8		T37	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1401255	1			T35	6		T36	8		T37	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5320982	1			T35	3		T36	8		T37	83
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3973114	1			T35	29		T36	5		T37	105
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1418746	1			T35	6		T36	4		T37	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1772292	1			T35	8		T36	49		T37	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	481506	1			T35	61		T36	15		T37	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1402623	1			T36	22		T37	4		T40	82
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5310267	1			T35	6		T36	30		T37	68
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3985951	1			T35	47		T36	8		T37	109
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1418313	1			T35	8		T36	4		T37	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1772598	1			T35	10		T36	23		T37	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	475924	1			T35	36		T36	5		T37	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1406210	1			T36	33		T37	18		T40	72
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5322086	1			T36	31		T37	84		T38	471
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3980449	1			T35	12		T36	9		T37	97
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1413646	1			T36	26		T37	9		T40	93
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1771820	1			T35	15		T36	19		T37	9
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	481060	1			T35	76		T36	7		T37	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1400202	1			T35	4		T36	11		T37	10
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5313311	1			T35	16		T36	45		T37	103
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3985512	1			T35	69		T36	13		T37	56
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1417071	1			T35	10		T37	10		T40	94
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1773524	1			T36	27		T37	31		T40	237
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	478471	1			T35	8		T36	4		T37	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1401374	1			T35	4		T36	14		T37	17

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal