Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[1]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[2]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[3]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[4]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[5]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[6]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[7]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[8]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[9]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[10]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[11]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[12]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[13]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[14]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[15]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[16]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[17]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[18]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[19]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[20]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[21]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[22]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[23]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[24]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[25]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[26]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[27]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[28]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[29]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[30]	14369263	1			T35	107		T36	103		T37	223
bins_for_gpio_bits[31]	14369263	1			T35	107		T36	103		T37	223

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272145369

1

T35

700

T36

2506

T37

3676

auto[1]

187671047

1

T35

2724

T36

790

T37

3460

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272138390

1

T35

700

T36

2506

T37

3670

auto[1]

187678026

1

T35

2724

T36

790

T37

3466

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8258950	1			T35	16		T36	73		T37	82
bins_for_gpio_bits[0]	auto[0]	auto[1]	251664	1			T35	2		T36	2		T40	21
bins_for_gpio_bits[0]	auto[1]	auto[0]	251890	1			T35	2		T36	2		T40	21
bins_for_gpio_bits[0]	auto[1]	auto[1]	5606759	1			T35	87		T36	26		T37	141
bins_for_gpio_bits[1]	auto[0]	auto[0]	8249534	1			T35	10		T36	87		T37	91
bins_for_gpio_bits[1]	auto[0]	auto[1]	251619	1			T35	1		T36	1		T40	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	251832	1			T35	1		T36	1		T40	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	5616278	1			T35	95		T36	14		T37	132
bins_for_gpio_bits[2]	auto[0]	auto[0]	8260137	1			T35	21		T36	72		T37	54
bins_for_gpio_bits[2]	auto[0]	auto[1]	251813	1			T35	2		T36	1		T40	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	251981	1			T35	2		T36	1		T40	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	5605332	1			T35	82		T36	29		T37	169
bins_for_gpio_bits[3]	auto[0]	auto[0]	8251774	1			T35	19		T36	72		T37	127
bins_for_gpio_bits[3]	auto[0]	auto[1]	252126	1			T35	1		T36	2		T40	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	252344	1			T35	1		T36	2		T40	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	5613019	1			T35	86		T36	27		T37	96
bins_for_gpio_bits[4]	auto[0]	auto[0]	8247868	1			T35	13		T36	76		T37	111
bins_for_gpio_bits[4]	auto[0]	auto[1]	251769	1			T35	1		T36	2		T40	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	252015	1			T35	1		T36	2		T40	12
bins_for_gpio_bits[4]	auto[1]	auto[1]	5617611	1			T35	92		T36	23		T37	112
bins_for_gpio_bits[5]	auto[0]	auto[0]	8248981	1			T35	17		T36	94		T37	163
bins_for_gpio_bits[5]	auto[0]	auto[1]	252185	1			T35	2		T40	12		T41	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	252415	1			T35	2		T40	12		T41	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	5615682	1			T35	86		T36	9		T37	60
bins_for_gpio_bits[6]	auto[0]	auto[0]	8250852	1			T35	28		T36	87		T37	122
bins_for_gpio_bits[6]	auto[0]	auto[1]	252631	1			T35	3		T36	1		T40	15
bins_for_gpio_bits[6]	auto[1]	auto[0]	252860	1			T35	3		T36	1		T40	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	5612920	1			T35	73		T36	14		T37	101
bins_for_gpio_bits[7]	auto[0]	auto[0]	8243087	1			T35	20		T36	80		T37	154
bins_for_gpio_bits[7]	auto[0]	auto[1]	252029	1			T35	1		T36	2		T40	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	252238	1			T35	1		T36	2		T37	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5621909	1			T35	85		T36	19		T37	68
bins_for_gpio_bits[8]	auto[0]	auto[0]	8261200	1			T35	19		T36	63		T37	105
bins_for_gpio_bits[8]	auto[0]	auto[1]	251552	1			T35	1		T36	3		T40	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	251745	1			T35	1		T36	3		T40	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	5604766	1			T35	86		T36	34		T37	118
bins_for_gpio_bits[9]	auto[0]	auto[0]	8248726	1			T35	19		T36	91		T37	127
bins_for_gpio_bits[9]	auto[0]	auto[1]	251635	1			T35	1		T36	1		T40	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	251841	1			T35	1		T36	1		T40	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	5617061	1			T35	86		T36	10		T37	96
bins_for_gpio_bits[10]	auto[0]	auto[0]	8247550	1			T35	23		T36	85		T37	114
bins_for_gpio_bits[10]	auto[0]	auto[1]	252108	1			T40	14		T41	13		T44	42
bins_for_gpio_bits[10]	auto[1]	auto[0]	252325	1			T40	15		T41	13		T44	41
bins_for_gpio_bits[10]	auto[1]	auto[1]	5617280	1			T35	84		T36	18		T37	109
bins_for_gpio_bits[11]	auto[0]	auto[0]	8262773	1			T35	19		T36	60		T37	133
bins_for_gpio_bits[11]	auto[0]	auto[1]	252195	1			T35	1		T36	3		T40	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	252403	1			T35	1		T36	3		T40	17
bins_for_gpio_bits[11]	auto[1]	auto[1]	5601892	1			T35	86		T36	37		T37	90
bins_for_gpio_bits[12]	auto[0]	auto[0]	8254723	1			T35	19		T36	85		T37	109
bins_for_gpio_bits[12]	auto[0]	auto[1]	251335	1			T35	1		T40	20		T41	15
bins_for_gpio_bits[12]	auto[1]	auto[0]	251575	1			T35	1		T40	21		T41	15
bins_for_gpio_bits[12]	auto[1]	auto[1]	5611630	1			T35	86		T36	18		T37	114
bins_for_gpio_bits[13]	auto[0]	auto[0]	8251498	1			T35	21		T36	75		T37	108
bins_for_gpio_bits[13]	auto[0]	auto[1]	251877	1			T35	2		T36	2		T40	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	252092	1			T35	2		T36	2		T40	13
bins_for_gpio_bits[13]	auto[1]	auto[1]	5613796	1			T35	82		T36	24		T37	115
bins_for_gpio_bits[14]	auto[0]	auto[0]	8259588	1			T35	27		T36	85		T37	150
bins_for_gpio_bits[14]	auto[0]	auto[1]	252222	1			T35	2		T36	1		T40	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	252437	1			T35	2		T36	1		T37	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5605016	1			T35	76		T36	16		T37	72
bins_for_gpio_bits[15]	auto[0]	auto[0]	8244949	1			T35	31		T36	89		T37	123
bins_for_gpio_bits[15]	auto[0]	auto[1]	252124	1			T35	4		T36	1		T40	22
bins_for_gpio_bits[15]	auto[1]	auto[0]	252339	1			T35	4		T36	1		T37	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	5619851	1			T35	68		T36	12		T37	99
bins_for_gpio_bits[16]	auto[0]	auto[0]	8256271	1			T35	17		T36	68		T37	86
bins_for_gpio_bits[16]	auto[0]	auto[1]	251704	1			T35	2		T36	2		T40	17
bins_for_gpio_bits[16]	auto[1]	auto[0]	251910	1			T35	2		T36	2		T37	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	5609378	1			T35	86		T36	31		T37	136
bins_for_gpio_bits[17]	auto[0]	auto[0]	8245570	1			T35	27		T36	78		T37	117
bins_for_gpio_bits[17]	auto[0]	auto[1]	251776	1			T35	2		T36	1		T40	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	251962	1			T35	2		T36	1		T40	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	5619955	1			T35	76		T36	23		T37	106
bins_for_gpio_bits[18]	auto[0]	auto[0]	8249429	1			T35	19		T36	78		T37	173
bins_for_gpio_bits[18]	auto[0]	auto[1]	251258	1			T37	1		T40	14		T41	20
bins_for_gpio_bits[18]	auto[1]	auto[0]	251477	1			T37	1		T40	15		T41	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	5617099	1			T35	88		T36	25		T37	48
bins_for_gpio_bits[19]	auto[0]	auto[0]	8245601	1			T35	28		T36	70		T37	126
bins_for_gpio_bits[19]	auto[0]	auto[1]	252014	1			T35	2		T36	3		T37	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	252217	1			T35	2		T36	3		T37	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	5619431	1			T35	75		T36	27		T37	95
bins_for_gpio_bits[20]	auto[0]	auto[0]	8265429	1			T35	20		T36	89		T37	86
bins_for_gpio_bits[20]	auto[0]	auto[1]	251567	1			T36	1		T40	14		T41	23
bins_for_gpio_bits[20]	auto[1]	auto[0]	251797	1			T36	1		T40	14		T41	23
bins_for_gpio_bits[20]	auto[1]	auto[1]	5600470	1			T35	87		T36	12		T37	137
bins_for_gpio_bits[21]	auto[0]	auto[0]	8256792	1			T35	21		T36	52		T37	141
bins_for_gpio_bits[21]	auto[0]	auto[1]	251426	1			T36	3		T37	1		T40	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	251641	1			T36	3		T40	11		T41	15
bins_for_gpio_bits[21]	auto[1]	auto[1]	5609404	1			T35	86		T36	45		T37	81
bins_for_gpio_bits[22]	auto[0]	auto[0]	8250146	1			T35	27		T36	80		T37	99
bins_for_gpio_bits[22]	auto[0]	auto[1]	252162	1			T35	3		T36	2		T37	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	252417	1			T35	3		T36	2		T37	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5614538	1			T35	74		T36	19		T37	122
bins_for_gpio_bits[23]	auto[0]	auto[0]	8240781	1			T35	25		T36	93		T37	98
bins_for_gpio_bits[23]	auto[0]	auto[1]	252203	1			T35	1		T40	17		T41	18
bins_for_gpio_bits[23]	auto[1]	auto[0]	252425	1			T35	1		T40	17		T41	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	5623854	1			T35	80		T36	10		T37	125
bins_for_gpio_bits[24]	auto[0]	auto[0]	8251995	1			T35	20		T36	79		T37	87
bins_for_gpio_bits[24]	auto[0]	auto[1]	251858	1			T35	2		T36	2		T40	14
bins_for_gpio_bits[24]	auto[1]	auto[0]	252071	1			T35	2		T36	2		T40	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	5613339	1			T35	83		T36	20		T37	136
bins_for_gpio_bits[25]	auto[0]	auto[0]	8243441	1			T35	21		T36	78		T37	115
bins_for_gpio_bits[25]	auto[0]	auto[1]	251218	1			T35	2		T36	2		T40	17
bins_for_gpio_bits[25]	auto[1]	auto[0]	251450	1			T35	2		T36	2		T40	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	5623154	1			T35	82		T36	21		T37	108
bins_for_gpio_bits[26]	auto[0]	auto[0]	8256605	1			T35	18		T36	86		T37	124
bins_for_gpio_bits[26]	auto[0]	auto[1]	251750	1			T35	1		T40	13		T41	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	252008	1			T35	1		T37	1		T40	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	5608900	1			T35	87		T36	17		T37	98
bins_for_gpio_bits[27]	auto[0]	auto[0]	8258850	1			T35	13		T36	75		T37	116
bins_for_gpio_bits[27]	auto[0]	auto[1]	251695	1			T36	2		T40	12		T41	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	251906	1			T36	2		T40	12		T41	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	5606812	1			T35	94		T36	24		T37	107
bins_for_gpio_bits[28]	auto[0]	auto[0]	8259995	1			T35	16		T36	57		T37	104
bins_for_gpio_bits[28]	auto[0]	auto[1]	251770	1			T35	1		T36	4		T40	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	252025	1			T35	1		T36	4		T40	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5605473	1			T35	89		T36	38		T37	119
bins_for_gpio_bits[29]	auto[0]	auto[0]	8248934	1			T35	22		T36	54		T37	77
bins_for_gpio_bits[29]	auto[0]	auto[1]	252036	1			T35	2		T36	3		T40	14
bins_for_gpio_bits[29]	auto[1]	auto[0]	252244	1			T35	2		T36	3		T40	14
bins_for_gpio_bits[29]	auto[1]	auto[1]	5616049	1			T35	81		T36	43		T37	146
bins_for_gpio_bits[30]	auto[0]	auto[0]	8256133	1			T35	15		T36	74		T37	101
bins_for_gpio_bits[30]	auto[0]	auto[1]	251197	1			T36	2		T40	15		T41	19
bins_for_gpio_bits[30]	auto[1]	auto[0]	251419	1			T36	2		T37	1		T40	16
bins_for_gpio_bits[30]	auto[1]	auto[1]	5610514	1			T35	92		T36	25		T37	121
bins_for_gpio_bits[31]	auto[0]	auto[0]	8252303	1			T35	23		T36	71		T37	143
bins_for_gpio_bits[31]	auto[0]	auto[1]	251407	1			T35	3		T36	1		T40	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	251603	1			T35	3		T36	1		T37	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5613950	1			T35	78		T36	30		T37	79