Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429457 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
113 |
| auto[1] |
6128023 |
1 |
|
|
T37 |
24 |
|
T39 |
202 |
|
T54 |
99 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13784256 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
135 |
| auto[1] |
773224 |
1 |
|
|
T37 |
2 |
|
T39 |
9 |
|
T54 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8497807 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
94 |
| auto[1] |
6059673 |
1 |
|
|
T37 |
43 |
|
T39 |
225 |
|
T54 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2630138 |
1 |
|
|
T37 |
32 |
|
T39 |
108 |
|
T54 |
58 |
| auto[1] |
auto[0] |
auto[1] |
383750 |
1 |
|
|
T37 |
1 |
|
T39 |
5 |
|
T54 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2656311 |
1 |
|
|
T37 |
9 |
|
T39 |
108 |
|
T54 |
55 |
| auto[1] |
auto[1] |
auto[1] |
389474 |
1 |
|
|
T37 |
1 |
|
T39 |
4 |
|
T156 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |