Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8493350 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
105 |
| auto[1] |
6064130 |
1 |
|
|
T37 |
32 |
|
T39 |
218 |
|
T54 |
69 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13783195 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
774285 |
1 |
|
|
T39 |
11 |
|
T54 |
5 |
|
T156 |
307 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8490865 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
118 |
| auto[1] |
6066615 |
1 |
|
|
T37 |
19 |
|
T39 |
219 |
|
T54 |
112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2661303 |
1 |
|
|
T37 |
13 |
|
T39 |
87 |
|
T54 |
77 |
| auto[1] |
auto[0] |
auto[1] |
390450 |
1 |
|
|
T39 |
4 |
|
T54 |
4 |
|
T156 |
126 |
| auto[1] |
auto[1] |
auto[0] |
2631027 |
1 |
|
|
T37 |
6 |
|
T39 |
121 |
|
T54 |
30 |
| auto[1] |
auto[1] |
auto[1] |
383835 |
1 |
|
|
T39 |
7 |
|
T54 |
1 |
|
T156 |
181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |