Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8494362 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
106 |
| auto[1] |
6063118 |
1 |
|
|
T37 |
31 |
|
T39 |
237 |
|
T54 |
88 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13770664 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
786816 |
1 |
|
|
T39 |
9 |
|
T54 |
5 |
|
T156 |
265 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8408557 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
108 |
| auto[1] |
6148923 |
1 |
|
|
T37 |
29 |
|
T39 |
235 |
|
T54 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693028 |
1 |
|
|
T37 |
25 |
|
T39 |
112 |
|
T54 |
58 |
| auto[1] |
auto[0] |
auto[1] |
397251 |
1 |
|
|
T39 |
3 |
|
T54 |
3 |
|
T156 |
140 |
| auto[1] |
auto[1] |
auto[0] |
2669079 |
1 |
|
|
T37 |
4 |
|
T39 |
114 |
|
T54 |
39 |
| auto[1] |
auto[1] |
auto[1] |
389565 |
1 |
|
|
T39 |
6 |
|
T54 |
2 |
|
T156 |
125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |