Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8472882 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
106 |
| auto[1] |
6084598 |
1 |
|
|
T37 |
31 |
|
T39 |
227 |
|
T54 |
77 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13782944 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
774536 |
1 |
|
|
T39 |
12 |
|
T54 |
8 |
|
T156 |
349 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8489854 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
109 |
| auto[1] |
6067626 |
1 |
|
|
T37 |
28 |
|
T39 |
219 |
|
T54 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2649333 |
1 |
|
|
T37 |
22 |
|
T39 |
85 |
|
T54 |
66 |
| auto[1] |
auto[0] |
auto[1] |
387807 |
1 |
|
|
T39 |
3 |
|
T54 |
6 |
|
T156 |
177 |
| auto[1] |
auto[1] |
auto[0] |
2643757 |
1 |
|
|
T37 |
6 |
|
T39 |
122 |
|
T54 |
42 |
| auto[1] |
auto[1] |
auto[1] |
386729 |
1 |
|
|
T39 |
9 |
|
T54 |
2 |
|
T156 |
172 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |