Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8501500 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
115 |
| auto[1] |
6055980 |
1 |
|
|
T37 |
22 |
|
T39 |
242 |
|
T54 |
91 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13773402 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
136 |
| auto[1] |
784078 |
1 |
|
|
T37 |
1 |
|
T39 |
10 |
|
T54 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442149 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
109 |
| auto[1] |
6115331 |
1 |
|
|
T37 |
28 |
|
T39 |
251 |
|
T54 |
109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689081 |
1 |
|
|
T37 |
19 |
|
T39 |
106 |
|
T54 |
43 |
| auto[1] |
auto[0] |
auto[1] |
395714 |
1 |
|
|
T37 |
1 |
|
T39 |
4 |
|
T54 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2642172 |
1 |
|
|
T37 |
8 |
|
T39 |
135 |
|
T54 |
56 |
| auto[1] |
auto[1] |
auto[1] |
388364 |
1 |
|
|
T39 |
6 |
|
T54 |
6 |
|
T156 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |