Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8489388 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
97 |
| auto[1] |
6068092 |
1 |
|
|
T37 |
40 |
|
T39 |
174 |
|
T54 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12026458 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
136 |
| auto[1] |
2531022 |
1 |
|
|
T37 |
1 |
|
T39 |
84 |
|
T54 |
71 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8472356 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
133 |
| auto[1] |
6085124 |
1 |
|
|
T37 |
4 |
|
T39 |
141 |
|
T54 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780734 |
1 |
|
|
T39 |
38 |
|
T54 |
20 |
|
T156 |
384 |
| auto[1] |
auto[0] |
auto[1] |
1271193 |
1 |
|
|
T39 |
41 |
|
T54 |
31 |
|
T156 |
387 |
| auto[1] |
auto[1] |
auto[0] |
1773368 |
1 |
|
|
T37 |
3 |
|
T39 |
19 |
|
T54 |
47 |
| auto[1] |
auto[1] |
auto[1] |
1259829 |
1 |
|
|
T37 |
1 |
|
T39 |
43 |
|
T54 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |