Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8471419 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
125 |
| auto[1] |
6086061 |
1 |
|
|
T37 |
12 |
|
T39 |
197 |
|
T54 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12022235 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
134 |
| auto[1] |
2535245 |
1 |
|
|
T37 |
3 |
|
T39 |
153 |
|
T54 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8459759 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
134 |
| auto[1] |
6097721 |
1 |
|
|
T37 |
3 |
|
T39 |
281 |
|
T54 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1790009 |
1 |
|
|
T39 |
66 |
|
T54 |
18 |
|
T156 |
378 |
| auto[1] |
auto[0] |
auto[1] |
1270682 |
1 |
|
|
T37 |
1 |
|
T39 |
77 |
|
T54 |
37 |
| auto[1] |
auto[1] |
auto[0] |
1772467 |
1 |
|
|
T39 |
62 |
|
T54 |
15 |
|
T156 |
430 |
| auto[1] |
auto[1] |
auto[1] |
1264563 |
1 |
|
|
T37 |
2 |
|
T39 |
76 |
|
T54 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |