Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8452563 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
111 |
| auto[1] |
6104917 |
1 |
|
|
T37 |
26 |
|
T39 |
226 |
|
T54 |
80 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12030951 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
134 |
| auto[1] |
2526529 |
1 |
|
|
T37 |
3 |
|
T39 |
98 |
|
T54 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8493093 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
126 |
| auto[1] |
6064387 |
1 |
|
|
T37 |
11 |
|
T39 |
181 |
|
T54 |
79 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770499 |
1 |
|
|
T37 |
6 |
|
T39 |
49 |
|
T54 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1262547 |
1 |
|
|
T37 |
3 |
|
T39 |
44 |
|
T54 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1767359 |
1 |
|
|
T37 |
2 |
|
T39 |
34 |
|
T54 |
21 |
| auto[1] |
auto[1] |
auto[1] |
1263982 |
1 |
|
|
T39 |
54 |
|
T54 |
19 |
|
T156 |
467 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |