Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456141 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
104 |
| auto[1] |
6101339 |
1 |
|
|
T37 |
33 |
|
T39 |
280 |
|
T54 |
84 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12030905 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
132 |
| auto[1] |
2526575 |
1 |
|
|
T37 |
5 |
|
T39 |
110 |
|
T54 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469840 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
121 |
| auto[1] |
6087640 |
1 |
|
|
T37 |
16 |
|
T39 |
216 |
|
T54 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780032 |
1 |
|
|
T37 |
10 |
|
T39 |
51 |
|
T54 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1269314 |
1 |
|
|
T37 |
2 |
|
T39 |
36 |
|
T54 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1781033 |
1 |
|
|
T37 |
1 |
|
T39 |
55 |
|
T54 |
14 |
| auto[1] |
auto[1] |
auto[1] |
1257261 |
1 |
|
|
T37 |
3 |
|
T39 |
74 |
|
T54 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |