Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8482804 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
101 |
| auto[1] |
6074676 |
1 |
|
|
T37 |
36 |
|
T39 |
192 |
|
T54 |
71 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12011948 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
2545532 |
1 |
|
|
T39 |
73 |
|
T54 |
19 |
|
T156 |
549 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8443383 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
125 |
| auto[1] |
6114097 |
1 |
|
|
T37 |
12 |
|
T39 |
180 |
|
T54 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1791180 |
1 |
|
|
T37 |
12 |
|
T39 |
58 |
|
T54 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1276524 |
1 |
|
|
T39 |
41 |
|
T54 |
13 |
|
T156 |
250 |
| auto[1] |
auto[1] |
auto[0] |
1777385 |
1 |
|
|
T39 |
49 |
|
T54 |
20 |
|
T156 |
312 |
| auto[1] |
auto[1] |
auto[1] |
1269008 |
1 |
|
|
T39 |
32 |
|
T54 |
6 |
|
T156 |
299 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |