Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455057 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
111 |
| auto[1] |
6102423 |
1 |
|
|
T37 |
26 |
|
T39 |
218 |
|
T54 |
90 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12018827 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
128 |
| auto[1] |
2538653 |
1 |
|
|
T37 |
9 |
|
T39 |
120 |
|
T54 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456148 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
118 |
| auto[1] |
6101332 |
1 |
|
|
T37 |
19 |
|
T39 |
259 |
|
T54 |
101 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1783654 |
1 |
|
|
T37 |
10 |
|
T39 |
75 |
|
T54 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1272274 |
1 |
|
|
T39 |
62 |
|
T54 |
38 |
|
T156 |
358 |
| auto[1] |
auto[1] |
auto[0] |
1779025 |
1 |
|
|
T39 |
64 |
|
T54 |
21 |
|
T156 |
271 |
| auto[1] |
auto[1] |
auto[1] |
1266379 |
1 |
|
|
T37 |
9 |
|
T39 |
58 |
|
T54 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |