Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8466347 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
112 |
| auto[1] |
6091133 |
1 |
|
|
T37 |
25 |
|
T39 |
189 |
|
T54 |
101 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12040115 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
2517365 |
1 |
|
|
T39 |
113 |
|
T54 |
71 |
|
T156 |
722 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8495410 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
126 |
| auto[1] |
6062070 |
1 |
|
|
T37 |
11 |
|
T39 |
198 |
|
T54 |
107 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1774510 |
1 |
|
|
T37 |
3 |
|
T39 |
48 |
|
T54 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1256523 |
1 |
|
|
T39 |
53 |
|
T54 |
30 |
|
T156 |
337 |
| auto[1] |
auto[1] |
auto[0] |
1770195 |
1 |
|
|
T37 |
8 |
|
T39 |
37 |
|
T54 |
20 |
| auto[1] |
auto[1] |
auto[1] |
1260842 |
1 |
|
|
T39 |
60 |
|
T54 |
41 |
|
T156 |
385 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |