Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8483618 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
111 |
| auto[1] |
6073862 |
1 |
|
|
T37 |
26 |
|
T39 |
224 |
|
T54 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12021495 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
132 |
| auto[1] |
2535985 |
1 |
|
|
T37 |
5 |
|
T39 |
114 |
|
T54 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8459661 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
123 |
| auto[1] |
6097819 |
1 |
|
|
T37 |
14 |
|
T39 |
222 |
|
T54 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1789000 |
1 |
|
|
T37 |
6 |
|
T39 |
38 |
|
T54 |
36 |
| auto[1] |
auto[0] |
auto[1] |
1279799 |
1 |
|
|
T37 |
5 |
|
T39 |
70 |
|
T54 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1772834 |
1 |
|
|
T37 |
3 |
|
T39 |
70 |
|
T54 |
36 |
| auto[1] |
auto[1] |
auto[1] |
1256186 |
1 |
|
|
T39 |
44 |
|
T54 |
14 |
|
T156 |
348 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |