Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462834 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
118 |
| auto[1] |
6094646 |
1 |
|
|
T37 |
19 |
|
T39 |
203 |
|
T54 |
89 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12021486 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
2535994 |
1 |
|
|
T39 |
111 |
|
T54 |
53 |
|
T156 |
709 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8464415 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
125 |
| auto[1] |
6093065 |
1 |
|
|
T37 |
12 |
|
T39 |
225 |
|
T54 |
71 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1775757 |
1 |
|
|
T37 |
8 |
|
T39 |
50 |
|
T54 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1269530 |
1 |
|
|
T39 |
59 |
|
T54 |
17 |
|
T156 |
394 |
| auto[1] |
auto[1] |
auto[0] |
1781314 |
1 |
|
|
T37 |
4 |
|
T39 |
64 |
|
T54 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1266464 |
1 |
|
|
T39 |
52 |
|
T54 |
36 |
|
T156 |
315 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |