Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455271 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
114 |
| auto[1] |
6102209 |
1 |
|
|
T37 |
23 |
|
T39 |
213 |
|
T54 |
65 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12021650 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
131 |
| auto[1] |
2535830 |
1 |
|
|
T37 |
6 |
|
T39 |
91 |
|
T54 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456728 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
131 |
| auto[1] |
6100752 |
1 |
|
|
T37 |
6 |
|
T39 |
156 |
|
T54 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1784194 |
1 |
|
|
T39 |
42 |
|
T54 |
14 |
|
T156 |
408 |
| auto[1] |
auto[0] |
auto[1] |
1264990 |
1 |
|
|
T37 |
5 |
|
T39 |
43 |
|
T54 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1780728 |
1 |
|
|
T39 |
23 |
|
T54 |
21 |
|
T156 |
490 |
| auto[1] |
auto[1] |
auto[1] |
1270840 |
1 |
|
|
T37 |
1 |
|
T39 |
48 |
|
T54 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |