Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8474489 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
106 |
| auto[1] |
6082991 |
1 |
|
|
T37 |
31 |
|
T39 |
211 |
|
T54 |
83 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12032093 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
135 |
| auto[1] |
2525387 |
1 |
|
|
T37 |
2 |
|
T39 |
57 |
|
T54 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8481264 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
133 |
| auto[1] |
6076216 |
1 |
|
|
T37 |
4 |
|
T39 |
180 |
|
T54 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1784512 |
1 |
|
|
T37 |
1 |
|
T39 |
48 |
|
T54 |
34 |
| auto[1] |
auto[0] |
auto[1] |
1267987 |
1 |
|
|
T39 |
29 |
|
T54 |
22 |
|
T156 |
307 |
| auto[1] |
auto[1] |
auto[0] |
1766317 |
1 |
|
|
T37 |
1 |
|
T39 |
75 |
|
T54 |
31 |
| auto[1] |
auto[1] |
auto[1] |
1257400 |
1 |
|
|
T37 |
2 |
|
T39 |
28 |
|
T54 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |