Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8491809 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
87 |
| auto[1] |
6065671 |
1 |
|
|
T37 |
50 |
|
T39 |
190 |
|
T54 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12037771 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
129 |
| auto[1] |
2519709 |
1 |
|
|
T37 |
8 |
|
T39 |
75 |
|
T54 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8496748 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
129 |
| auto[1] |
6060732 |
1 |
|
|
T37 |
8 |
|
T39 |
196 |
|
T54 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1779994 |
1 |
|
|
T39 |
68 |
|
T54 |
16 |
|
T156 |
449 |
| auto[1] |
auto[0] |
auto[1] |
1263483 |
1 |
|
|
T37 |
7 |
|
T39 |
40 |
|
T54 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1761029 |
1 |
|
|
T39 |
53 |
|
T54 |
8 |
|
T156 |
502 |
| auto[1] |
auto[1] |
auto[1] |
1256226 |
1 |
|
|
T37 |
1 |
|
T39 |
35 |
|
T54 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |