Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8472454 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
116 |
| auto[1] |
6085026 |
1 |
|
|
T37 |
21 |
|
T39 |
183 |
|
T54 |
95 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13775317 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
136 |
| auto[1] |
782163 |
1 |
|
|
T37 |
1 |
|
T39 |
10 |
|
T54 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8444486 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
108 |
| auto[1] |
6112994 |
1 |
|
|
T37 |
29 |
|
T39 |
169 |
|
T54 |
101 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2682693 |
1 |
|
|
T37 |
26 |
|
T39 |
106 |
|
T54 |
50 |
| auto[1] |
auto[0] |
auto[1] |
394694 |
1 |
|
|
T37 |
1 |
|
T39 |
7 |
|
T54 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2648138 |
1 |
|
|
T37 |
2 |
|
T39 |
53 |
|
T54 |
47 |
| auto[1] |
auto[1] |
auto[1] |
387469 |
1 |
|
|
T39 |
3 |
|
T54 |
2 |
|
T156 |
204 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |