Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8423608 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
105 |
| auto[1] |
6133872 |
1 |
|
|
T37 |
32 |
|
T39 |
187 |
|
T54 |
85 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12024772 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
129 |
| auto[1] |
2532708 |
1 |
|
|
T37 |
8 |
|
T39 |
77 |
|
T54 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469391 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
127 |
| auto[1] |
6088089 |
1 |
|
|
T37 |
10 |
|
T39 |
202 |
|
T54 |
120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780086 |
1 |
|
|
T37 |
2 |
|
T39 |
71 |
|
T54 |
46 |
| auto[1] |
auto[0] |
auto[1] |
1267261 |
1 |
|
|
T37 |
1 |
|
T39 |
53 |
|
T54 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1775295 |
1 |
|
|
T39 |
54 |
|
T54 |
40 |
|
T156 |
523 |
| auto[1] |
auto[1] |
auto[1] |
1265447 |
1 |
|
|
T37 |
7 |
|
T39 |
24 |
|
T54 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |