Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8470822 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
115 |
| auto[1] |
6086658 |
1 |
|
|
T37 |
22 |
|
T39 |
177 |
|
T54 |
83 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13780519 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
776961 |
1 |
|
|
T39 |
16 |
|
T54 |
4 |
|
T156 |
271 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469159 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
104 |
| auto[1] |
6088321 |
1 |
|
|
T37 |
33 |
|
T39 |
270 |
|
T54 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2669403 |
1 |
|
|
T37 |
24 |
|
T39 |
155 |
|
T54 |
53 |
| auto[1] |
auto[0] |
auto[1] |
391084 |
1 |
|
|
T39 |
8 |
|
T54 |
3 |
|
T156 |
123 |
| auto[1] |
auto[1] |
auto[0] |
2641957 |
1 |
|
|
T37 |
9 |
|
T39 |
99 |
|
T54 |
43 |
| auto[1] |
auto[1] |
auto[1] |
385877 |
1 |
|
|
T39 |
8 |
|
T54 |
1 |
|
T156 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |