Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469841 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
114 |
| auto[1] |
6087639 |
1 |
|
|
T37 |
23 |
|
T39 |
223 |
|
T54 |
120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13782286 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
137 |
| auto[1] |
775194 |
1 |
|
|
T39 |
10 |
|
T54 |
5 |
|
T156 |
337 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8494098 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
102 |
| auto[1] |
6063382 |
1 |
|
|
T37 |
35 |
|
T39 |
171 |
|
T54 |
101 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2649073 |
1 |
|
|
T37 |
20 |
|
T39 |
73 |
|
T54 |
35 |
| auto[1] |
auto[0] |
auto[1] |
388094 |
1 |
|
|
T39 |
4 |
|
T54 |
3 |
|
T156 |
165 |
| auto[1] |
auto[1] |
auto[0] |
2639115 |
1 |
|
|
T37 |
15 |
|
T39 |
88 |
|
T54 |
61 |
| auto[1] |
auto[1] |
auto[1] |
387100 |
1 |
|
|
T39 |
6 |
|
T54 |
2 |
|
T156 |
172 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |