Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8457312 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
106 |
| auto[1] |
6100168 |
1 |
|
|
T37 |
31 |
|
T39 |
213 |
|
T54 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13775887 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
136 |
| auto[1] |
781593 |
1 |
|
|
T37 |
1 |
|
T39 |
11 |
|
T54 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8451090 |
1 |
|
|
T35 |
53 |
|
T36 |
57 |
|
T37 |
94 |
| auto[1] |
6106390 |
1 |
|
|
T37 |
43 |
|
T39 |
180 |
|
T54 |
94 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2669460 |
1 |
|
|
T37 |
30 |
|
T39 |
80 |
|
T54 |
48 |
| auto[1] |
auto[0] |
auto[1] |
392055 |
1 |
|
|
T37 |
1 |
|
T39 |
9 |
|
T54 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2655337 |
1 |
|
|
T37 |
12 |
|
T39 |
89 |
|
T54 |
40 |
| auto[1] |
auto[1] |
auto[1] |
389538 |
1 |
|
|
T39 |
2 |
|
T54 |
3 |
|
T156 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |