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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
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T760 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3793552742 Aug 02 04:42:20 PM PDT 24 Aug 02 04:42:21 PM PDT 24 15053825 ps
T761 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1473414292 Aug 02 04:42:24 PM PDT 24 Aug 02 04:42:25 PM PDT 24 16887902 ps
T762 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2427043310 Aug 02 04:42:00 PM PDT 24 Aug 02 04:42:01 PM PDT 24 46641962 ps
T763 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2254756201 Aug 02 04:42:09 PM PDT 24 Aug 02 04:42:10 PM PDT 24 43411437 ps
T764 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.207198772 Aug 02 04:42:09 PM PDT 24 Aug 02 04:42:10 PM PDT 24 19992693 ps
T59 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.815202779 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 189674161 ps
T765 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2931356594 Aug 02 04:42:22 PM PDT 24 Aug 02 04:42:23 PM PDT 24 29070221 ps
T766 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2478661575 Aug 02 04:42:30 PM PDT 24 Aug 02 04:42:31 PM PDT 24 24710426 ps
T118 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.985382344 Aug 02 04:42:11 PM PDT 24 Aug 02 04:42:12 PM PDT 24 67395232 ps
T62 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3528612531 Aug 02 04:42:24 PM PDT 24 Aug 02 04:42:25 PM PDT 24 70274538 ps
T767 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1396443939 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:19 PM PDT 24 206445813 ps
T768 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1873422608 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:19 PM PDT 24 36342022 ps
T769 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2246424212 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 99574541 ps
T770 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.871564731 Aug 02 04:42:11 PM PDT 24 Aug 02 04:42:12 PM PDT 24 22125536 ps
T771 /workspace/coverage/cover_reg_top/32.gpio_intr_test.32469819 Aug 02 04:42:37 PM PDT 24 Aug 02 04:42:38 PM PDT 24 49415624 ps
T772 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2493126426 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 21725890 ps
T773 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3613422702 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:10 PM PDT 24 61500276 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3851585351 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 25926757 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3858412746 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:20 PM PDT 24 537149630 ps
T776 /workspace/coverage/cover_reg_top/4.gpio_intr_test.978401592 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:09 PM PDT 24 100297669 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_intr_test.869040882 Aug 02 04:42:28 PM PDT 24 Aug 02 04:42:29 PM PDT 24 61461340 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2232044108 Aug 02 04:42:27 PM PDT 24 Aug 02 04:42:28 PM PDT 24 18325777 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3012418192 Aug 02 04:42:01 PM PDT 24 Aug 02 04:42:01 PM PDT 24 38616153 ps
T119 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3647438961 Aug 02 04:42:01 PM PDT 24 Aug 02 04:42:02 PM PDT 24 213444227 ps
T780 /workspace/coverage/cover_reg_top/21.gpio_intr_test.728294447 Aug 02 04:42:30 PM PDT 24 Aug 02 04:42:30 PM PDT 24 66773695 ps
T781 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1614558311 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:20 PM PDT 24 290296583 ps
T782 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2244967734 Aug 02 04:42:36 PM PDT 24 Aug 02 04:42:36 PM PDT 24 48579624 ps
T783 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2884847883 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:26 PM PDT 24 14513273 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1247714274 Aug 02 04:42:30 PM PDT 24 Aug 02 04:42:33 PM PDT 24 2354124895 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2157920054 Aug 02 04:42:22 PM PDT 24 Aug 02 04:42:23 PM PDT 24 51150883 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.843745148 Aug 02 04:42:28 PM PDT 24 Aug 02 04:42:29 PM PDT 24 24411748 ps
T787 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1183524804 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:18 PM PDT 24 13873675 ps
T788 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.507016269 Aug 02 04:41:58 PM PDT 24 Aug 02 04:42:00 PM PDT 24 77309705 ps
T789 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3228086405 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 191831349 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.747141741 Aug 02 04:42:24 PM PDT 24 Aug 02 04:42:25 PM PDT 24 91581695 ps
T791 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3145198267 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:27 PM PDT 24 87264368 ps
T792 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3118898045 Aug 02 04:42:07 PM PDT 24 Aug 02 04:42:09 PM PDT 24 277800741 ps
T793 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2382373614 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:09 PM PDT 24 52394967 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1662154584 Aug 02 04:42:07 PM PDT 24 Aug 02 04:42:07 PM PDT 24 70270212 ps
T795 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4057178290 Aug 02 04:42:37 PM PDT 24 Aug 02 04:42:38 PM PDT 24 28808770 ps
T796 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1936252739 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:27 PM PDT 24 277010426 ps
T797 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1173780749 Aug 02 04:42:14 PM PDT 24 Aug 02 04:42:14 PM PDT 24 43056386 ps
T798 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1340704341 Aug 02 04:42:15 PM PDT 24 Aug 02 04:42:15 PM PDT 24 50826183 ps
T799 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1395791863 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:09 PM PDT 24 40687897 ps
T120 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3848497371 Aug 02 04:42:21 PM PDT 24 Aug 02 04:42:22 PM PDT 24 52928983 ps
T800 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1850956884 Aug 02 04:42:46 PM PDT 24 Aug 02 04:42:47 PM PDT 24 34544419 ps
T801 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3553745116 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:25 PM PDT 24 18015166 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1671011201 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:09 PM PDT 24 130188614 ps
T803 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3059070060 Aug 02 04:42:11 PM PDT 24 Aug 02 04:42:13 PM PDT 24 180845892 ps
T121 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.584953771 Aug 02 04:42:09 PM PDT 24 Aug 02 04:42:10 PM PDT 24 69923654 ps
T804 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2352462515 Aug 02 04:42:34 PM PDT 24 Aug 02 04:42:35 PM PDT 24 19522884 ps
T805 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3996542230 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 46489079 ps
T806 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3666798690 Aug 02 04:42:27 PM PDT 24 Aug 02 04:42:28 PM PDT 24 21765789 ps
T807 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4133609126 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:26 PM PDT 24 85841152 ps
T808 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4088502799 Aug 02 04:42:40 PM PDT 24 Aug 02 04:42:40 PM PDT 24 69609958 ps
T809 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.427334985 Aug 02 04:42:11 PM PDT 24 Aug 02 04:42:12 PM PDT 24 135418231 ps
T810 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2918778745 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:19 PM PDT 24 13033828 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.937305076 Aug 02 04:42:00 PM PDT 24 Aug 02 04:42:01 PM PDT 24 57221600 ps
T812 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.194438115 Aug 02 04:42:16 PM PDT 24 Aug 02 04:42:17 PM PDT 24 69111870 ps
T813 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2274094550 Aug 02 04:42:16 PM PDT 24 Aug 02 04:42:17 PM PDT 24 19220460 ps
T122 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3500897720 Aug 02 04:42:13 PM PDT 24 Aug 02 04:42:14 PM PDT 24 101087455 ps
T814 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3671399427 Aug 02 04:42:33 PM PDT 24 Aug 02 04:42:35 PM PDT 24 190966146 ps
T815 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2104479333 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:28 PM PDT 24 208316954 ps
T816 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1022406676 Aug 02 04:42:24 PM PDT 24 Aug 02 04:42:26 PM PDT 24 34330770 ps
T817 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1711237130 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:19 PM PDT 24 21961626 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.476497773 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 219485048 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3958687489 Aug 02 04:42:36 PM PDT 24 Aug 02 04:42:37 PM PDT 24 30407272 ps
T820 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2061567135 Aug 02 04:42:09 PM PDT 24 Aug 02 04:42:11 PM PDT 24 181997282 ps
T821 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2040570602 Aug 02 04:42:34 PM PDT 24 Aug 02 04:42:35 PM PDT 24 15952927 ps
T822 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1392428595 Aug 02 04:42:22 PM PDT 24 Aug 02 04:42:24 PM PDT 24 45942835 ps
T823 /workspace/coverage/cover_reg_top/48.gpio_intr_test.4228238400 Aug 02 04:42:34 PM PDT 24 Aug 02 04:42:35 PM PDT 24 36655283 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.459938499 Aug 02 04:42:30 PM PDT 24 Aug 02 04:42:32 PM PDT 24 100788120 ps
T825 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3925489110 Aug 02 04:42:36 PM PDT 24 Aug 02 04:42:37 PM PDT 24 42593499 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1711093355 Aug 02 04:42:00 PM PDT 24 Aug 02 04:42:01 PM PDT 24 33031399 ps
T827 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1668417341 Aug 02 04:42:17 PM PDT 24 Aug 02 04:42:18 PM PDT 24 18475810 ps
T828 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1109356976 Aug 02 04:42:30 PM PDT 24 Aug 02 04:42:31 PM PDT 24 46769915 ps
T829 /workspace/coverage/cover_reg_top/20.gpio_intr_test.917319443 Aug 02 04:42:28 PM PDT 24 Aug 02 04:42:29 PM PDT 24 55078782 ps
T830 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2015973314 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:08 PM PDT 24 17721493 ps
T831 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2415183482 Aug 02 04:42:35 PM PDT 24 Aug 02 04:42:36 PM PDT 24 15089690 ps
T832 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3038019209 Aug 02 04:42:34 PM PDT 24 Aug 02 04:42:35 PM PDT 24 36693613 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.545890774 Aug 02 04:42:25 PM PDT 24 Aug 02 04:42:26 PM PDT 24 81089909 ps
T834 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1214237005 Aug 02 04:42:27 PM PDT 24 Aug 02 04:42:28 PM PDT 24 34688594 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3537557052 Aug 02 04:42:27 PM PDT 24 Aug 02 04:42:29 PM PDT 24 258584849 ps
T123 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.717007918 Aug 02 04:42:19 PM PDT 24 Aug 02 04:42:19 PM PDT 24 41202731 ps
T836 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3683849506 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:20 PM PDT 24 370383244 ps
T837 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3729147899 Aug 02 04:42:18 PM PDT 24 Aug 02 04:42:19 PM PDT 24 44468568 ps
T838 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.428501931 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:09 PM PDT 24 148260809 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.648241386 Aug 02 04:42:08 PM PDT 24 Aug 02 04:42:11 PM PDT 24 137621363 ps
T124 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3827178742 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 28930975 ps
T840 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.57942061 Aug 02 04:41:58 PM PDT 24 Aug 02 04:41:59 PM PDT 24 15619622 ps
T841 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1674053796 Aug 02 04:42:09 PM PDT 24 Aug 02 04:42:11 PM PDT 24 153245165 ps
T842 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2071228301 Aug 02 04:42:10 PM PDT 24 Aug 02 04:42:11 PM PDT 24 130799732 ps
T843 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3228289357 Aug 02 04:42:00 PM PDT 24 Aug 02 04:42:02 PM PDT 24 574720477 ps
T844 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2232538451 Aug 02 04:42:11 PM PDT 24 Aug 02 04:42:12 PM PDT 24 155696736 ps
T845 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3087894526 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:17 PM PDT 24 72594010 ps
T846 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836261570 Aug 02 04:23:59 PM PDT 24 Aug 02 04:24:00 PM PDT 24 142921853 ps
T847 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.662709705 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:31 PM PDT 24 273118223 ps
T848 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1647122680 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:16 PM PDT 24 77117304 ps
T849 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1705514634 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:26 PM PDT 24 35756612 ps
T850 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3102456724 Aug 02 04:23:26 PM PDT 24 Aug 02 04:23:27 PM PDT 24 240215086 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3195603081 Aug 02 04:24:26 PM PDT 24 Aug 02 04:24:28 PM PDT 24 48959493 ps
T852 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3503635553 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 129528148 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4079097281 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:44 PM PDT 24 216506067 ps
T854 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405988735 Aug 02 04:23:21 PM PDT 24 Aug 02 04:23:23 PM PDT 24 116111023 ps
T855 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125630782 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:43 PM PDT 24 105797470 ps
T856 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1319789924 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:17 PM PDT 24 43460795 ps
T857 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.316680903 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:26 PM PDT 24 70156593 ps
T858 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1615447355 Aug 02 04:24:09 PM PDT 24 Aug 02 04:24:11 PM PDT 24 61556110 ps
T859 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645983819 Aug 02 04:24:08 PM PDT 24 Aug 02 04:24:09 PM PDT 24 451460681 ps
T860 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3599518642 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:26 PM PDT 24 72302126 ps
T861 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402544994 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:31 PM PDT 24 768478559 ps
T862 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.497018757 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:26 PM PDT 24 85288062 ps
T863 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17546972 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:45 PM PDT 24 118409060 ps
T864 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.6766605 Aug 02 04:23:58 PM PDT 24 Aug 02 04:24:00 PM PDT 24 239846204 ps
T865 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2744159908 Aug 02 04:24:45 PM PDT 24 Aug 02 04:24:46 PM PDT 24 70842066 ps
T866 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.72496810 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:30 PM PDT 24 57809633 ps
T867 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123048161 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 58084884 ps
T868 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.329317255 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:42 PM PDT 24 44154752 ps
T869 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4171143821 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:17 PM PDT 24 173525348 ps
T870 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206941726 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:26 PM PDT 24 57223748 ps
T871 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2782984865 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:30 PM PDT 24 324632833 ps
T872 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2224587862 Aug 02 04:23:21 PM PDT 24 Aug 02 04:23:23 PM PDT 24 60570668 ps
T873 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2409867211 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:31 PM PDT 24 42013119 ps
T874 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2030214736 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:31 PM PDT 24 71556534 ps
T875 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787248200 Aug 02 04:24:20 PM PDT 24 Aug 02 04:24:21 PM PDT 24 319198547 ps
T876 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3197537498 Aug 02 04:24:46 PM PDT 24 Aug 02 04:24:47 PM PDT 24 72233869 ps
T877 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.830982528 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:26 PM PDT 24 53455496 ps
T878 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1982885804 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:46 PM PDT 24 63885582 ps
T879 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2266246879 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:27 PM PDT 24 168530811 ps
T880 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.5838399 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:27 PM PDT 24 132796154 ps
T881 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2847466844 Aug 02 04:24:46 PM PDT 24 Aug 02 04:24:47 PM PDT 24 61937284 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484606902 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:30 PM PDT 24 40763940 ps
T883 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4214038381 Aug 02 04:24:01 PM PDT 24 Aug 02 04:24:02 PM PDT 24 107967756 ps
T884 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2992059680 Aug 02 04:23:36 PM PDT 24 Aug 02 04:23:37 PM PDT 24 133121873 ps
T885 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.239701881 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:44 PM PDT 24 65171023 ps
T886 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3690243596 Aug 02 04:25:18 PM PDT 24 Aug 02 04:25:19 PM PDT 24 197830099 ps
T887 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2275027118 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:42 PM PDT 24 122432963 ps
T888 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618604142 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:42 PM PDT 24 25200402 ps
T889 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3730410530 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:31 PM PDT 24 159227300 ps
T890 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.562561478 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:44 PM PDT 24 66578190 ps
T891 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.472758959 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:44 PM PDT 24 47777603 ps
T892 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3532746983 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:26 PM PDT 24 62740759 ps
T893 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1386548179 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:17 PM PDT 24 47724966 ps
T894 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1171836862 Aug 02 04:24:13 PM PDT 24 Aug 02 04:24:15 PM PDT 24 513036036 ps
T895 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122380304 Aug 02 04:23:22 PM PDT 24 Aug 02 04:23:23 PM PDT 24 50788637 ps
T896 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3665815468 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:44 PM PDT 24 304170849 ps
T897 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1116926975 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:27 PM PDT 24 115990325 ps
T898 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1514112109 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:43 PM PDT 24 184080209 ps
T899 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156163475 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:44 PM PDT 24 51549145 ps
T900 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.240035211 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:32 PM PDT 24 412950767 ps
T901 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1825157056 Aug 02 04:24:11 PM PDT 24 Aug 02 04:24:12 PM PDT 24 69615044 ps
T902 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.301817561 Aug 02 04:23:37 PM PDT 24 Aug 02 04:23:38 PM PDT 24 135791845 ps
T903 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.758417759 Aug 02 04:24:42 PM PDT 24 Aug 02 04:24:43 PM PDT 24 64900036 ps
T904 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3373052390 Aug 02 04:23:59 PM PDT 24 Aug 02 04:24:00 PM PDT 24 120062621 ps
T905 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750460846 Aug 02 04:24:26 PM PDT 24 Aug 02 04:24:27 PM PDT 24 57099107 ps
T906 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.200345532 Aug 02 04:24:41 PM PDT 24 Aug 02 04:24:42 PM PDT 24 183502817 ps
T907 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3857408007 Aug 02 04:23:23 PM PDT 24 Aug 02 04:23:24 PM PDT 24 699173631 ps
T908 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1536555694 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:16 PM PDT 24 32328239 ps
T909 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.662736621 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:44 PM PDT 24 230431581 ps
T910 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3092920568 Aug 02 04:24:43 PM PDT 24 Aug 02 04:24:44 PM PDT 24 54552099 ps
T911 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2884068029 Aug 02 04:24:30 PM PDT 24 Aug 02 04:24:31 PM PDT 24 49970046 ps
T912 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4268877827 Aug 02 04:23:27 PM PDT 24 Aug 02 04:23:28 PM PDT 24 98005769 ps
T913 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2957811612 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:26 PM PDT 24 91815628 ps
T914 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2096461963 Aug 02 04:23:28 PM PDT 24 Aug 02 04:23:29 PM PDT 24 53920496 ps
T915 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4130394938 Aug 02 04:25:18 PM PDT 24 Aug 02 04:25:19 PM PDT 24 42802432 ps
T916 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4038014565 Aug 02 04:23:22 PM PDT 24 Aug 02 04:23:23 PM PDT 24 111299882 ps
T917 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1938854692 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:45 PM PDT 24 77308290 ps
T918 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1794073787 Aug 02 04:23:21 PM PDT 24 Aug 02 04:23:23 PM PDT 24 172189763 ps
T919 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3792474160 Aug 02 04:24:27 PM PDT 24 Aug 02 04:24:28 PM PDT 24 114833987 ps
T920 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1625357812 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:17 PM PDT 24 143209032 ps
T921 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2516671490 Aug 02 04:24:55 PM PDT 24 Aug 02 04:24:56 PM PDT 24 107504819 ps
T922 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1037267268 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:17 PM PDT 24 63748031 ps
T923 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1616670306 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:31 PM PDT 24 25397439 ps
T924 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1353864345 Aug 02 04:24:24 PM PDT 24 Aug 02 04:24:25 PM PDT 24 42126142 ps
T925 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2022959728 Aug 02 04:24:45 PM PDT 24 Aug 02 04:24:46 PM PDT 24 222270279 ps
T926 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.148539988 Aug 02 04:25:02 PM PDT 24 Aug 02 04:25:05 PM PDT 24 42937111 ps
T927 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1295563109 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:17 PM PDT 24 133599159 ps
T928 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1164268345 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:25 PM PDT 24 451915131 ps
T929 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.681434774 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:30 PM PDT 24 59717463 ps
T930 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3801189804 Aug 02 04:23:22 PM PDT 24 Aug 02 04:23:23 PM PDT 24 106923210 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3287807460 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:31 PM PDT 24 168523288 ps
T932 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2467747860 Aug 02 04:24:25 PM PDT 24 Aug 02 04:24:26 PM PDT 24 260103424 ps
T933 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.955173215 Aug 02 04:23:11 PM PDT 24 Aug 02 04:23:13 PM PDT 24 403567720 ps
T934 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644694698 Aug 02 04:23:15 PM PDT 24 Aug 02 04:23:17 PM PDT 24 39703043 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211004478 Aug 02 04:24:44 PM PDT 24 Aug 02 04:24:45 PM PDT 24 95607579 ps
T936 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509828224 Aug 02 04:23:58 PM PDT 24 Aug 02 04:23:59 PM PDT 24 157200988 ps
T937 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2231189707 Aug 02 04:24:27 PM PDT 24 Aug 02 04:24:28 PM PDT 24 219497250 ps
T938 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021260113 Aug 02 04:24:28 PM PDT 24 Aug 02 04:24:30 PM PDT 24 360193719 ps
T939 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3628619294 Aug 02 04:23:24 PM PDT 24 Aug 02 04:23:26 PM PDT 24 48647904 ps
T940 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3285050902 Aug 02 04:23:25 PM PDT 24 Aug 02 04:23:27 PM PDT 24 295089828 ps
T941 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4105291212 Aug 02 04:24:29 PM PDT 24 Aug 02 04:24:30 PM PDT 24 58472523 ps
T942 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080662905 Aug 02 04:23:16 PM PDT 24 Aug 02 04:23:22 PM PDT 24 105539873 ps
T943 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.243569847 Aug 02 04:25:17 PM PDT 24 Aug 02 04:25:18 PM PDT 24 108829086 ps
T944 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3014236040 Aug 02 04:25:18 PM PDT 24 Aug 02 04:25:19 PM PDT 24 16256482 ps

Test location /workspace/coverage/default/36.gpio_full_random.3907828041
Short name T37
Test name
Test status
Simulation time 102204554 ps
CPU time 1 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198268 kb
Host smart-0b2ad8b1-e4e3-433f-83b0-eae14eb83f06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907828041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3907828041
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.961334769
Short name T154
Test name
Test status
Simulation time 61901804 ps
CPU time 2.22 seconds
Started Aug 02 04:47:50 PM PDT 24
Finished Aug 02 04:47:53 PM PDT 24
Peak memory 198552 kb
Host smart-6d84a1cb-3dc3-4e66-8db1-8bea86a89aee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961334769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.961334769
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2391445169
Short name T80
Test name
Test status
Simulation time 81765045231 ps
CPU time 1985.86 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 198816 kb
Host smart-ed24c539-977e-42be-83c1-87eee9ca4368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2391445169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2391445169
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1463483946
Short name T1
Test name
Test status
Simulation time 656099386 ps
CPU time 2.04 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 198364 kb
Host smart-1a394f4c-7c03-4f01-bdd8-c2cdb343cf51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463483946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1463483946
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.724711786
Short name T49
Test name
Test status
Simulation time 156826905 ps
CPU time 1.41 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198664 kb
Host smart-cfcb6e5a-6e2c-4778-a5d3-80a9a50f6317
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724711786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.724711786
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1157660809
Short name T55
Test name
Test status
Simulation time 17652858 ps
CPU time 0.55 seconds
Started Aug 02 04:49:07 PM PDT 24
Finished Aug 02 04:49:08 PM PDT 24
Peak memory 194372 kb
Host smart-3420ae0e-f541-4902-8d21-3a043723f33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157660809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1157660809
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3263265775
Short name T158
Test name
Test status
Simulation time 75298174 ps
CPU time 0.9 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 197272 kb
Host smart-2e208612-7194-4027-8b65-c2b6f40b2e08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263265775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3263265775
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.811497602
Short name T51
Test name
Test status
Simulation time 438741158 ps
CPU time 0.86 seconds
Started Aug 02 04:47:12 PM PDT 24
Finished Aug 02 04:47:13 PM PDT 24
Peak memory 214232 kb
Host smart-c83ebd7c-ec86-47dc-af83-45c1d6ff5bdc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811497602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.811497602
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.477646185
Short name T103
Test name
Test status
Simulation time 97422387 ps
CPU time 0.85 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 197224 kb
Host smart-43631f3f-8eff-4204-af0b-c18e0463ce5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477646185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.477646185
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3925009403
Short name T137
Test name
Test status
Simulation time 131853404 ps
CPU time 0.74 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:02 PM PDT 24
Peak memory 197544 kb
Host smart-be1fa5dd-66c9-4c42-ab1b-1403a65acbff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925009403 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3925009403
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.815202779
Short name T59
Test name
Test status
Simulation time 189674161 ps
CPU time 1.41 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 198660 kb
Host smart-395f6626-22f3-4285-a290-afa69923b56b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815202779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.815202779
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.732269182
Short name T22
Test name
Test status
Simulation time 96592725 ps
CPU time 1.37 seconds
Started Aug 02 04:47:10 PM PDT 24
Finished Aug 02 04:47:11 PM PDT 24
Peak memory 197476 kb
Host smart-8a7140b8-0b71-43a8-b55e-4652ec8218bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732269182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.732269182
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3228289357
Short name T843
Test name
Test status
Simulation time 574720477 ps
CPU time 2.45 seconds
Started Aug 02 04:42:00 PM PDT 24
Finished Aug 02 04:42:02 PM PDT 24
Peak memory 197788 kb
Host smart-ae6fdd62-f6ec-4bc9-b3fc-423492b2d230
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228289357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3228289357
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3153793227
Short name T731
Test name
Test status
Simulation time 149070599 ps
CPU time 0.64 seconds
Started Aug 02 04:41:57 PM PDT 24
Finished Aug 02 04:41:58 PM PDT 24
Peak memory 195320 kb
Host smart-636f6728-9f19-4c61-a2e5-3d7e17f78225
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153793227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3153793227
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1711093355
Short name T826
Test name
Test status
Simulation time 33031399 ps
CPU time 1.37 seconds
Started Aug 02 04:42:00 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 198612 kb
Host smart-a38fe126-1a16-4482-ad27-87c01cd477ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711093355 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1711093355
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2662119464
Short name T737
Test name
Test status
Simulation time 25309673 ps
CPU time 0.66 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:02 PM PDT 24
Peak memory 195236 kb
Host smart-a0f34f27-e2c0-46d9-aa06-5043cf5f1cb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662119464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2662119464
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3012418192
Short name T779
Test name
Test status
Simulation time 38616153 ps
CPU time 0.59 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 194300 kb
Host smart-01811832-9381-4b18-b7f4-a1fedf8d0c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012418192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3012418192
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2427043310
Short name T762
Test name
Test status
Simulation time 46641962 ps
CPU time 0.78 seconds
Started Aug 02 04:42:00 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 196680 kb
Host smart-06181d8e-aa73-4b3c-bacb-4df9c720384c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427043310 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2427043310
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2393113137
Short name T732
Test name
Test status
Simulation time 56291895 ps
CPU time 2.77 seconds
Started Aug 02 04:42:00 PM PDT 24
Finished Aug 02 04:42:03 PM PDT 24
Peak memory 198644 kb
Host smart-b692457f-c365-4f01-ae2e-454180ced8a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393113137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2393113137
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3647438961
Short name T119
Test name
Test status
Simulation time 213444227 ps
CPU time 0.81 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:02 PM PDT 24
Peak memory 196464 kb
Host smart-bd96818a-a79b-46d9-83c5-1a995736ba33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647438961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3647438961
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3613422702
Short name T773
Test name
Test status
Simulation time 61500276 ps
CPU time 1.44 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 198584 kb
Host smart-eece62ad-35c7-4e89-b1bf-fe3a4c2454df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613422702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3613422702
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3827178742
Short name T124
Test name
Test status
Simulation time 28930975 ps
CPU time 0.61 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 195536 kb
Host smart-b83b659e-eda1-4095-8b6c-933687ca9c49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827178742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3827178742
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.937305076
Short name T811
Test name
Test status
Simulation time 57221600 ps
CPU time 0.92 seconds
Started Aug 02 04:42:00 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 193332 kb
Host smart-b60702f3-ba1e-4223-8e30-1081fae8bdd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937305076 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.937305076
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.57942061
Short name T840
Test name
Test status
Simulation time 15619622 ps
CPU time 0.61 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 195320 kb
Host smart-e31b7857-d967-4c27-a10e-d00bd6bc3c50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57942061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_c
sr_rw.57942061
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3669050655
Short name T759
Test name
Test status
Simulation time 70477800 ps
CPU time 0.58 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:41:58 PM PDT 24
Peak memory 194352 kb
Host smart-a0066cc8-7fc8-4602-8a7f-878ce70508b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669050655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3669050655
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.484147505
Short name T739
Test name
Test status
Simulation time 446466706 ps
CPU time 1.98 seconds
Started Aug 02 04:42:01 PM PDT 24
Finished Aug 02 04:42:03 PM PDT 24
Peak memory 198828 kb
Host smart-e11fe47d-716a-4387-9172-638c5d9fc916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484147505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.484147505
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.507016269
Short name T788
Test name
Test status
Simulation time 77309705 ps
CPU time 1.12 seconds
Started Aug 02 04:41:58 PM PDT 24
Finished Aug 02 04:42:00 PM PDT 24
Peak memory 198652 kb
Host smart-2fab91fa-b46e-4986-8c0d-ca9b0e85775c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507016269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.507016269
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2274094550
Short name T813
Test name
Test status
Simulation time 19220460 ps
CPU time 0.73 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 198548 kb
Host smart-471a218a-146e-409f-90ad-7c27c20d6590
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274094550 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2274094550
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1668417341
Short name T827
Test name
Test status
Simulation time 18475810 ps
CPU time 0.57 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 194540 kb
Host smart-6a5e92c0-60c7-47d7-b99e-923aba1af398
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668417341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1668417341
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3729147899
Short name T837
Test name
Test status
Simulation time 44468568 ps
CPU time 0.6 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 194396 kb
Host smart-5ce7bf60-fc9c-4f79-ba3e-6ee6082a2b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729147899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3729147899
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3212148492
Short name T141
Test name
Test status
Simulation time 35101724 ps
CPU time 0.66 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 195020 kb
Host smart-a5035f1f-0b57-47ed-9abe-fc6b076e7885
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212148492 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3212148492
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1392428595
Short name T822
Test name
Test status
Simulation time 45942835 ps
CPU time 2.33 seconds
Started Aug 02 04:42:22 PM PDT 24
Finished Aug 02 04:42:24 PM PDT 24
Peak memory 198644 kb
Host smart-4a14bf0d-aab0-42f4-a71a-31ce633b2da6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392428595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1392428595
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1614558311
Short name T781
Test name
Test status
Simulation time 290296583 ps
CPU time 1.1 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198616 kb
Host smart-1b647434-077e-4dd3-8b11-1d313830a770
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614558311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1614558311
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1657732552
Short name T720
Test name
Test status
Simulation time 39805152 ps
CPU time 0.95 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 198480 kb
Host smart-c2c7491d-e756-4031-b140-f65c4418a9a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657732552 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1657732552
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3851585351
Short name T774
Test name
Test status
Simulation time 25926757 ps
CPU time 0.58 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 193968 kb
Host smart-af585463-7ccd-4b63-bb50-619334ebe43e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851585351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3851585351
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2918778745
Short name T810
Test name
Test status
Simulation time 13033828 ps
CPU time 0.59 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 194344 kb
Host smart-1fac24ca-b472-4b0e-86e6-a6d1972dccc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918778745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2918778745
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1432361951
Short name T105
Test name
Test status
Simulation time 127429040 ps
CPU time 0.76 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 196680 kb
Host smart-01497022-d3e5-4aba-a601-33d2694bb426
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432361951 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1432361951
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1711237130
Short name T817
Test name
Test status
Simulation time 21961626 ps
CPU time 1.23 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 198648 kb
Host smart-f98c0bc3-0fce-47bc-b1dd-9a330eb4bbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711237130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1711237130
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.644970003
Short name T61
Test name
Test status
Simulation time 214111521 ps
CPU time 1.43 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198600 kb
Host smart-888d6d74-165e-4afc-b409-5ef106093c62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644970003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.644970003
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3228086405
Short name T789
Test name
Test status
Simulation time 191831349 ps
CPU time 0.93 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198432 kb
Host smart-2fb90636-0058-4cde-b976-42a18d6e8f1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228086405 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3228086405
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3793552742
Short name T760
Test name
Test status
Simulation time 15053825 ps
CPU time 0.62 seconds
Started Aug 02 04:42:20 PM PDT 24
Finished Aug 02 04:42:21 PM PDT 24
Peak memory 195604 kb
Host smart-4e4151e9-1b87-45ad-b207-861c66b439b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793552742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3793552742
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2493126426
Short name T772
Test name
Test status
Simulation time 21725890 ps
CPU time 0.61 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 194968 kb
Host smart-4f7be42c-09a6-4371-a2ad-42714f8a5b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493126426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2493126426
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2246424212
Short name T769
Test name
Test status
Simulation time 99574541 ps
CPU time 0.77 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 197292 kb
Host smart-ab0f42d4-4cba-4e2a-8e0d-e7090b3bd8bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246424212 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2246424212
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2873808973
Short name T756
Test name
Test status
Simulation time 58838265 ps
CPU time 1.42 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198652 kb
Host smart-f1328d31-1014-4f23-a391-2dc7d83ca730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873808973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2873808973
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3982858716
Short name T714
Test name
Test status
Simulation time 59714878 ps
CPU time 1.35 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198724 kb
Host smart-95af36d9-181a-4f36-a733-9e519eda2f0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982858716 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3982858716
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2931356594
Short name T765
Test name
Test status
Simulation time 29070221 ps
CPU time 0.61 seconds
Started Aug 02 04:42:22 PM PDT 24
Finished Aug 02 04:42:23 PM PDT 24
Peak memory 195220 kb
Host smart-dc25567a-e1e2-4a1c-9b23-b9ff714742dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931356594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2931356594
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.832390301
Short name T744
Test name
Test status
Simulation time 42234278 ps
CPU time 0.62 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 195044 kb
Host smart-06ce69f6-4e12-4c20-99f4-08a918568bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832390301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.832390301
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1340704341
Short name T798
Test name
Test status
Simulation time 50826183 ps
CPU time 0.64 seconds
Started Aug 02 04:42:15 PM PDT 24
Finished Aug 02 04:42:15 PM PDT 24
Peak memory 194976 kb
Host smart-53ff70db-e7da-4d12-a052-fdba945c7df2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340704341 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1340704341
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3858412746
Short name T775
Test name
Test status
Simulation time 537149630 ps
CPU time 2.4 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198616 kb
Host smart-a061802f-bcc2-4fad-ba32-d1043d1d64e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858412746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3858412746
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1396443939
Short name T767
Test name
Test status
Simulation time 206445813 ps
CPU time 0.87 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 198428 kb
Host smart-df16b814-f381-45ab-b035-da6870175605
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396443939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1396443939
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.545890774
Short name T833
Test name
Test status
Simulation time 81089909 ps
CPU time 1.02 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 198576 kb
Host smart-3e327a38-c165-4b8f-847e-8ba7cc18a76f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545890774 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.545890774
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3848497371
Short name T120
Test name
Test status
Simulation time 52928983 ps
CPU time 0.63 seconds
Started Aug 02 04:42:21 PM PDT 24
Finished Aug 02 04:42:22 PM PDT 24
Peak memory 195400 kb
Host smart-7c32ebe3-382f-488d-b6e8-b91dbe0e6f5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848497371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3848497371
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2036069283
Short name T718
Test name
Test status
Simulation time 18323694 ps
CPU time 0.57 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 194336 kb
Host smart-87e471ef-05f8-4473-a044-e36b6af40003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036069283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2036069283
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2121960712
Short name T140
Test name
Test status
Simulation time 98928998 ps
CPU time 0.74 seconds
Started Aug 02 04:42:24 PM PDT 24
Finished Aug 02 04:42:25 PM PDT 24
Peak memory 196724 kb
Host smart-a2b8750a-6cfd-4c09-923d-ff3e3ae725f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121960712 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2121960712
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3537557052
Short name T835
Test name
Test status
Simulation time 258584849 ps
CPU time 2.25 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:29 PM PDT 24
Peak memory 198616 kb
Host smart-dc7403af-c435-48a1-ae9a-982e46637fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537557052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3537557052
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.747141741
Short name T790
Test name
Test status
Simulation time 91581695 ps
CPU time 0.86 seconds
Started Aug 02 04:42:24 PM PDT 24
Finished Aug 02 04:42:25 PM PDT 24
Peak memory 198368 kb
Host smart-ee34ed21-f3e1-4706-af9d-d458574e6614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747141741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.747141741
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1022406676
Short name T816
Test name
Test status
Simulation time 34330770 ps
CPU time 1.61 seconds
Started Aug 02 04:42:24 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 198700 kb
Host smart-4c2814cb-a86f-4a64-80b4-78905f943403
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022406676 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1022406676
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1565579025
Short name T753
Test name
Test status
Simulation time 43063119 ps
CPU time 0.63 seconds
Started Aug 02 04:42:32 PM PDT 24
Finished Aug 02 04:42:32 PM PDT 24
Peak memory 195388 kb
Host smart-7a851fd9-ba25-4305-b36d-71852e5b96a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565579025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1565579025
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.869040882
Short name T777
Test name
Test status
Simulation time 61461340 ps
CPU time 0.58 seconds
Started Aug 02 04:42:28 PM PDT 24
Finished Aug 02 04:42:29 PM PDT 24
Peak memory 193592 kb
Host smart-f4a5e3ff-ac5b-40e5-a5be-6b36dcc3ad78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869040882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.869040882
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4133609126
Short name T807
Test name
Test status
Simulation time 85841152 ps
CPU time 0.61 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 195244 kb
Host smart-901edb66-0936-4c55-af47-ae4caeccb468
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133609126 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4133609126
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3671399427
Short name T814
Test name
Test status
Simulation time 190966146 ps
CPU time 1.97 seconds
Started Aug 02 04:42:33 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 198672 kb
Host smart-f60be4e7-3864-4ad4-9b3d-5cb47643a662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671399427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3671399427
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2157920054
Short name T785
Test name
Test status
Simulation time 51150883 ps
CPU time 0.91 seconds
Started Aug 02 04:42:22 PM PDT 24
Finished Aug 02 04:42:23 PM PDT 24
Peak memory 197496 kb
Host smart-529c3662-501b-4c53-9027-92067cf8e460
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157920054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2157920054
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.236034314
Short name T723
Test name
Test status
Simulation time 52207959 ps
CPU time 0.99 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 198496 kb
Host smart-1c7735a1-5a4c-4663-be4c-1206ad31db8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236034314 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.236034314
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2125919408
Short name T754
Test name
Test status
Simulation time 11578001 ps
CPU time 0.57 seconds
Started Aug 02 04:42:26 PM PDT 24
Finished Aug 02 04:42:27 PM PDT 24
Peak memory 193860 kb
Host smart-8241e563-5470-49b7-a27e-a7b7eb3b5a2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125919408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2125919408
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2235595910
Short name T748
Test name
Test status
Simulation time 63448772 ps
CPU time 0.62 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:31 PM PDT 24
Peak memory 195068 kb
Host smart-411cbfb6-4a0f-4ad1-8fbe-8d8968b17124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235595910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2235595910
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3181142709
Short name T107
Test name
Test status
Simulation time 18147398 ps
CPU time 0.64 seconds
Started Aug 02 04:42:28 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 195360 kb
Host smart-cfeb4bfc-f8cb-42f5-93c0-7710c4cc652d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181142709 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3181142709
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1149296900
Short name T750
Test name
Test status
Simulation time 36405123 ps
CPU time 1.8 seconds
Started Aug 02 04:42:28 PM PDT 24
Finished Aug 02 04:42:30 PM PDT 24
Peak memory 198200 kb
Host smart-58a9987b-b503-41ea-a9a5-249872ec18ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149296900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1149296900
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3395966844
Short name T50
Test name
Test status
Simulation time 311409105 ps
CPU time 1.09 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 198652 kb
Host smart-2ca6a416-9ceb-47b0-89d6-62b00b9c95e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395966844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3395966844
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2478661575
Short name T766
Test name
Test status
Simulation time 24710426 ps
CPU time 1.16 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:31 PM PDT 24
Peak memory 198764 kb
Host smart-e4e4e794-e82c-4075-8a5d-a5e59b3bda0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478661575 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2478661575
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4285181936
Short name T741
Test name
Test status
Simulation time 14538549 ps
CPU time 0.58 seconds
Started Aug 02 04:42:26 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 195216 kb
Host smart-03331243-3f06-49c1-ad36-94ac5b6e89c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285181936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4285181936
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2884847883
Short name T783
Test name
Test status
Simulation time 14513273 ps
CPU time 0.62 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 194588 kb
Host smart-9ac8db2d-0fde-486e-8154-16c48b282846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884847883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2884847883
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2232044108
Short name T778
Test name
Test status
Simulation time 18325777 ps
CPU time 0.71 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 197216 kb
Host smart-b0dbf965-6401-47cc-9458-66484f463583
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232044108 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2232044108
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3145198267
Short name T791
Test name
Test status
Simulation time 87264368 ps
CPU time 1.38 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:27 PM PDT 24
Peak memory 198616 kb
Host smart-66547396-ea2d-4b50-bec4-88dfe6ab5d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145198267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3145198267
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.459938499
Short name T824
Test name
Test status
Simulation time 100788120 ps
CPU time 1.41 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:32 PM PDT 24
Peak memory 198592 kb
Host smart-ae662e3e-869c-4f14-807c-1ce3013b692a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459938499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.459938499
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3958687489
Short name T819
Test name
Test status
Simulation time 30407272 ps
CPU time 0.65 seconds
Started Aug 02 04:42:36 PM PDT 24
Finished Aug 02 04:42:37 PM PDT 24
Peak memory 197744 kb
Host smart-ad568b5b-9b2c-41eb-9583-574bf47ad11c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958687489 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3958687489
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1214237005
Short name T834
Test name
Test status
Simulation time 34688594 ps
CPU time 0.6 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 195328 kb
Host smart-4e14262b-874f-4512-afa9-32f3e795af93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214237005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1214237005
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4252645397
Short name T726
Test name
Test status
Simulation time 12204013 ps
CPU time 0.62 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:31 PM PDT 24
Peak memory 194368 kb
Host smart-b514da39-61cb-4da9-a8a5-759bcea4fa02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252645397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4252645397
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1473414292
Short name T761
Test name
Test status
Simulation time 16887902 ps
CPU time 0.64 seconds
Started Aug 02 04:42:24 PM PDT 24
Finished Aug 02 04:42:25 PM PDT 24
Peak memory 195984 kb
Host smart-81a3b255-9b2e-4678-b9f1-da7b068049fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473414292 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1473414292
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1247714274
Short name T784
Test name
Test status
Simulation time 2354124895 ps
CPU time 2.61 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:33 PM PDT 24
Peak memory 198760 kb
Host smart-55a4261a-36bf-4aaa-9a21-ade42d93ef24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247714274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1247714274
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1936252739
Short name T796
Test name
Test status
Simulation time 277010426 ps
CPU time 1.09 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:27 PM PDT 24
Peak memory 198604 kb
Host smart-430fb31c-0a7d-455c-b060-2584f4a26d64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936252739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1936252739
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.843745148
Short name T786
Test name
Test status
Simulation time 24411748 ps
CPU time 1.05 seconds
Started Aug 02 04:42:28 PM PDT 24
Finished Aug 02 04:42:29 PM PDT 24
Peak memory 198188 kb
Host smart-dd29ccf7-4ce6-4739-9cb7-a73abf6d90b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843745148 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.843745148
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4003642601
Short name T736
Test name
Test status
Simulation time 11382806 ps
CPU time 0.57 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 194992 kb
Host smart-bc186503-ecd2-4aba-a290-37d37ff5163e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003642601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4003642601
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1109356976
Short name T828
Test name
Test status
Simulation time 46769915 ps
CPU time 0.55 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:31 PM PDT 24
Peak memory 194412 kb
Host smart-8ef9b60e-f11e-419a-b1ca-ff4545908490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109356976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1109356976
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1775666885
Short name T134
Test name
Test status
Simulation time 20324801 ps
CPU time 0.77 seconds
Started Aug 02 04:42:29 PM PDT 24
Finished Aug 02 04:42:30 PM PDT 24
Peak memory 197384 kb
Host smart-875207f7-cda2-4d1b-859b-addef209e480
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775666885 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1775666885
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2104479333
Short name T815
Test name
Test status
Simulation time 208316954 ps
CPU time 2.29 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 198692 kb
Host smart-4857e6ef-39e9-479b-93a9-9e729672cdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104479333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2104479333
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3528612531
Short name T62
Test name
Test status
Simulation time 70274538 ps
CPU time 1.09 seconds
Started Aug 02 04:42:24 PM PDT 24
Finished Aug 02 04:42:25 PM PDT 24
Peak memory 198628 kb
Host smart-8b533261-69f0-4613-a361-e81174b00329
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528612531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3528612531
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.584953771
Short name T121
Test name
Test status
Simulation time 69923654 ps
CPU time 0.76 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 195764 kb
Host smart-e67c6342-ea0e-402e-b22e-948587bb85b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584953771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.584953771
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2061567135
Short name T820
Test name
Test status
Simulation time 181997282 ps
CPU time 1.41 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 197028 kb
Host smart-76e6f431-d8f6-415c-a3ed-c102867dc8f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061567135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2061567135
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2382373614
Short name T793
Test name
Test status
Simulation time 52394967 ps
CPU time 0.65 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 195896 kb
Host smart-57bd854f-f6d4-4ebf-a1cd-ef58889099e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382373614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2382373614
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1671011201
Short name T802
Test name
Test status
Simulation time 130188614 ps
CPU time 0.86 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 198520 kb
Host smart-cb81b1fb-98c2-49bd-b481-79743a15a06f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671011201 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1671011201
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3409858966
Short name T102
Test name
Test status
Simulation time 12842635 ps
CPU time 0.63 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 195292 kb
Host smart-4d937d97-8612-479b-85bd-7a0629f5679a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409858966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3409858966
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1024648662
Short name T745
Test name
Test status
Simulation time 20786275 ps
CPU time 0.6 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 194320 kb
Host smart-e31da212-c9cc-4df0-8a84-691aab77b6c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024648662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1024648662
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1147426357
Short name T135
Test name
Test status
Simulation time 58041941 ps
CPU time 0.73 seconds
Started Aug 02 04:42:06 PM PDT 24
Finished Aug 02 04:42:07 PM PDT 24
Peak memory 196564 kb
Host smart-46b8f29c-8283-4d18-a0ae-b425fb2b9667
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147426357 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1147426357
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1674053796
Short name T841
Test name
Test status
Simulation time 153245165 ps
CPU time 1.8 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 198652 kb
Host smart-774921a5-dfca-4459-89f6-881507dbdd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674053796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1674053796
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1897873191
Short name T58
Test name
Test status
Simulation time 70783258 ps
CPU time 1.12 seconds
Started Aug 02 04:42:06 PM PDT 24
Finished Aug 02 04:42:08 PM PDT 24
Peak memory 198248 kb
Host smart-2149f2a5-14bf-4043-9793-9edc76fb17e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897873191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1897873191
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.917319443
Short name T829
Test name
Test status
Simulation time 55078782 ps
CPU time 0.61 seconds
Started Aug 02 04:42:28 PM PDT 24
Finished Aug 02 04:42:29 PM PDT 24
Peak memory 194268 kb
Host smart-cf40a1b3-3393-4de8-93d9-7b416cd5c4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917319443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.917319443
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.728294447
Short name T780
Test name
Test status
Simulation time 66773695 ps
CPU time 0.61 seconds
Started Aug 02 04:42:30 PM PDT 24
Finished Aug 02 04:42:30 PM PDT 24
Peak memory 194352 kb
Host smart-c3a9782a-875f-4df5-b80b-233c4a9b0675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728294447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.728294447
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2688780954
Short name T746
Test name
Test status
Simulation time 59821220 ps
CPU time 0.6 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 194464 kb
Host smart-aa9a903b-92ac-4e38-a444-200a474b9617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688780954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2688780954
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.45404032
Short name T721
Test name
Test status
Simulation time 48567409 ps
CPU time 0.64 seconds
Started Aug 02 04:42:32 PM PDT 24
Finished Aug 02 04:42:32 PM PDT 24
Peak memory 194296 kb
Host smart-c7c2a66c-7c9d-4e50-83e0-329cafe4854f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45404032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.45404032
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3553745116
Short name T801
Test name
Test status
Simulation time 18015166 ps
CPU time 0.62 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:25 PM PDT 24
Peak memory 195060 kb
Host smart-ed129536-dde4-4557-9444-993abf99148d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553745116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3553745116
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3666798690
Short name T806
Test name
Test status
Simulation time 21765789 ps
CPU time 0.58 seconds
Started Aug 02 04:42:27 PM PDT 24
Finished Aug 02 04:42:28 PM PDT 24
Peak memory 194300 kb
Host smart-12bef66c-de48-4fa4-8612-7cb757171b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666798690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3666798690
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2730123232
Short name T757
Test name
Test status
Simulation time 12721463 ps
CPU time 0.62 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 195084 kb
Host smart-ec889940-1a95-487c-a30f-acdd04fe3802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730123232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2730123232
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3178994363
Short name T722
Test name
Test status
Simulation time 28852129 ps
CPU time 0.61 seconds
Started Aug 02 04:42:25 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 195116 kb
Host smart-5105220a-ec1d-4a59-9f41-991f10716fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178994363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3178994363
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3088032541
Short name T752
Test name
Test status
Simulation time 17178223 ps
CPU time 0.59 seconds
Started Aug 02 04:42:36 PM PDT 24
Finished Aug 02 04:42:36 PM PDT 24
Peak memory 194416 kb
Host smart-6d8c7a11-1222-4bae-bacb-34b26aeded89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088032541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3088032541
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4088502799
Short name T808
Test name
Test status
Simulation time 69609958 ps
CPU time 0.61 seconds
Started Aug 02 04:42:40 PM PDT 24
Finished Aug 02 04:42:40 PM PDT 24
Peak memory 194420 kb
Host smart-94b60ba9-5bdb-4650-b604-e41b5b7ece18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088502799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4088502799
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3500897720
Short name T122
Test name
Test status
Simulation time 101087455 ps
CPU time 0.74 seconds
Started Aug 02 04:42:13 PM PDT 24
Finished Aug 02 04:42:14 PM PDT 24
Peak memory 196976 kb
Host smart-be0b6b51-7296-4959-ae72-e2ceb9e244d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500897720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3500897720
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.500256446
Short name T117
Test name
Test status
Simulation time 132561439 ps
CPU time 2.14 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 197256 kb
Host smart-d2e26d33-e508-4fa7-b701-c66ca400bc57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500256446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.500256446
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2015973314
Short name T830
Test name
Test status
Simulation time 17721493 ps
CPU time 0.65 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:08 PM PDT 24
Peak memory 195424 kb
Host smart-a8979aa8-676b-42cf-93f0-7f779fc5b261
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015973314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2015973314
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4115996343
Short name T740
Test name
Test status
Simulation time 43984894 ps
CPU time 1.18 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 198652 kb
Host smart-248c7efd-e817-49e6-9777-2a6b722f9b64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115996343 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4115996343
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1395791863
Short name T799
Test name
Test status
Simulation time 40687897 ps
CPU time 0.6 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 194968 kb
Host smart-7944b444-822c-4c0b-93a4-c3a148f1bf5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395791863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1395791863
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.838535201
Short name T749
Test name
Test status
Simulation time 37087420 ps
CPU time 0.63 seconds
Started Aug 02 04:42:10 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 194376 kb
Host smart-7403cd6c-0fed-42d9-8e43-17b5c92f8b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838535201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.838535201
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.71096681
Short name T758
Test name
Test status
Simulation time 17791970 ps
CPU time 0.81 seconds
Started Aug 02 04:42:14 PM PDT 24
Finished Aug 02 04:42:15 PM PDT 24
Peak memory 197448 kb
Host smart-56edb4a5-9768-4cc5-b051-6d84f9203b6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71096681 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.gpio_same_csr_outstanding.71096681
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2551257679
Short name T729
Test name
Test status
Simulation time 54766784 ps
CPU time 2.81 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 198692 kb
Host smart-2a1ca446-5395-47d7-893a-311aece75120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551257679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2551257679
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2254756201
Short name T763
Test name
Test status
Simulation time 43411437 ps
CPU time 0.85 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 198092 kb
Host smart-7f50079c-485c-402e-8083-26eab287498a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254756201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2254756201
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4057178290
Short name T795
Test name
Test status
Simulation time 28808770 ps
CPU time 0.59 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:38 PM PDT 24
Peak memory 194360 kb
Host smart-e139bdf8-8678-4baa-bb5d-34e733032f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057178290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4057178290
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2978484661
Short name T743
Test name
Test status
Simulation time 29297951 ps
CPU time 0.6 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:37 PM PDT 24
Peak memory 194396 kb
Host smart-ba8541b8-9f30-4427-b921-f94ead283123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978484661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2978484661
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.32469819
Short name T771
Test name
Test status
Simulation time 49415624 ps
CPU time 0.63 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:38 PM PDT 24
Peak memory 194336 kb
Host smart-bec5e449-1101-448d-af37-b0f540e70171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32469819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.32469819
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.374437214
Short name T717
Test name
Test status
Simulation time 74421752 ps
CPU time 0.58 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 195016 kb
Host smart-deb7f705-5757-43ed-a00a-a07bacd999cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374437214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.374437214
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3925489110
Short name T825
Test name
Test status
Simulation time 42593499 ps
CPU time 0.59 seconds
Started Aug 02 04:42:36 PM PDT 24
Finished Aug 02 04:42:37 PM PDT 24
Peak memory 194352 kb
Host smart-d1349a77-013e-4d21-915f-4c7bc5460308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925489110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3925489110
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1850956884
Short name T800
Test name
Test status
Simulation time 34544419 ps
CPU time 0.59 seconds
Started Aug 02 04:42:46 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 194272 kb
Host smart-34191aa0-b300-4ce5-841f-4a8ed0ee1cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850956884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1850956884
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.421270980
Short name T742
Test name
Test status
Simulation time 95833438 ps
CPU time 0.64 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194360 kb
Host smart-781ffe3a-68a8-40e5-b171-63797fe7e143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421270980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.421270980
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2040570602
Short name T821
Test name
Test status
Simulation time 15952927 ps
CPU time 0.58 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194976 kb
Host smart-b07c6cdd-239a-49ce-945f-a1f54a0d1517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040570602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2040570602
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.192428044
Short name T734
Test name
Test status
Simulation time 58688742 ps
CPU time 0.6 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194300 kb
Host smart-cf173e3e-95f3-44b5-812e-45fc1aa3ee62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192428044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.192428044
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4233485326
Short name T724
Test name
Test status
Simulation time 17055976 ps
CPU time 0.61 seconds
Started Aug 02 04:42:40 PM PDT 24
Finished Aug 02 04:42:41 PM PDT 24
Peak memory 194312 kb
Host smart-d86bb491-ce06-411c-960d-e15c731da3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233485326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4233485326
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.985382344
Short name T118
Test name
Test status
Simulation time 67395232 ps
CPU time 0.88 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 196624 kb
Host smart-ab89a01d-94ca-4fb2-aa3d-f21f5ec77556
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985382344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.985382344
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3059070060
Short name T803
Test name
Test status
Simulation time 180845892 ps
CPU time 2.37 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:13 PM PDT 24
Peak memory 197644 kb
Host smart-d40b22d1-9379-4c8d-8ca4-a6917c70429c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059070060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3059070060
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1173780749
Short name T797
Test name
Test status
Simulation time 43056386 ps
CPU time 0.61 seconds
Started Aug 02 04:42:14 PM PDT 24
Finished Aug 02 04:42:14 PM PDT 24
Peak memory 195124 kb
Host smart-23627acc-bd5c-40ce-98b6-5975c264e7c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173780749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1173780749
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1595933749
Short name T716
Test name
Test status
Simulation time 39168601 ps
CPU time 1.8 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 198700 kb
Host smart-1cd1543c-6cd6-451f-a0be-fc952481735e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595933749 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1595933749
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1093822224
Short name T151
Test name
Test status
Simulation time 19210141 ps
CPU time 0.61 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 196140 kb
Host smart-6e5d9e3c-d39b-4a41-80c6-b99d485c5363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093822224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1093822224
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.978401592
Short name T776
Test name
Test status
Simulation time 100297669 ps
CPU time 0.61 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 194364 kb
Host smart-c6ff5a99-b120-43b9-95e9-eb1a00f5e258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978401592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.978401592
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.207198772
Short name T764
Test name
Test status
Simulation time 19992693 ps
CPU time 0.65 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:10 PM PDT 24
Peak memory 195316 kb
Host smart-91a9e173-42fd-4063-83ed-1f4ed3f1a750
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207198772 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.207198772
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.738497198
Short name T755
Test name
Test status
Simulation time 27683174 ps
CPU time 1.55 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:13 PM PDT 24
Peak memory 198736 kb
Host smart-a0448f8e-db41-4170-aa06-c2f4fdebb1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738497198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.738497198
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.428501931
Short name T838
Test name
Test status
Simulation time 148260809 ps
CPU time 0.86 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 197780 kb
Host smart-56cd9ec6-8354-4d65-aa67-ddf16aad4be8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428501931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.428501931
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2352462515
Short name T804
Test name
Test status
Simulation time 19522884 ps
CPU time 0.62 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194512 kb
Host smart-4992b862-2507-46b9-aacf-494273db45c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352462515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2352462515
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2244967734
Short name T782
Test name
Test status
Simulation time 48579624 ps
CPU time 0.57 seconds
Started Aug 02 04:42:36 PM PDT 24
Finished Aug 02 04:42:36 PM PDT 24
Peak memory 194304 kb
Host smart-34901f67-3764-4ee3-8f82-a192e42c0669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244967734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2244967734
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2094473223
Short name T715
Test name
Test status
Simulation time 38492710 ps
CPU time 0.59 seconds
Started Aug 02 04:42:47 PM PDT 24
Finished Aug 02 04:42:48 PM PDT 24
Peak memory 194940 kb
Host smart-60ceadeb-8abe-40c8-8184-cfe7e9c994f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094473223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2094473223
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3038019209
Short name T832
Test name
Test status
Simulation time 36693613 ps
CPU time 0.55 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194348 kb
Host smart-d219ac11-01b6-470c-b989-7977754feb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038019209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3038019209
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2415183482
Short name T831
Test name
Test status
Simulation time 15089690 ps
CPU time 0.56 seconds
Started Aug 02 04:42:35 PM PDT 24
Finished Aug 02 04:42:36 PM PDT 24
Peak memory 194340 kb
Host smart-43659979-5c34-4a8b-8aa2-835e50da88c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415183482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2415183482
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1573099325
Short name T728
Test name
Test status
Simulation time 12784624 ps
CPU time 0.61 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 195076 kb
Host smart-56f1d7a2-5ef1-4199-9468-03ddc2ba94fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573099325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1573099325
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2662069320
Short name T733
Test name
Test status
Simulation time 12853370 ps
CPU time 0.57 seconds
Started Aug 02 04:42:33 PM PDT 24
Finished Aug 02 04:42:34 PM PDT 24
Peak memory 194332 kb
Host smart-61f54c04-9770-4414-bd64-e60148b18fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662069320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2662069320
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2816994351
Short name T725
Test name
Test status
Simulation time 51014451 ps
CPU time 0.62 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:38 PM PDT 24
Peak memory 194992 kb
Host smart-2f11965b-b7e2-454f-b1e5-66837ee36680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816994351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2816994351
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4228238400
Short name T823
Test name
Test status
Simulation time 36655283 ps
CPU time 0.6 seconds
Started Aug 02 04:42:34 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 194488 kb
Host smart-72b1472b-8bf7-443f-93a8-a3bb68a28767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228238400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4228238400
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.917684414
Short name T719
Test name
Test status
Simulation time 53949016 ps
CPU time 0.58 seconds
Started Aug 02 04:42:37 PM PDT 24
Finished Aug 02 04:42:37 PM PDT 24
Peak memory 195000 kb
Host smart-5f5ca27d-3b63-4a03-9d19-87bc9d72d974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917684414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.917684414
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3118898045
Short name T792
Test name
Test status
Simulation time 277800741 ps
CPU time 0.94 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 198544 kb
Host smart-f6bb0ca9-fb0f-4ea2-8a97-02f9362debc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118898045 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3118898045
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3583174274
Short name T106
Test name
Test status
Simulation time 42857758 ps
CPU time 0.59 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 195304 kb
Host smart-7d2945f7-2c6a-4ae6-914c-e24b82e41b2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583174274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3583174274
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3334874602
Short name T738
Test name
Test status
Simulation time 15256826 ps
CPU time 0.6 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 194352 kb
Host smart-c4073356-01e8-4417-94ab-cf0d66bec02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334874602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3334874602
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2042882378
Short name T139
Test name
Test status
Simulation time 63286697 ps
CPU time 0.62 seconds
Started Aug 02 04:42:06 PM PDT 24
Finished Aug 02 04:42:07 PM PDT 24
Peak memory 195700 kb
Host smart-29ef3507-1fea-4dd4-b4a6-d150875f9549
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042882378 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2042882378
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.648241386
Short name T839
Test name
Test status
Simulation time 137621363 ps
CPU time 2.83 seconds
Started Aug 02 04:42:08 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 198644 kb
Host smart-0df8d8cf-4038-42e9-a934-c96602e739a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648241386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.648241386
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.86532608
Short name T155
Test name
Test status
Simulation time 163538128 ps
CPU time 0.78 seconds
Started Aug 02 04:42:12 PM PDT 24
Finished Aug 02 04:42:13 PM PDT 24
Peak memory 197396 kb
Host smart-40222091-1492-4d81-8017-fbf95c003367
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86532608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.gpio_tl_intg_err.86532608
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.427334985
Short name T809
Test name
Test status
Simulation time 135418231 ps
CPU time 1.04 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 198504 kb
Host smart-c6993fcd-56dd-4f71-ac72-b9eae8706ed2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427334985 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.427334985
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1531945857
Short name T104
Test name
Test status
Simulation time 39778692 ps
CPU time 0.61 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:07 PM PDT 24
Peak memory 195632 kb
Host smart-4b29f22a-b5bf-405a-a098-f2a830b44f6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531945857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1531945857
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.397170448
Short name T747
Test name
Test status
Simulation time 16256119 ps
CPU time 0.6 seconds
Started Aug 02 04:42:15 PM PDT 24
Finished Aug 02 04:42:16 PM PDT 24
Peak memory 194356 kb
Host smart-e0ccedfc-9454-4f2d-9c4e-1a2932fd0c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397170448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.397170448
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3441283261
Short name T138
Test name
Test status
Simulation time 82745356 ps
CPU time 0.72 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 196416 kb
Host smart-233d5938-5bf2-4c65-888d-4aec4330e57c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441283261 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3441283261
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2071228301
Short name T842
Test name
Test status
Simulation time 130799732 ps
CPU time 1.51 seconds
Started Aug 02 04:42:10 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 198704 kb
Host smart-e1db41a6-ddd4-4b0b-b729-b459e5e3150b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071228301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2071228301
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2232538451
Short name T844
Test name
Test status
Simulation time 155696736 ps
CPU time 1.22 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 198676 kb
Host smart-21b4941e-3444-4208-8583-cc1b906ac34b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232538451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2232538451
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1662154584
Short name T794
Test name
Test status
Simulation time 70270212 ps
CPU time 0.81 seconds
Started Aug 02 04:42:07 PM PDT 24
Finished Aug 02 04:42:07 PM PDT 24
Peak memory 198464 kb
Host smart-688b3c10-f011-489a-bc59-44530f005741
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662154584 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1662154584
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1824235861
Short name T153
Test name
Test status
Simulation time 142345871 ps
CPU time 0.62 seconds
Started Aug 02 04:42:09 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 195108 kb
Host smart-a97c4f48-c1c3-473a-98cf-6bdab02afd05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824235861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1824235861
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1873422608
Short name T768
Test name
Test status
Simulation time 36342022 ps
CPU time 0.58 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 195040 kb
Host smart-98554af0-88d0-40f9-a9f0-e04b40b920a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873422608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1873422608
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.871564731
Short name T770
Test name
Test status
Simulation time 22125536 ps
CPU time 0.67 seconds
Started Aug 02 04:42:11 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 195888 kb
Host smart-3a181db0-b6be-4ba9-8ca5-a7915ec1c79c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871564731 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.871564731
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3693652755
Short name T751
Test name
Test status
Simulation time 83749569 ps
CPU time 1.21 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198640 kb
Host smart-24cee1d0-e911-4a64-b25c-66c48d87ea6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693652755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3693652755
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.476497773
Short name T818
Test name
Test status
Simulation time 219485048 ps
CPU time 1.4 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198532 kb
Host smart-731552b3-fabc-4fa3-8520-f9148a9a9d11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476497773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.476497773
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3726763150
Short name T735
Test name
Test status
Simulation time 17199875 ps
CPU time 0.69 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 197936 kb
Host smart-6c3aa495-cac7-429c-b258-e38124742cbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726763150 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3726763150
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.717007918
Short name T123
Test name
Test status
Simulation time 41202731 ps
CPU time 0.64 seconds
Started Aug 02 04:42:19 PM PDT 24
Finished Aug 02 04:42:19 PM PDT 24
Peak memory 195584 kb
Host smart-8c397cef-dc5d-423a-9402-08ac78a43f52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717007918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.717007918
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1183524804
Short name T787
Test name
Test status
Simulation time 13873675 ps
CPU time 0.59 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 194964 kb
Host smart-7341baed-2404-48ca-83bf-699992524d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183524804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1183524804
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2393826276
Short name T136
Test name
Test status
Simulation time 77209670 ps
CPU time 0.85 seconds
Started Aug 02 04:42:19 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 197600 kb
Host smart-ec52ea28-3bbc-41e4-82c0-2aecb4e84fab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393826276 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2393826276
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3683849506
Short name T836
Test name
Test status
Simulation time 370383244 ps
CPU time 2.12 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198720 kb
Host smart-125b22cd-a052-4df8-bad3-560f6ca313f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683849506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3683849506
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4016813218
Short name T63
Test name
Test status
Simulation time 75344202 ps
CPU time 1.13 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198524 kb
Host smart-a59de27a-637a-4990-b767-976e938fd535
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016813218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4016813218
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1721002802
Short name T727
Test name
Test status
Simulation time 88296501 ps
CPU time 0.98 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 198532 kb
Host smart-fdf78016-39f1-44cc-9e73-f8630ebe1cc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721002802 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1721002802
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1298518887
Short name T152
Test name
Test status
Simulation time 20138661 ps
CPU time 0.59 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 195712 kb
Host smart-fda363a5-6fc4-4f85-ad86-b8ac86f8b6d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298518887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1298518887
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3996542230
Short name T805
Test name
Test status
Simulation time 46489079 ps
CPU time 0.58 seconds
Started Aug 02 04:42:17 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 194908 kb
Host smart-2a479074-1c27-4267-a6b8-d4cb355bcef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996542230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3996542230
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.194438115
Short name T812
Test name
Test status
Simulation time 69111870 ps
CPU time 0.8 seconds
Started Aug 02 04:42:16 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 196836 kb
Host smart-66dfdf75-b417-4004-a1f3-000a8acb9e11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194438115 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.194438115
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4106861949
Short name T730
Test name
Test status
Simulation time 409798477 ps
CPU time 1.91 seconds
Started Aug 02 04:42:22 PM PDT 24
Finished Aug 02 04:42:24 PM PDT 24
Peak memory 198628 kb
Host smart-069f3e19-3560-46d1-b270-4c59c4b73075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106861949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4106861949
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2003567788
Short name T48
Test name
Test status
Simulation time 164133848 ps
CPU time 1.17 seconds
Started Aug 02 04:42:18 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 198612 kb
Host smart-041adafb-89e9-4765-b87b-25accae837a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003567788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2003567788
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2772801047
Short name T537
Test name
Test status
Simulation time 44836487 ps
CPU time 0.57 seconds
Started Aug 02 04:47:23 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 194480 kb
Host smart-0ee21aa3-e6df-44a1-997f-495aa5bc6440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772801047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2772801047
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3502763824
Short name T60
Test name
Test status
Simulation time 65227584 ps
CPU time 0.83 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 196944 kb
Host smart-f3876e72-c84d-459d-baf9-b515addfd522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502763824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3502763824
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1944779122
Short name T93
Test name
Test status
Simulation time 307298593 ps
CPU time 12.02 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 195988 kb
Host smart-d7ca4dfc-6d22-43c7-a8bc-19e9f1febcd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944779122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1944779122
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3497432115
Short name T504
Test name
Test status
Simulation time 72011402 ps
CPU time 0.95 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 197116 kb
Host smart-4100d1a7-428a-4821-a4be-0b00d3e8c9a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497432115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3497432115
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1055739422
Short name T660
Test name
Test status
Simulation time 190436931 ps
CPU time 1.05 seconds
Started Aug 02 04:47:25 PM PDT 24
Finished Aug 02 04:47:26 PM PDT 24
Peak memory 196380 kb
Host smart-b216e62c-e3bf-44de-8185-549f6488f045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055739422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1055739422
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.877887400
Short name T602
Test name
Test status
Simulation time 82172851 ps
CPU time 3.18 seconds
Started Aug 02 04:47:25 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 198500 kb
Host smart-e695825b-7c25-432c-bd39-e57278d193e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877887400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.877887400
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3419261672
Short name T264
Test name
Test status
Simulation time 352609012 ps
CPU time 3.15 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:34 PM PDT 24
Peak memory 196284 kb
Host smart-29f3e69c-691e-4641-a7fb-64cae266bb2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419261672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3419261672
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3275870526
Short name T709
Test name
Test status
Simulation time 19510641 ps
CPU time 0.67 seconds
Started Aug 02 04:47:22 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 194640 kb
Host smart-2cbc1a46-d4dd-4e88-a987-071b51e447ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275870526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3275870526
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3646193689
Short name T521
Test name
Test status
Simulation time 65208084 ps
CPU time 0.83 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:47:17 PM PDT 24
Peak memory 196300 kb
Host smart-68c4322c-80e4-403e-8665-ea9db545a3ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646193689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3646193689
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2588734827
Short name T692
Test name
Test status
Simulation time 353377317 ps
CPU time 4.27 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 198464 kb
Host smart-21531c83-4d8d-439d-8dee-ea832e5179fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588734827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2588734827
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1901846551
Short name T645
Test name
Test status
Simulation time 221179156 ps
CPU time 0.9 seconds
Started Aug 02 04:47:11 PM PDT 24
Finished Aug 02 04:47:12 PM PDT 24
Peak memory 197476 kb
Host smart-d85e7974-cc8a-4ebe-afb0-1f9593ebf8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901846551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1901846551
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1565057034
Short name T667
Test name
Test status
Simulation time 155774818 ps
CPU time 0.87 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:47:17 PM PDT 24
Peak memory 195832 kb
Host smart-2739111d-d8f7-461c-be53-456467663d0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565057034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1565057034
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.532069041
Short name T460
Test name
Test status
Simulation time 27804639857 ps
CPU time 78.48 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:48:35 PM PDT 24
Peak memory 198672 kb
Host smart-36d938a5-7042-42b6-b4ce-57d0b0adce39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532069041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.532069041
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3391380947
Short name T560
Test name
Test status
Simulation time 393857476778 ps
CPU time 1514.8 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 05:12:28 PM PDT 24
Peak memory 206916 kb
Host smart-cb036dfa-aafd-4c93-8ec4-4d198f358298
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3391380947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3391380947
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2544392376
Short name T414
Test name
Test status
Simulation time 15390950 ps
CPU time 0.62 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 194308 kb
Host smart-83b5dc4a-9e15-4660-9b3a-4dc764a65cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544392376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2544392376
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3377839667
Short name T320
Test name
Test status
Simulation time 35524353 ps
CPU time 0.74 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 196292 kb
Host smart-41fbbc57-cb14-4637-bdcb-fe9300734155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377839667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3377839667
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.482382155
Short name T176
Test name
Test status
Simulation time 1369976308 ps
CPU time 9.52 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 197420 kb
Host smart-2f7a2689-288c-4a4a-a740-423821d92767
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482382155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.482382155
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3717425225
Short name T381
Test name
Test status
Simulation time 26202283 ps
CPU time 0.69 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 195164 kb
Host smart-f08a3423-a91b-4d52-9543-071bbb44c072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717425225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3717425225
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.258120845
Short name T444
Test name
Test status
Simulation time 64918028 ps
CPU time 1.91 seconds
Started Aug 02 04:47:12 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 198684 kb
Host smart-c3a0e08e-c8fb-46e9-9211-2fef9affb68a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258120845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.258120845
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2303469800
Short name T11
Test name
Test status
Simulation time 110584047 ps
CPU time 3.07 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 197368 kb
Host smart-b39f294e-d5c9-4f9a-956f-95793e01eb50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303469800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2303469800
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3363336280
Short name T364
Test name
Test status
Simulation time 165311663 ps
CPU time 1.06 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 197128 kb
Host smart-a7c630d5-4b67-4c4b-ad4b-d551f1cce567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363336280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3363336280
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3979985085
Short name T129
Test name
Test status
Simulation time 27707763 ps
CPU time 1.08 seconds
Started Aug 02 04:47:13 PM PDT 24
Finished Aug 02 04:47:14 PM PDT 24
Peak memory 196340 kb
Host smart-293b00d2-d3aa-4b9d-8edb-bbc1b1cd55b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979985085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3979985085
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2192901109
Short name T711
Test name
Test status
Simulation time 950296529 ps
CPU time 4.8 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 198468 kb
Host smart-62be2afa-d66e-48c9-b8ab-2edb09005392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192901109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2192901109
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3546485073
Short name T65
Test name
Test status
Simulation time 41331927 ps
CPU time 0.82 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 214276 kb
Host smart-7bd8db7f-3a07-4e40-9024-a5385718a22f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546485073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3546485073
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.860914790
Short name T600
Test name
Test status
Simulation time 31614711 ps
CPU time 0.92 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 196952 kb
Host smart-b038dacc-636f-4f46-b2ee-788d2596e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860914790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.860914790
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2968080933
Short name T231
Test name
Test status
Simulation time 175415471 ps
CPU time 0.87 seconds
Started Aug 02 04:47:17 PM PDT 24
Finished Aug 02 04:47:18 PM PDT 24
Peak memory 196408 kb
Host smart-ab4a1d3e-97d4-4d9c-baa9-8ff8310bf49f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968080933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2968080933
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.848626719
Short name T356
Test name
Test status
Simulation time 1220000368 ps
CPU time 20.97 seconds
Started Aug 02 04:47:17 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 198536 kb
Host smart-a6c55156-5345-45fe-92de-c55ef6d2cd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848626719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.848626719
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.447969173
Short name T100
Test name
Test status
Simulation time 28737688886 ps
CPU time 428.97 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 198752 kb
Host smart-2a9aa22c-3b56-4fbb-9834-1dd13cfba6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=447969173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.447969173
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4148147834
Short name T272
Test name
Test status
Simulation time 90015064 ps
CPU time 0.57 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:34 PM PDT 24
Peak memory 195068 kb
Host smart-a0d7d5d5-6f24-4750-b02b-40ebda2652d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148147834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4148147834
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.578356454
Short name T275
Test name
Test status
Simulation time 117184235 ps
CPU time 0.68 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 194568 kb
Host smart-6a87d54c-8a45-461e-8c94-fb71590ada6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578356454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.578356454
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1719023533
Short name T464
Test name
Test status
Simulation time 396011796 ps
CPU time 20.05 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 197696 kb
Host smart-0474bffa-8e33-48e0-aab5-1a95ba64c040
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719023533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1719023533
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1741620939
Short name T475
Test name
Test status
Simulation time 107262213 ps
CPU time 0.68 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 195120 kb
Host smart-fc056f55-232a-4c98-a957-f27ccb614f9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741620939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1741620939
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1339421662
Short name T633
Test name
Test status
Simulation time 78910143 ps
CPU time 1.07 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 196280 kb
Host smart-7f46b763-f799-4655-bc8d-59627a7d2c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339421662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1339421662
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3769298885
Short name T368
Test name
Test status
Simulation time 238193002 ps
CPU time 2.69 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 198712 kb
Host smart-7d5c9288-e67d-4e99-b857-1d5ae56a45aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769298885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3769298885
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.33976626
Short name T304
Test name
Test status
Simulation time 573328160 ps
CPU time 3.02 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:48 PM PDT 24
Peak memory 197684 kb
Host smart-139497c2-39ab-43f3-bd1c-b025a58a4515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.33976626
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2495097360
Short name T453
Test name
Test status
Simulation time 43192107 ps
CPU time 0.95 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 197208 kb
Host smart-1450c6ae-fbd6-46f7-b4d6-53ec20439e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495097360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2495097360
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2929531719
Short name T484
Test name
Test status
Simulation time 205862511 ps
CPU time 0.68 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 194752 kb
Host smart-581e8ce6-4852-48c0-af67-59fbea63a4fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929531719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2929531719
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1684280859
Short name T204
Test name
Test status
Simulation time 818166909 ps
CPU time 5.33 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:43 PM PDT 24
Peak memory 198436 kb
Host smart-1a9a0d1d-8f54-4965-9182-21867e7520f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684280859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1684280859
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3157118067
Short name T625
Test name
Test status
Simulation time 81796419 ps
CPU time 0.78 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 195780 kb
Host smart-5e7fe745-dcd0-4bf3-9b57-7625c9adac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157118067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3157118067
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.794164977
Short name T181
Test name
Test status
Simulation time 42990227 ps
CPU time 1.12 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 196728 kb
Host smart-e8e0cfc0-2f18-4a03-8d05-f0613aa85b16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794164977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.794164977
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1257703943
Short name T97
Test name
Test status
Simulation time 10699269570 ps
CPU time 68.72 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:48:41 PM PDT 24
Peak memory 198664 kb
Host smart-52ca4a44-e0d3-4ea6-9099-a66d4958a8ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257703943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1257703943
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2860132826
Short name T174
Test name
Test status
Simulation time 59152034 ps
CPU time 0.55 seconds
Started Aug 02 04:47:48 PM PDT 24
Finished Aug 02 04:47:49 PM PDT 24
Peak memory 194540 kb
Host smart-d5ee13b5-21b1-43bb-8c32-8303627760cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860132826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2860132826
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3090044805
Short name T289
Test name
Test status
Simulation time 121684118 ps
CPU time 0.67 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 194676 kb
Host smart-07d313c7-a570-42d3-b4a4-fa61f37abca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090044805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3090044805
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.729646504
Short name T222
Test name
Test status
Simulation time 545635570 ps
CPU time 18.49 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:57 PM PDT 24
Peak memory 198460 kb
Host smart-4395389c-6a94-4fcd-968c-c223289f76ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729646504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.729646504
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2118667949
Short name T225
Test name
Test status
Simulation time 61774918 ps
CPU time 1.17 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 198212 kb
Host smart-c912bdaa-2831-4f92-9472-c51b374c77a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118667949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2118667949
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.348570840
Short name T585
Test name
Test status
Simulation time 52097231 ps
CPU time 0.74 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 196528 kb
Host smart-4d9bb774-0d76-4323-8b41-7b978bf0741c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348570840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.348570840
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1811265053
Short name T341
Test name
Test status
Simulation time 234301693 ps
CPU time 1.89 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 198640 kb
Host smart-056ab031-50e6-4178-97db-a2f3061a68b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811265053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1811265053
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4135860033
Short name T564
Test name
Test status
Simulation time 218985790 ps
CPU time 2.82 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 197988 kb
Host smart-e709ef53-276a-4e99-b578-35f06c5d7146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135860033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4135860033
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.745392133
Short name T433
Test name
Test status
Simulation time 94359877 ps
CPU time 1.02 seconds
Started Aug 02 04:47:48 PM PDT 24
Finished Aug 02 04:47:49 PM PDT 24
Peak memory 197268 kb
Host smart-064948bf-f1b7-4a13-8dc2-a3e85664f17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745392133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.745392133
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3236296487
Short name T232
Test name
Test status
Simulation time 310707182 ps
CPU time 0.95 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 196516 kb
Host smart-bdce8838-1e6c-4272-8623-bbdccabd018c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236296487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3236296487
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.70297365
Short name T649
Test name
Test status
Simulation time 921342350 ps
CPU time 3.9 seconds
Started Aug 02 04:47:43 PM PDT 24
Finished Aug 02 04:47:47 PM PDT 24
Peak memory 197892 kb
Host smart-f6767551-4e48-4018-80c1-761e507602fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70297365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand
om_long_reg_writes_reg_reads.70297365
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1726793302
Short name T303
Test name
Test status
Simulation time 118238057 ps
CPU time 1.03 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:34 PM PDT 24
Peak memory 196288 kb
Host smart-40fc416d-cbe6-4813-ae68-0b64c9745f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726793302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1726793302
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1092167361
Short name T384
Test name
Test status
Simulation time 142351575 ps
CPU time 1.29 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 197048 kb
Host smart-3f1f501f-aadb-4122-8601-1547a8ed8091
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092167361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1092167361
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.63478049
Short name T211
Test name
Test status
Simulation time 25396817284 ps
CPU time 86.93 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:49:04 PM PDT 24
Peak memory 198636 kb
Host smart-3ac72961-917e-4245-92d8-12eb11be3783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63478049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gp
io_stress_all.63478049
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2678446948
Short name T635
Test name
Test status
Simulation time 37547251239 ps
CPU time 934.81 seconds
Started Aug 02 04:47:41 PM PDT 24
Finished Aug 02 05:03:16 PM PDT 24
Peak memory 198784 kb
Host smart-4f21f9a4-bc94-4123-b03a-12ea5dd12819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2678446948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2678446948
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.937391500
Short name T544
Test name
Test status
Simulation time 38413799 ps
CPU time 0.59 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:44 PM PDT 24
Peak memory 195128 kb
Host smart-d858417b-f5a7-44d4-8ca9-a66a3bd8cbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937391500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.937391500
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.528588841
Short name T512
Test name
Test status
Simulation time 53590675 ps
CPU time 0.63 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 194424 kb
Host smart-8b0c1d0d-1a36-47e8-901b-2eea607b98c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528588841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.528588841
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.68499346
Short name T654
Test name
Test status
Simulation time 758432042 ps
CPU time 20.39 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 197320 kb
Host smart-77fcae14-4e1b-4844-8d87-dbf5d461e33d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68499346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stress
.68499346
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1441687229
Short name T242
Test name
Test status
Simulation time 185469214 ps
CPU time 1.07 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 197104 kb
Host smart-74da6f72-104a-4d68-8175-f063f78e57f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441687229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1441687229
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3307241800
Short name T263
Test name
Test status
Simulation time 415557877 ps
CPU time 1.35 seconds
Started Aug 02 04:47:51 PM PDT 24
Finished Aug 02 04:47:52 PM PDT 24
Peak memory 196232 kb
Host smart-fef72e81-dd48-4e3e-b05d-e1ebd53ccecd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307241800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3307241800
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1301884361
Short name T427
Test name
Test status
Simulation time 111356243 ps
CPU time 2.81 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:42 PM PDT 24
Peak memory 198484 kb
Host smart-d4eb8893-23dc-41d8-b0cd-b7b969fe673b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301884361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1301884361
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1376389292
Short name T561
Test name
Test status
Simulation time 106939548 ps
CPU time 2.17 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:42 PM PDT 24
Peak memory 198560 kb
Host smart-68c771d3-e56c-4338-ac5a-7d750eac864a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376389292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1376389292
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2585184943
Short name T638
Test name
Test status
Simulation time 79000862 ps
CPU time 1.28 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:47:50 PM PDT 24
Peak memory 197304 kb
Host smart-005efd24-0203-452e-9bbf-7a94baf53edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585184943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2585184943
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.673078641
Short name T343
Test name
Test status
Simulation time 25592095 ps
CPU time 0.72 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 195808 kb
Host smart-907c2bfa-23a1-4c98-b203-1f9817ac3864
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673078641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.673078641
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2324588129
Short name T562
Test name
Test status
Simulation time 676757432 ps
CPU time 2.11 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 198616 kb
Host smart-b595468a-2992-400a-9a29-7b22bacbcb62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324588129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2324588129
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3097884581
Short name T307
Test name
Test status
Simulation time 41987581 ps
CPU time 1.16 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 196248 kb
Host smart-1533c17b-8f3a-44ac-9a7b-68d4b6828268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097884581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3097884581
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2290600359
Short name T358
Test name
Test status
Simulation time 416916534 ps
CPU time 0.93 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196796 kb
Host smart-15228409-6c1f-47ac-9795-cc834ba1c7e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290600359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2290600359
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2013047555
Short name T446
Test name
Test status
Simulation time 2409877980 ps
CPU time 57.72 seconds
Started Aug 02 04:47:36 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 198632 kb
Host smart-81444502-cab0-4bb7-aa3d-9e25b2ab57cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013047555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2013047555
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.4289247681
Short name T459
Test name
Test status
Simulation time 11426490 ps
CPU time 0.58 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 194380 kb
Host smart-9b3c5ebb-7a68-4691-b580-54cd8721ee73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289247681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.4289247681
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2717001588
Short name T208
Test name
Test status
Simulation time 259114125 ps
CPU time 0.67 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 194432 kb
Host smart-4da6ef23-63fd-4423-ae80-1df295cb9741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717001588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2717001588
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3039377678
Short name T595
Test name
Test status
Simulation time 1567252149 ps
CPU time 19.97 seconds
Started Aug 02 04:47:47 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 196984 kb
Host smart-edbd7d3f-1eab-47e8-bf60-e36aa711db3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039377678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3039377678
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3961986615
Short name T495
Test name
Test status
Simulation time 102297361 ps
CPU time 0.81 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 196376 kb
Host smart-5192875b-640b-442f-9f19-31ac13534e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961986615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3961986615
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4207412441
Short name T387
Test name
Test status
Simulation time 118867559 ps
CPU time 0.76 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 196656 kb
Host smart-5ca99bd9-4d83-40ad-9d98-160e007c2f7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207412441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4207412441
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1239956062
Short name T398
Test name
Test status
Simulation time 51418689 ps
CPU time 1.99 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 198600 kb
Host smart-40a842ee-59a1-456f-8a2c-278c370e0db1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239956062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1239956062
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.545320664
Short name T266
Test name
Test status
Simulation time 106329186 ps
CPU time 1.83 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:47:48 PM PDT 24
Peak memory 197092 kb
Host smart-e99008ad-ab2a-4a54-8799-f79abac51699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545320664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
545320664
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1503576448
Short name T195
Test name
Test status
Simulation time 151872043 ps
CPU time 1.23 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196336 kb
Host smart-67a1bd92-ff0d-4247-99ef-64733c4a4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503576448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1503576448
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.417064585
Short name T300
Test name
Test status
Simulation time 57011493 ps
CPU time 1.21 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196372 kb
Host smart-b13d8abc-5165-4638-a350-b8ad1976704f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417064585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.417064585
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2940646535
Short name T279
Test name
Test status
Simulation time 39659244 ps
CPU time 1.7 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:47:48 PM PDT 24
Peak memory 198488 kb
Host smart-289a5c87-a2bd-424c-a1f6-86101857fc57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940646535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2940646535
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1639582529
Short name T339
Test name
Test status
Simulation time 98250307 ps
CPU time 1.05 seconds
Started Aug 02 04:47:50 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 196712 kb
Host smart-0dc009a6-23e6-452a-b823-fca932d4d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639582529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1639582529
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2934301019
Short name T88
Test name
Test status
Simulation time 101613351 ps
CPU time 1.44 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:47:50 PM PDT 24
Peak memory 197188 kb
Host smart-bcacb130-3650-4621-8791-183fc8ff3a84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934301019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2934301019
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.129917274
Short name T685
Test name
Test status
Simulation time 23249896350 ps
CPU time 99.65 seconds
Started Aug 02 04:47:43 PM PDT 24
Finished Aug 02 04:49:23 PM PDT 24
Peak memory 198784 kb
Host smart-1a97cb54-fc72-4e17-9934-cdd94793f538
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129917274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.129917274
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.435244009
Short name T529
Test name
Test status
Simulation time 11675504 ps
CPU time 0.55 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 194452 kb
Host smart-e8bbecc8-f0c8-4bd4-b2ef-4566f565f1e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435244009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.435244009
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1076622038
Short name T698
Test name
Test status
Simulation time 13245458 ps
CPU time 0.61 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 193896 kb
Host smart-135fa757-9a2f-4074-9722-7adf8f067758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076622038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1076622038
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3884005504
Short name T205
Test name
Test status
Simulation time 640028487 ps
CPU time 18.78 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:57 PM PDT 24
Peak memory 197100 kb
Host smart-019a950f-9d6e-48e9-80ea-927335b6c8e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884005504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3884005504
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.690891517
Short name T458
Test name
Test status
Simulation time 50745001 ps
CPU time 0.8 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 196296 kb
Host smart-254ee5e0-cebc-420f-8161-028ff2b4a2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690891517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.690891517
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2954174346
Short name T466
Test name
Test status
Simulation time 25807840 ps
CPU time 0.72 seconds
Started Aug 02 04:47:50 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 195444 kb
Host smart-610572c4-0fa9-4a8c-bf51-bcb02acdbe89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954174346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2954174346
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.581717155
Short name T281
Test name
Test status
Simulation time 1026313937 ps
CPU time 1.24 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 197196 kb
Host smart-c5922fa4-5f79-408c-8d00-2125fd0cebb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581717155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
581717155
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3091869547
Short name T535
Test name
Test status
Simulation time 104000883 ps
CPU time 0.95 seconds
Started Aug 02 04:47:41 PM PDT 24
Finished Aug 02 04:47:42 PM PDT 24
Peak memory 196416 kb
Host smart-acefdf32-14a0-4c40-b76c-465ff8452fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091869547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3091869547
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3634620498
Short name T619
Test name
Test status
Simulation time 134752341 ps
CPU time 0.9 seconds
Started Aug 02 04:47:40 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196412 kb
Host smart-ffb05c75-c317-4460-9e02-479b905424c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634620498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3634620498
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1366055554
Short name T702
Test name
Test status
Simulation time 2804247248 ps
CPU time 3.33 seconds
Started Aug 02 04:47:51 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 198492 kb
Host smart-5593acdc-5212-41e8-ac1b-d49e5c453b51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366055554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1366055554
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.142455995
Short name T454
Test name
Test status
Simulation time 82213046 ps
CPU time 1.28 seconds
Started Aug 02 04:47:42 PM PDT 24
Finished Aug 02 04:47:43 PM PDT 24
Peak memory 196936 kb
Host smart-e7d3e4fc-1689-43c2-a21b-af90886c6dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142455995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.142455995
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1046244728
Short name T291
Test name
Test status
Simulation time 175674266 ps
CPU time 0.96 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 196100 kb
Host smart-ceddf02f-3709-4dbb-8d71-3bbc35291cb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046244728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1046244728
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2367269720
Short name T663
Test name
Test status
Simulation time 75328927102 ps
CPU time 88.35 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:49:12 PM PDT 24
Peak memory 198092 kb
Host smart-807f2a1a-001c-4d12-b111-39ab600cfa25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367269720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2367269720
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1475980186
Short name T591
Test name
Test status
Simulation time 35848745 ps
CPU time 0.59 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 194308 kb
Host smart-9c654403-adac-48cd-b6a2-7b8f10e2e063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475980186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1475980186
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1388314943
Short name T294
Test name
Test status
Simulation time 80838216 ps
CPU time 0.87 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 196720 kb
Host smart-dc2f5f9f-6838-4857-aead-aa80b990f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388314943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1388314943
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2118829801
Short name T455
Test name
Test status
Simulation time 1814598874 ps
CPU time 23.3 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 196656 kb
Host smart-9e01c1f1-deb2-4860-a116-2dda4b86d135
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118829801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2118829801
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3688703635
Short name T94
Test name
Test status
Simulation time 90013963 ps
CPU time 0.82 seconds
Started Aug 02 04:47:51 PM PDT 24
Finished Aug 02 04:47:52 PM PDT 24
Peak memory 196904 kb
Host smart-5d58b423-fa72-4c36-9bde-9c5173bd40c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688703635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3688703635
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3341506261
Short name T230
Test name
Test status
Simulation time 645696370 ps
CPU time 0.84 seconds
Started Aug 02 04:47:53 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 195960 kb
Host smart-5bdb6621-adfc-4c77-8d59-256e91f2bed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341506261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3341506261
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2858155319
Short name T23
Test name
Test status
Simulation time 25255895 ps
CPU time 1.14 seconds
Started Aug 02 04:48:04 PM PDT 24
Finished Aug 02 04:48:05 PM PDT 24
Peak memory 198312 kb
Host smart-1dac8fb4-974e-4b1a-b62b-7bca050177b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858155319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2858155319
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2583978181
Short name T375
Test name
Test status
Simulation time 544199589 ps
CPU time 2.62 seconds
Started Aug 02 04:47:51 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 198568 kb
Host smart-1e30130b-7c37-469f-bf93-f7c2a104e272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583978181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2583978181
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1007018893
Short name T98
Test name
Test status
Simulation time 143673612 ps
CPU time 1.2 seconds
Started Aug 02 04:47:43 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 197452 kb
Host smart-8926fde9-e743-42d3-955d-ae167838b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007018893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1007018893
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1033759636
Short name T36
Test name
Test status
Simulation time 16999094 ps
CPU time 0.62 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 194716 kb
Host smart-6dcb4eb3-70ec-4b21-99fb-4a97ce86cabd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033759636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1033759636
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2264683904
Short name T705
Test name
Test status
Simulation time 218849277 ps
CPU time 2.2 seconds
Started Aug 02 04:48:07 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 198556 kb
Host smart-2ad3b51e-c1ee-40fa-b2d5-7485c19fe824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264683904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2264683904
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.598849291
Short name T128
Test name
Test status
Simulation time 91310804 ps
CPU time 1.34 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 197188 kb
Host smart-012a818b-6283-4c4d-952a-d594cc497ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598849291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.598849291
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.972075454
Short name T16
Test name
Test status
Simulation time 115904036 ps
CPU time 1.42 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:47:48 PM PDT 24
Peak memory 198368 kb
Host smart-218ac3c9-2c7a-44c2-96cb-01cf29887fc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972075454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.972075454
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.128476083
Short name T632
Test name
Test status
Simulation time 49953965679 ps
CPU time 152.81 seconds
Started Aug 02 04:47:54 PM PDT 24
Finished Aug 02 04:50:27 PM PDT 24
Peak memory 198676 kb
Host smart-9e18543a-7223-499b-9591-0632837d2108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128476083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.128476083
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.4130352863
Short name T87
Test name
Test status
Simulation time 25943118 ps
CPU time 0.57 seconds
Started Aug 02 04:47:53 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 194464 kb
Host smart-7d719f3c-3248-4eb0-b742-523bbcb23e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130352863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.4130352863
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3285085940
Short name T370
Test name
Test status
Simulation time 18654404 ps
CPU time 0.61 seconds
Started Aug 02 04:47:57 PM PDT 24
Finished Aug 02 04:47:57 PM PDT 24
Peak memory 195108 kb
Host smart-c3818214-c933-4d40-8b60-7c496f886d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285085940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3285085940
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1547274738
Short name T397
Test name
Test status
Simulation time 343190055 ps
CPU time 17.54 seconds
Started Aug 02 04:47:51 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 197180 kb
Host smart-cb6e64d0-a491-4c41-89c0-596487f5f35a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547274738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1547274738
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1863816727
Short name T311
Test name
Test status
Simulation time 81159155 ps
CPU time 0.81 seconds
Started Aug 02 04:47:57 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 196420 kb
Host smart-2b14fd6e-3444-4792-8fb9-3de74d62c80d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863816727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1863816727
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2115614568
Short name T594
Test name
Test status
Simulation time 61749290 ps
CPU time 0.97 seconds
Started Aug 02 04:47:43 PM PDT 24
Finished Aug 02 04:47:44 PM PDT 24
Peak memory 196288 kb
Host smart-b57ac2fb-8197-44dd-a316-56fdc033e57f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115614568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2115614568
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.741870503
Short name T367
Test name
Test status
Simulation time 86505880 ps
CPU time 3.45 seconds
Started Aug 02 04:47:50 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 198600 kb
Host smart-47697c66-fde9-41ed-a277-f569b8f7150f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741870503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.741870503
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2796327411
Short name T470
Test name
Test status
Simulation time 84363418 ps
CPU time 1.19 seconds
Started Aug 02 04:48:02 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 195864 kb
Host smart-360eb3b2-05cf-46d7-935c-03ae44026a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796327411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2796327411
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.210664801
Short name T543
Test name
Test status
Simulation time 30974044 ps
CPU time 0.81 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 195928 kb
Host smart-bee28121-5913-4a57-8d58-1bb1b2bacb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210664801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.210664801
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2237569367
Short name T68
Test name
Test status
Simulation time 37374395 ps
CPU time 1.26 seconds
Started Aug 02 04:47:56 PM PDT 24
Finished Aug 02 04:47:57 PM PDT 24
Peak memory 197508 kb
Host smart-be9b9bb0-074f-4542-8260-fa6b715efd19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237569367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2237569367
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3186566349
Short name T592
Test name
Test status
Simulation time 2015729206 ps
CPU time 5.46 seconds
Started Aug 02 04:47:57 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 198352 kb
Host smart-c6ef38aa-ed52-455d-8012-7caaf99d2ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186566349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3186566349
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4049504100
Short name T244
Test name
Test status
Simulation time 62425141 ps
CPU time 0.86 seconds
Started Aug 02 04:47:44 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 195664 kb
Host smart-4eab1124-b594-448f-bf4d-23881098265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049504100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4049504100
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.172695827
Short name T662
Test name
Test status
Simulation time 71194297 ps
CPU time 1.27 seconds
Started Aug 02 04:47:56 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 197652 kb
Host smart-b8b3af8e-8f9d-4d96-8c4e-b724f897da58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172695827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.172695827
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1266527118
Short name T280
Test name
Test status
Simulation time 9925103614 ps
CPU time 134.76 seconds
Started Aug 02 04:48:05 PM PDT 24
Finished Aug 02 04:50:20 PM PDT 24
Peak memory 198560 kb
Host smart-25128084-90d4-433b-8c67-09b33e9f60f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266527118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1266527118
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3382236667
Short name T506
Test name
Test status
Simulation time 56660362 ps
CPU time 0.65 seconds
Started Aug 02 04:47:58 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 194680 kb
Host smart-a41072e0-02bf-4f28-8577-9b50a995d677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382236667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3382236667
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3681872415
Short name T268
Test name
Test status
Simulation time 33775311 ps
CPU time 0.66 seconds
Started Aug 02 04:47:54 PM PDT 24
Finished Aug 02 04:47:55 PM PDT 24
Peak memory 194664 kb
Host smart-5d2eec12-a044-4ed3-981e-c3c3b34ac7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681872415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3681872415
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.400677470
Short name T510
Test name
Test status
Simulation time 1676051018 ps
CPU time 21.84 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 197508 kb
Host smart-7bbb3f62-3843-4bb9-b6c3-f010c9194a77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400677470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.400677470
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.954704160
Short name T19
Test name
Test status
Simulation time 272316208 ps
CPU time 0.91 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 197664 kb
Host smart-587a2a68-260d-48aa-ac8a-524f49f99a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954704160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.954704160
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.235054921
Short name T251
Test name
Test status
Simulation time 43757317 ps
CPU time 1.22 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:48:02 PM PDT 24
Peak memory 196372 kb
Host smart-48463c74-e995-4a84-b342-d982fde5aaed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235054921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.235054921
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3887693404
Short name T708
Test name
Test status
Simulation time 63990890 ps
CPU time 2.39 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:06 PM PDT 24
Peak memory 198700 kb
Host smart-f028f70e-6df5-4fbe-b5f9-60d86eeaf4c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887693404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3887693404
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2607194771
Short name T546
Test name
Test status
Simulation time 98957682 ps
CPU time 2.57 seconds
Started Aug 02 04:48:04 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 196472 kb
Host smart-63fedcf2-2123-4eef-afa9-4e12a7b8eb37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607194771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2607194771
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1583466102
Short name T622
Test name
Test status
Simulation time 117192127 ps
CPU time 0.76 seconds
Started Aug 02 04:47:57 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 196504 kb
Host smart-e3b1ecae-fc72-4e01-932d-f559ecc332ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583466102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1583466102
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.783224640
Short name T245
Test name
Test status
Simulation time 62149730 ps
CPU time 0.89 seconds
Started Aug 02 04:48:06 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 196288 kb
Host smart-97d1db82-6dbe-404d-ba70-c75555ea2485
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783224640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.783224640
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1418749284
Short name T5
Test name
Test status
Simulation time 2367254188 ps
CPU time 2 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 198560 kb
Host smart-bcf7286d-d372-4675-9854-ca9a1c4f588c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418749284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1418749284
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3740102202
Short name T569
Test name
Test status
Simulation time 229753427 ps
CPU time 1.02 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:47:50 PM PDT 24
Peak memory 196348 kb
Host smart-594d8641-b7cc-4573-af85-c83f11decda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740102202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3740102202
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1450978330
Short name T362
Test name
Test status
Simulation time 39818815 ps
CPU time 0.9 seconds
Started Aug 02 04:48:06 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 196968 kb
Host smart-e904988d-6ab1-4ac3-95c8-85d2cc1e896a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450978330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1450978330
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1059466812
Short name T533
Test name
Test status
Simulation time 17249456246 ps
CPU time 74.57 seconds
Started Aug 02 04:47:53 PM PDT 24
Finished Aug 02 04:49:08 PM PDT 24
Peak memory 198668 kb
Host smart-72fd846f-d6cd-4bba-b4ae-2945c4b2ed94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059466812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1059466812
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3489698471
Short name T611
Test name
Test status
Simulation time 22768783 ps
CPU time 0.61 seconds
Started Aug 02 04:48:07 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 195096 kb
Host smart-9289c6f4-1ecb-4d3d-b7d6-00b312d6f0b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489698471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3489698471
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.597961805
Short name T238
Test name
Test status
Simulation time 86423994 ps
CPU time 0.83 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 197060 kb
Host smart-e940532f-a079-4c7a-8d93-a62002849604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597961805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.597961805
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.913420972
Short name T276
Test name
Test status
Simulation time 726127344 ps
CPU time 18.82 seconds
Started Aug 02 04:47:58 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 197048 kb
Host smart-3e55400d-63df-4958-8ad1-67879e995fbd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913420972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.913420972
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.438979381
Short name T143
Test name
Test status
Simulation time 40201557 ps
CPU time 0.75 seconds
Started Aug 02 04:48:02 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 196120 kb
Host smart-e455e1a9-6b4d-4af2-8054-390585daa305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438979381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.438979381
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3973665904
Short name T437
Test name
Test status
Simulation time 102196560 ps
CPU time 0.91 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 196908 kb
Host smart-f3ef031c-ae46-4738-a1cf-f84d722030f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973665904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3973665904
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4048997922
Short name T233
Test name
Test status
Simulation time 188168007 ps
CPU time 1.96 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 198224 kb
Host smart-690f9b30-3b61-48c4-9af8-cfd3276d620e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048997922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4048997922
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3800791128
Short name T486
Test name
Test status
Simulation time 41878191 ps
CPU time 1.39 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:47:50 PM PDT 24
Peak memory 196324 kb
Host smart-66c8bf36-a457-40dc-99a7-6a7ba89cc219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800791128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3800791128
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2014441525
Short name T317
Test name
Test status
Simulation time 39074159 ps
CPU time 1.28 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:46 PM PDT 24
Peak memory 196296 kb
Host smart-be761b3d-56f1-4356-9951-c4a013d2063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014441525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2014441525
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4138075054
Short name T681
Test name
Test status
Simulation time 226486239 ps
CPU time 1.09 seconds
Started Aug 02 04:48:07 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 197272 kb
Host smart-db3491d1-d8fd-427b-b656-e25856df3060
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138075054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4138075054
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1620407761
Short name T9
Test name
Test status
Simulation time 665065600 ps
CPU time 2.35 seconds
Started Aug 02 04:47:52 PM PDT 24
Finished Aug 02 04:47:55 PM PDT 24
Peak memory 198528 kb
Host smart-b5e680da-d751-420e-8fd1-35fbdd3c0f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620407761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1620407761
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2208435303
Short name T114
Test name
Test status
Simulation time 70231277 ps
CPU time 1.38 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 198484 kb
Host smart-2b7c75d6-b9df-4b17-b45c-3e1b1296ed23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208435303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2208435303
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3679515348
Short name T684
Test name
Test status
Simulation time 83586840 ps
CPU time 1.44 seconds
Started Aug 02 04:47:49 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 196660 kb
Host smart-947907b5-4123-4430-bcf6-2ab3ff092b36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679515348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3679515348
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3624881248
Short name T386
Test name
Test status
Simulation time 29426185894 ps
CPU time 103.67 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:49:30 PM PDT 24
Peak memory 198724 kb
Host smart-e66b9ad4-db51-4181-9efa-c97122a16be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624881248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3624881248
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1467298548
Short name T203
Test name
Test status
Simulation time 61280561 ps
CPU time 0.58 seconds
Started Aug 02 04:47:57 PM PDT 24
Finished Aug 02 04:47:58 PM PDT 24
Peak memory 195344 kb
Host smart-c72c6545-0f13-4725-a992-b83ff788432d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467298548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1467298548
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1905548820
Short name T305
Test name
Test status
Simulation time 22732371 ps
CPU time 0.61 seconds
Started Aug 02 04:47:50 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 194340 kb
Host smart-ae29f58c-209e-4202-b541-e3f3cc6e0d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905548820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1905548820
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3302907729
Short name T465
Test name
Test status
Simulation time 481542206 ps
CPU time 12.39 seconds
Started Aug 02 04:47:59 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 197372 kb
Host smart-9cb62873-1262-4e32-a38b-63e2ecb0f973
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302907729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3302907729
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.476949469
Short name T319
Test name
Test status
Simulation time 27009606 ps
CPU time 0.67 seconds
Started Aug 02 04:47:46 PM PDT 24
Finished Aug 02 04:47:47 PM PDT 24
Peak memory 195260 kb
Host smart-83d8f709-104f-4618-9646-4f2ec8262a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476949469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.476949469
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1910483559
Short name T541
Test name
Test status
Simulation time 59930624 ps
CPU time 1.11 seconds
Started Aug 02 04:47:53 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 197000 kb
Host smart-33cef198-5d12-4a05-a2f8-5d3375f2bd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910483559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1910483559
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2350414429
Short name T116
Test name
Test status
Simulation time 26055098 ps
CPU time 1.1 seconds
Started Aug 02 04:48:02 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 197356 kb
Host smart-0878c081-574f-4d4c-9639-d676d22b0ba8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350414429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2350414429
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3222960946
Short name T424
Test name
Test status
Simulation time 1481762329 ps
CPU time 1.81 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:05 PM PDT 24
Peak memory 196956 kb
Host smart-9af0c8e3-7dce-4683-8d84-d058168bbcfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222960946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3222960946
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.373932929
Short name T675
Test name
Test status
Simulation time 65816608 ps
CPU time 0.74 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 196512 kb
Host smart-60157c23-cb45-4c82-8de2-9d7e7ad94851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373932929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.373932929
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.4130211133
Short name T404
Test name
Test status
Simulation time 60056400 ps
CPU time 1.29 seconds
Started Aug 02 04:47:53 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 197456 kb
Host smart-2bec9d82-e10c-42c2-a773-511433d1355d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130211133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.4130211133
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.82705593
Short name T217
Test name
Test status
Simulation time 572261408 ps
CPU time 5.09 seconds
Started Aug 02 04:47:45 PM PDT 24
Finished Aug 02 04:47:50 PM PDT 24
Peak memory 198600 kb
Host smart-3296711a-aef2-4503-875c-e94a06fa1672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82705593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand
om_long_reg_writes_reg_reads.82705593
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.639376268
Short name T183
Test name
Test status
Simulation time 53973392 ps
CPU time 0.97 seconds
Started Aug 02 04:48:05 PM PDT 24
Finished Aug 02 04:48:06 PM PDT 24
Peak memory 196932 kb
Host smart-526abc3c-d6d8-4425-86a8-321ec6fbef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639376268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.639376268
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.63868326
Short name T542
Test name
Test status
Simulation time 103073615 ps
CPU time 1.13 seconds
Started Aug 02 04:48:00 PM PDT 24
Finished Aug 02 04:48:01 PM PDT 24
Peak memory 196232 kb
Host smart-a1d8a860-e47d-46a8-b86a-14596b7a932b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63868326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.63868326
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1258047949
Short name T519
Test name
Test status
Simulation time 898952079 ps
CPU time 26.8 seconds
Started Aug 02 04:47:58 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 198456 kb
Host smart-7ec69b46-3a79-4e14-b716-deb118b60600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258047949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1258047949
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1456449499
Short name T485
Test name
Test status
Simulation time 18024602 ps
CPU time 0.58 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 195044 kb
Host smart-b99266c1-68c3-48d7-aea5-7e5ee0b31f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456449499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1456449499
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1468119627
Short name T110
Test name
Test status
Simulation time 45498583 ps
CPU time 0.83 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 197420 kb
Host smart-b1190bba-9f89-46da-87c0-4a84dfa828b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468119627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1468119627
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2526582427
Short name T609
Test name
Test status
Simulation time 3274026621 ps
CPU time 19.47 seconds
Started Aug 02 04:47:17 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 198728 kb
Host smart-0f2eb67e-a70f-4d45-83e9-372fb85c8ebe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526582427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2526582427
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2902011035
Short name T636
Test name
Test status
Simulation time 299861330 ps
CPU time 0.88 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 197440 kb
Host smart-f072654a-28cf-4c5e-a51d-0b129f23a05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902011035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2902011035
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2117927150
Short name T473
Test name
Test status
Simulation time 80033038 ps
CPU time 1.38 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 196288 kb
Host smart-a7b60170-2743-40f4-81cf-728360540ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117927150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2117927150
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3559322194
Short name T573
Test name
Test status
Simulation time 53938309 ps
CPU time 2.24 seconds
Started Aug 02 04:47:24 PM PDT 24
Finished Aug 02 04:47:27 PM PDT 24
Peak memory 198448 kb
Host smart-6992488a-091a-41b8-b441-1bf6aa3bbeb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559322194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3559322194
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1933337339
Short name T472
Test name
Test status
Simulation time 786351079 ps
CPU time 2.88 seconds
Started Aug 02 04:47:17 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 197876 kb
Host smart-1dac3bc4-350d-41ff-80f7-b05534866ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933337339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1933337339
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3638085956
Short name T99
Test name
Test status
Simulation time 18432854 ps
CPU time 0.72 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 194684 kb
Host smart-6f8868d4-cba4-441d-acc4-290006bae664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638085956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3638085956
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1937856249
Short name T201
Test name
Test status
Simulation time 58110091 ps
CPU time 1.1 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 197608 kb
Host smart-7cb62b9d-ecca-41cc-b6ec-c74c78c86f67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937856249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1937856249
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3707493875
Short name T92
Test name
Test status
Simulation time 4521563574 ps
CPU time 5 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 198528 kb
Host smart-52b61400-71a8-4811-9048-0a54491b9c3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707493875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3707493875
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.186199034
Short name T53
Test name
Test status
Simulation time 35191250 ps
CPU time 0.87 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 214328 kb
Host smart-0cdd900d-575a-4df2-9fe8-b2fc5a8dd153
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186199034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.186199034
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1940246141
Short name T160
Test name
Test status
Simulation time 195788310 ps
CPU time 1.14 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 196196 kb
Host smart-c6b076d4-9b1f-4150-a538-a0dcf6e1fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940246141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1940246141
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3825323287
Short name T207
Test name
Test status
Simulation time 55377079 ps
CPU time 1.07 seconds
Started Aug 02 04:47:22 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 196164 kb
Host smart-f69dc804-ac9b-4b30-a1b9-fb5fe9fa1af7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825323287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3825323287
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.446212422
Short name T641
Test name
Test status
Simulation time 6289208071 ps
CPU time 158.36 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:50:06 PM PDT 24
Peak memory 198680 kb
Host smart-dea302d3-c3e2-4263-ac0a-82f2e7bc2e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446212422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.446212422
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3878006895
Short name T82
Test name
Test status
Simulation time 131793120214 ps
CPU time 1546.76 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 05:13:07 PM PDT 24
Peak memory 198744 kb
Host smart-4b1fa700-93fa-4123-b7c1-74cc22d4b161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3878006895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3878006895
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.322998898
Short name T361
Test name
Test status
Simulation time 30745794 ps
CPU time 0.58 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 195068 kb
Host smart-33057de2-8ae7-41ee-8aa5-f8116e1536a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322998898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.322998898
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1128952595
Short name T704
Test name
Test status
Simulation time 25279949 ps
CPU time 0.79 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 195856 kb
Host smart-6f74b7b9-db43-490f-9792-d1a069291e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128952595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1128952595
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1062768329
Short name T605
Test name
Test status
Simulation time 1183388669 ps
CPU time 15.04 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 198556 kb
Host smart-de37d0d4-3a4c-47c3-905a-6c1275d5afd5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062768329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1062768329
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2029853229
Short name T604
Test name
Test status
Simulation time 171455898 ps
CPU time 0.74 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 195216 kb
Host smart-a8dc6bd7-bcb4-4007-ac6a-2ca4cefa8717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029853229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2029853229
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1793345087
Short name T292
Test name
Test status
Simulation time 19750433 ps
CPU time 0.66 seconds
Started Aug 02 04:48:13 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 194784 kb
Host smart-5f101fa7-d58f-4865-97d0-0b5a1024c28e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793345087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1793345087
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3913507400
Short name T296
Test name
Test status
Simulation time 46316043 ps
CPU time 1.76 seconds
Started Aug 02 04:47:59 PM PDT 24
Finished Aug 02 04:48:01 PM PDT 24
Peak memory 198488 kb
Host smart-db4b3cdf-219a-47fe-bf27-5677e79efce1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913507400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3913507400
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3222037076
Short name T162
Test name
Test status
Simulation time 83500114 ps
CPU time 1.26 seconds
Started Aug 02 04:48:05 PM PDT 24
Finished Aug 02 04:48:06 PM PDT 24
Peak memory 196488 kb
Host smart-03eec0bf-b171-4058-b939-0418e5dc5bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222037076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3222037076
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1160819893
Short name T330
Test name
Test status
Simulation time 95395321 ps
CPU time 1.1 seconds
Started Aug 02 04:47:58 PM PDT 24
Finished Aug 02 04:47:59 PM PDT 24
Peak memory 196312 kb
Host smart-32f1d384-82fb-4809-97cd-978e2c33e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160819893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1160819893
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3821894392
Short name T586
Test name
Test status
Simulation time 48217472 ps
CPU time 0.83 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 196456 kb
Host smart-6eedc3e7-d419-456d-badb-23009aefe8bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821894392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3821894392
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.566356733
Short name T346
Test name
Test status
Simulation time 1342813788 ps
CPU time 5.72 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 198476 kb
Host smart-03d00867-71d9-4171-b957-8367fa73a0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566356733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.566356733
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.613229834
Short name T677
Test name
Test status
Simulation time 88388855 ps
CPU time 0.97 seconds
Started Aug 02 04:48:05 PM PDT 24
Finished Aug 02 04:48:06 PM PDT 24
Peak memory 196128 kb
Host smart-00eba618-4eeb-4966-a5bf-5738916f300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613229834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.613229834
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3147920630
Short name T483
Test name
Test status
Simulation time 41653655 ps
CPU time 1.01 seconds
Started Aug 02 04:48:04 PM PDT 24
Finished Aug 02 04:48:05 PM PDT 24
Peak memory 196316 kb
Host smart-6d545ce6-08b6-4e95-989a-9cfeb69fc105
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147920630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3147920630
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.175415926
Short name T587
Test name
Test status
Simulation time 59788383777 ps
CPU time 207.88 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:51:44 PM PDT 24
Peak memory 198732 kb
Host smart-361a8ffc-4ac7-4188-8c9a-e2210a9a32a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175415926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.175415926
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2576075787
Short name T438
Test name
Test status
Simulation time 191277389212 ps
CPU time 869.39 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 05:02:41 PM PDT 24
Peak memory 198864 kb
Host smart-aae2190d-9096-4e37-8905-c8d1f64047a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2576075787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2576075787
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1286067866
Short name T57
Test name
Test status
Simulation time 11890341 ps
CPU time 0.56 seconds
Started Aug 02 04:48:13 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 195060 kb
Host smart-4ca85363-b00d-459b-845e-b9c25149f961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286067866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1286067866
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2666282302
Short name T557
Test name
Test status
Simulation time 62173236 ps
CPU time 0.61 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 194248 kb
Host smart-6ed131ba-a07f-40af-84a9-abb8516b0b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666282302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2666282302
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1436240261
Short name T66
Test name
Test status
Simulation time 145636323 ps
CPU time 4.73 seconds
Started Aug 02 04:48:09 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 196424 kb
Host smart-3fdf662d-43e0-4d1c-9642-a2c00d4d12de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436240261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1436240261
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3032550573
Short name T572
Test name
Test status
Simulation time 74687290 ps
CPU time 0.95 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 196556 kb
Host smart-8d4d2a76-c9d0-4bf9-8371-6ffc656dd5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032550573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3032550573
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1479133980
Short name T471
Test name
Test status
Simulation time 206873994 ps
CPU time 0.88 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 197716 kb
Host smart-c35210a8-cb88-4481-8368-7d1157ac8ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479133980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1479133980
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4123443149
Short name T252
Test name
Test status
Simulation time 200923383 ps
CPU time 2.07 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 198464 kb
Host smart-9a93a09c-c144-4355-bce2-a024673f4257
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123443149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4123443149
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4285658274
Short name T694
Test name
Test status
Simulation time 43837479 ps
CPU time 1.19 seconds
Started Aug 02 04:47:59 PM PDT 24
Finished Aug 02 04:48:00 PM PDT 24
Peak memory 196256 kb
Host smart-779d00fa-d49b-46d0-8a8e-cdcb687b07c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285658274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4285658274
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.891254513
Short name T476
Test name
Test status
Simulation time 58280310 ps
CPU time 1.12 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 196904 kb
Host smart-b079c0b4-2031-44bf-9d24-23215a12fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891254513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.891254513
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2084874373
Short name T584
Test name
Test status
Simulation time 40091468 ps
CPU time 0.72 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 195708 kb
Host smart-257a56fc-2eca-40da-91af-e2266757b1eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084874373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2084874373
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3902915663
Short name T574
Test name
Test status
Simulation time 343071417 ps
CPU time 5.71 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 198496 kb
Host smart-d4627618-634d-4726-8681-419f6e258d31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902915663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3902915663
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3701028894
Short name T353
Test name
Test status
Simulation time 47683357 ps
CPU time 1.3 seconds
Started Aug 02 04:48:10 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 198476 kb
Host smart-21afc301-ccd7-414b-aafc-02d08f3183c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701028894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3701028894
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2083304111
Short name T456
Test name
Test status
Simulation time 178203954 ps
CPU time 1.45 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 198592 kb
Host smart-42eb8902-5c0f-4e7b-8fe2-69edc8d33200
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083304111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2083304111
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3511845667
Short name T329
Test name
Test status
Simulation time 8486980221 ps
CPU time 46.44 seconds
Started Aug 02 04:48:13 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 198640 kb
Host smart-09b645a1-ba03-4f02-b92a-d783840bff46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511845667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3511845667
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.526791932
Short name T45
Test name
Test status
Simulation time 35795861465 ps
CPU time 301.19 seconds
Started Aug 02 04:48:06 PM PDT 24
Finished Aug 02 04:53:08 PM PDT 24
Peak memory 198804 kb
Host smart-1f52f7b7-0f16-4772-a591-826bd3ed5f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=526791932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.526791932
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.762337824
Short name T599
Test name
Test status
Simulation time 27919893 ps
CPU time 0.55 seconds
Started Aug 02 04:48:06 PM PDT 24
Finished Aug 02 04:48:07 PM PDT 24
Peak memory 194448 kb
Host smart-f0a76343-527f-4cb6-b0ec-5d710aef3927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762337824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.762337824
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2436449409
Short name T278
Test name
Test status
Simulation time 478193428 ps
CPU time 0.81 seconds
Started Aug 02 04:48:02 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 195932 kb
Host smart-abd8bc8f-79c8-4f8b-975a-9c157cb8fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436449409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2436449409
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.732485478
Short name T312
Test name
Test status
Simulation time 537906578 ps
CPU time 14.23 seconds
Started Aug 02 04:48:00 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 196056 kb
Host smart-a9438b69-f5f1-4970-817d-008f06ef8bf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732485478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.732485478
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.663772426
Short name T651
Test name
Test status
Simulation time 163471117 ps
CPU time 1.02 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:10 PM PDT 24
Peak memory 197124 kb
Host smart-d7712347-af11-4555-b7c3-74dbaefa1751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663772426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.663772426
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1970257676
Short name T345
Test name
Test status
Simulation time 637724409 ps
CPU time 1.13 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 196464 kb
Host smart-74a5635e-d8ca-4b7d-a348-e5b32cf453e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970257676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1970257676
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.960161949
Short name T640
Test name
Test status
Simulation time 532906755 ps
CPU time 1.99 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 198472 kb
Host smart-70694856-81d0-44d2-848f-ebcb072d38b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960161949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.960161949
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1553824521
Short name T490
Test name
Test status
Simulation time 82407722 ps
CPU time 2.67 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:48:03 PM PDT 24
Peak memory 198528 kb
Host smart-9759978e-2ebd-49ba-a300-3fa8c7a69c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553824521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1553824521
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1788498008
Short name T178
Test name
Test status
Simulation time 165122518 ps
CPU time 1.27 seconds
Started Aug 02 04:48:07 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 196344 kb
Host smart-954031f6-85b7-43cd-a6d5-332f7b3ea37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788498008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1788498008
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.167085484
Short name T463
Test name
Test status
Simulation time 54109211 ps
CPU time 1.03 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 196448 kb
Host smart-4a789293-d468-4bfe-aee9-23370d198eb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167085484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.167085484
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.249006349
Short name T315
Test name
Test status
Simulation time 892812201 ps
CPU time 5.78 seconds
Started Aug 02 04:48:09 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 198448 kb
Host smart-fdcc41df-8e98-46a3-9bc3-8e18c074af6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249006349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.249006349
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1647338663
Short name T15
Test name
Test status
Simulation time 84639212 ps
CPU time 1.14 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 196244 kb
Host smart-37200f44-da78-4c43-8949-f8030a7e4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647338663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1647338663
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.347099072
Short name T89
Test name
Test status
Simulation time 74033898 ps
CPU time 0.8 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 195668 kb
Host smart-d7057d95-ba5f-447a-80fd-a250fa40702d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347099072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.347099072
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2386545666
Short name T528
Test name
Test status
Simulation time 48693094276 ps
CPU time 106.29 seconds
Started Aug 02 04:48:09 PM PDT 24
Finished Aug 02 04:49:55 PM PDT 24
Peak memory 198672 kb
Host smart-3cd1e241-5b19-419c-8064-aeebfaac2ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386545666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2386545666
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2640096335
Short name T150
Test name
Test status
Simulation time 239751838760 ps
CPU time 725.58 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 05:00:14 PM PDT 24
Peak memory 198752 kb
Host smart-127544c6-cb5e-4856-bda2-55fb472c12fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2640096335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2640096335
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1268237236
Short name T431
Test name
Test status
Simulation time 12139791 ps
CPU time 0.59 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 194448 kb
Host smart-44fc91e4-ca1d-4088-ac40-91b14871cd5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268237236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1268237236
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1142115853
Short name T333
Test name
Test status
Simulation time 29387306 ps
CPU time 0.84 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 197544 kb
Host smart-64616779-104e-4315-bd62-6e94c2ef20e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142115853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1142115853
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1109412844
Short name T646
Test name
Test status
Simulation time 641211219 ps
CPU time 13.37 seconds
Started Aug 02 04:48:10 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 195912 kb
Host smart-d40daee3-f114-4a65-aa8c-3f8cad68e1d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109412844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1109412844
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3902385946
Short name T467
Test name
Test status
Simulation time 47100886 ps
CPU time 0.73 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:11 PM PDT 24
Peak memory 195904 kb
Host smart-90167fcf-1f3b-4245-98b5-296a330e16b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902385946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3902385946
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1141367586
Short name T274
Test name
Test status
Simulation time 65494216 ps
CPU time 0.95 seconds
Started Aug 02 04:47:58 PM PDT 24
Finished Aug 02 04:47:59 PM PDT 24
Peak memory 196288 kb
Host smart-fc84c529-e974-46bc-b335-8f020c15a695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141367586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1141367586
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.755352387
Short name T190
Test name
Test status
Simulation time 471822554 ps
CPU time 1.94 seconds
Started Aug 02 04:48:10 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 198372 kb
Host smart-8816903a-ae28-4887-bb63-b0f82c701e13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755352387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.755352387
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1599904928
Short name T612
Test name
Test status
Simulation time 381999207 ps
CPU time 2.23 seconds
Started Aug 02 04:48:05 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 197468 kb
Host smart-980b7b3f-4b11-42fe-99c1-4988a7f53462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599904928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1599904928
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3278494641
Short name T349
Test name
Test status
Simulation time 62143560 ps
CPU time 0.88 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 196892 kb
Host smart-eaec4b19-363c-40a0-9097-9a3374c55bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278494641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3278494641
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3941535148
Short name T219
Test name
Test status
Simulation time 52430781 ps
CPU time 0.87 seconds
Started Aug 02 04:48:04 PM PDT 24
Finished Aug 02 04:48:05 PM PDT 24
Peak memory 196496 kb
Host smart-c18e5f55-c68e-48d7-a75c-df930371d2df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941535148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3941535148
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.363510895
Short name T567
Test name
Test status
Simulation time 542594140 ps
CPU time 2.3 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 198368 kb
Host smart-536737ff-daeb-4a31-8c57-963cc995e2ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363510895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.363510895
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1445055628
Short name T601
Test name
Test status
Simulation time 95436580 ps
CPU time 1.35 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 197280 kb
Host smart-2066eb12-8a2e-439c-9faf-6619a92a0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445055628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1445055628
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3896936461
Short name T565
Test name
Test status
Simulation time 135704767 ps
CPU time 0.99 seconds
Started Aug 02 04:48:03 PM PDT 24
Finished Aug 02 04:48:04 PM PDT 24
Peak memory 196216 kb
Host smart-51b9c4ba-3e1a-4baa-b389-4b59224431f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896936461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3896936461
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1533337909
Short name T575
Test name
Test status
Simulation time 8965365904 ps
CPU time 117.01 seconds
Started Aug 02 04:48:01 PM PDT 24
Finished Aug 02 04:49:58 PM PDT 24
Peak memory 198688 kb
Host smart-2df5a98e-071c-4647-ab7c-a76ffde50465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533337909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1533337909
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2318867758
Short name T658
Test name
Test status
Simulation time 13480487261 ps
CPU time 297.88 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:53:13 PM PDT 24
Peak memory 198696 kb
Host smart-d10785f4-7d8b-43f3-ade6-e4891cd3e1ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2318867758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2318867758
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2252602167
Short name T199
Test name
Test status
Simulation time 12895902 ps
CPU time 0.57 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 194544 kb
Host smart-e4032ade-1c04-4d24-b587-6f277bceb620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252602167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2252602167
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4104976373
Short name T374
Test name
Test status
Simulation time 174871895 ps
CPU time 0.59 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 194252 kb
Host smart-d99499e4-a08c-4bca-84bb-0bdf06f9f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104976373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4104976373
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2256780688
Short name T169
Test name
Test status
Simulation time 825153735 ps
CPU time 21.36 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 197288 kb
Host smart-236e4b4b-2951-4482-b77e-255d4c85ed1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256780688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2256780688
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.175249090
Short name T115
Test name
Test status
Simulation time 45279925 ps
CPU time 0.67 seconds
Started Aug 02 04:48:08 PM PDT 24
Finished Aug 02 04:48:09 PM PDT 24
Peak memory 195580 kb
Host smart-b47d5748-4a7a-4626-8b59-87447185eef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175249090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.175249090
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.97811039
Short name T676
Test name
Test status
Simulation time 245359593 ps
CPU time 1.02 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 197264 kb
Host smart-37d78360-7958-42b7-832d-2fd378e15e81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97811039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.97811039
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3972964240
Short name T224
Test name
Test status
Simulation time 389414427 ps
CPU time 2.06 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 198700 kb
Host smart-59b71d76-a2b7-4a5b-ae54-731d7a698bc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972964240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3972964240
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3102312364
Short name T388
Test name
Test status
Simulation time 132224723 ps
CPU time 2.45 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 197664 kb
Host smart-58da060f-20dd-49f4-8c5f-39d1d4b33f21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102312364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3102312364
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.769196296
Short name T27
Test name
Test status
Simulation time 69262244 ps
CPU time 1.24 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:15 PM PDT 24
Peak memory 198260 kb
Host smart-8999be4a-2e57-4fad-a13b-80a524c0dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769196296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.769196296
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3602299974
Short name T550
Test name
Test status
Simulation time 167597999 ps
CPU time 1.11 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 196532 kb
Host smart-a2b1709c-f2da-414c-a24b-6b677cb415ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602299974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3602299974
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2848904282
Short name T357
Test name
Test status
Simulation time 377328226 ps
CPU time 4.3 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 198596 kb
Host smart-6fc330f8-c558-45c5-839f-7469a494d0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848904282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2848904282
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1117412926
Short name T376
Test name
Test status
Simulation time 37316574 ps
CPU time 1.19 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 196720 kb
Host smart-78fc5aae-b5cd-4f44-8b0d-891b420aad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117412926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1117412926
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3455322007
Short name T323
Test name
Test status
Simulation time 97304402 ps
CPU time 1.43 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 197040 kb
Host smart-9af4e454-ce33-48d7-8dc2-de8d701e3eaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455322007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3455322007
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.766960343
Short name T643
Test name
Test status
Simulation time 71976041533 ps
CPU time 178.2 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:51:17 PM PDT 24
Peak memory 198572 kb
Host smart-50ec9952-c733-44bc-ad3e-4d7e40542b98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766960343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.766960343
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3202350501
Short name T457
Test name
Test status
Simulation time 524244625401 ps
CPU time 1785.97 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 05:17:59 PM PDT 24
Peak memory 198768 kb
Host smart-29e2101b-696a-47a2-abc8-f9b6c15ddffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3202350501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3202350501
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2307059189
Short name T420
Test name
Test status
Simulation time 42121000 ps
CPU time 0.56 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 194564 kb
Host smart-a8831396-9b23-4676-85c2-085af9d04f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307059189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2307059189
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.955688762
Short name T282
Test name
Test status
Simulation time 183860488 ps
CPU time 0.66 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 195308 kb
Host smart-7e7ba86f-2377-4ee7-8493-eb6531089d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955688762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.955688762
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2304366122
Short name T603
Test name
Test status
Simulation time 698170786 ps
CPU time 24.14 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:40 PM PDT 24
Peak memory 197372 kb
Host smart-da4a8b95-ac2c-40b9-b9cf-21ad4b016f47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304366122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2304366122
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3563204339
Short name T661
Test name
Test status
Simulation time 84581121 ps
CPU time 0.63 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 194788 kb
Host smart-4d59fa28-fb3a-4c9a-92d9-8cb7169267d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563204339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3563204339
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3858788058
Short name T246
Test name
Test status
Simulation time 54433878 ps
CPU time 0.99 seconds
Started Aug 02 04:48:13 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 197044 kb
Host smart-77ad7688-873e-4d24-89b7-5170a3d6c4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858788058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3858788058
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4257111344
Short name T253
Test name
Test status
Simulation time 201774975 ps
CPU time 2.12 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 198444 kb
Host smart-c60f8f47-dd5e-4902-9f4e-319594423de9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257111344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4257111344
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2709826706
Short name T480
Test name
Test status
Simulation time 249803334 ps
CPU time 1.71 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 196548 kb
Host smart-3795de43-c8a2-4d37-aa9d-aed9866cf6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709826706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2709826706
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2055399641
Short name T363
Test name
Test status
Simulation time 73520688 ps
CPU time 0.72 seconds
Started Aug 02 04:48:10 PM PDT 24
Finished Aug 02 04:48:11 PM PDT 24
Peak memory 195932 kb
Host smart-e94f03c1-03f4-4efc-9cae-32449ba200ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055399641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2055399641
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.767354934
Short name T385
Test name
Test status
Simulation time 69263558 ps
CPU time 1.35 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 197412 kb
Host smart-d3234d00-50d8-4c9b-a1f0-beca4bb13b0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767354934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.767354934
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2689159189
Short name T627
Test name
Test status
Simulation time 400342646 ps
CPU time 4.4 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 198464 kb
Host smart-947048a5-b0cf-4518-89c7-349426f849e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689159189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2689159189
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.431729528
Short name T366
Test name
Test status
Simulation time 204281507 ps
CPU time 1 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 196224 kb
Host smart-45256cf6-578f-499c-82b6-5ffa960f91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431729528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.431729528
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3677484661
Short name T113
Test name
Test status
Simulation time 275888705 ps
CPU time 1.23 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 196244 kb
Host smart-b54cce4c-7135-46f0-8f3b-7d3b7affb76e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677484661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3677484661
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1659778789
Short name T703
Test name
Test status
Simulation time 99735798459 ps
CPU time 198.77 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:51:37 PM PDT 24
Peak memory 198556 kb
Host smart-8d365a43-f2fe-4e5f-9d91-6004d0d0b253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659778789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1659778789
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1211564234
Short name T689
Test name
Test status
Simulation time 54568106494 ps
CPU time 227.75 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:52:10 PM PDT 24
Peak memory 198828 kb
Host smart-74681418-5392-4bba-b2f2-4b56ead0d92c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1211564234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1211564234
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1734827759
Short name T248
Test name
Test status
Simulation time 42385542 ps
CPU time 0.6 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 194536 kb
Host smart-f2f60da0-f651-4893-861b-fdd365eda5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734827759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1734827759
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.649044062
Short name T74
Test name
Test status
Simulation time 14511854 ps
CPU time 0.63 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 195212 kb
Host smart-777a0d3f-e691-46dc-ae74-45d28ee19b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649044062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.649044062
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.993760584
Short name T249
Test name
Test status
Simulation time 1651426882 ps
CPU time 25.59 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:36 PM PDT 24
Peak memory 197552 kb
Host smart-62539bbb-c167-4f8a-81e8-599fba9eb61f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993760584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.993760584
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2221424272
Short name T262
Test name
Test status
Simulation time 67971202 ps
CPU time 0.68 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:19 PM PDT 24
Peak memory 195824 kb
Host smart-7d3cc9b8-358a-42c3-80f8-8b4f3f85d98b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221424272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2221424272
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1075547327
Short name T445
Test name
Test status
Simulation time 35701757 ps
CPU time 0.79 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 196560 kb
Host smart-5c4b9940-93eb-407b-8b80-feb6eabff982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075547327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1075547327
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3094145262
Short name T322
Test name
Test status
Simulation time 154240750 ps
CPU time 1.57 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 198536 kb
Host smart-9494af3d-f033-4807-81df-4397d0504cc5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094145262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3094145262
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.197614330
Short name T582
Test name
Test status
Simulation time 95151628 ps
CPU time 2.77 seconds
Started Aug 02 04:48:13 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 197700 kb
Host smart-7acefcbc-83cb-4cbf-9076-52bac79c6790
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197614330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
197614330
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2077000294
Short name T491
Test name
Test status
Simulation time 18941205 ps
CPU time 0.73 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 196600 kb
Host smart-f4ba166f-fc46-4824-8fac-5f79ce4f380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077000294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2077000294
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.936167600
Short name T440
Test name
Test status
Simulation time 189942805 ps
CPU time 1.18 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 197548 kb
Host smart-984f9a30-2f75-4868-8294-ccd1086e9088
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936167600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.936167600
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.97248413
Short name T215
Test name
Test status
Simulation time 352950783 ps
CPU time 5.37 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 198504 kb
Host smart-52b5d834-ff21-40e6-8569-356691e891ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97248413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand
om_long_reg_writes_reg_reads.97248413
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2430836176
Short name T639
Test name
Test status
Simulation time 113026398 ps
CPU time 1.07 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 197000 kb
Host smart-1badd4d7-c632-4ad1-a44a-981190dbb19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430836176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2430836176
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2310166576
Short name T354
Test name
Test status
Simulation time 83985815 ps
CPU time 1.25 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 197332 kb
Host smart-727df88d-d63b-4fb8-b9ec-f66d0db25f2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310166576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2310166576
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4104255852
Short name T324
Test name
Test status
Simulation time 17751862210 ps
CPU time 204.96 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:51:41 PM PDT 24
Peak memory 198700 kb
Host smart-4f06d87e-925b-4033-bb3c-36f5d696d969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104255852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4104255852
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3846524914
Short name T270
Test name
Test status
Simulation time 28236690 ps
CPU time 0.57 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:19 PM PDT 24
Peak memory 194472 kb
Host smart-d8140404-fa16-4f50-9336-a97548963b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846524914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3846524914
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4158377765
Short name T227
Test name
Test status
Simulation time 21107059 ps
CPU time 0.6 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 194264 kb
Host smart-e63433d2-311c-4b61-b090-4fd9002fb1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158377765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4158377765
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.968607494
Short name T226
Test name
Test status
Simulation time 675274381 ps
CPU time 22.24 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 198548 kb
Host smart-774e8308-09d5-4acf-a64e-52a4f5e3385f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968607494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.968607494
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3791635001
Short name T563
Test name
Test status
Simulation time 84010477 ps
CPU time 0.77 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 196276 kb
Host smart-f0ede9fa-3778-42c3-a258-56fe35858d5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791635001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3791635001
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2494205662
Short name T525
Test name
Test status
Simulation time 78722662 ps
CPU time 1.19 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 196684 kb
Host smart-5148d799-ea62-41e4-a3c3-d363c8b7d90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494205662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2494205662
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1623810156
Short name T240
Test name
Test status
Simulation time 424806248 ps
CPU time 2.8 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 196684 kb
Host smart-e5d5fd6e-38ee-4340-979d-b5945e594358
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623810156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1623810156
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3518058331
Short name T516
Test name
Test status
Simulation time 124631415 ps
CPU time 3.46 seconds
Started Aug 02 04:48:14 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 198528 kb
Host smart-f1db7c7f-dc83-4dd8-baf3-9d9916c9a661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518058331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3518058331
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1259240130
Short name T534
Test name
Test status
Simulation time 23236606 ps
CPU time 0.68 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:19 PM PDT 24
Peak memory 194836 kb
Host smart-cf32a60b-aad6-4669-b278-0ed88f7587c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259240130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1259240130
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1258879315
Short name T608
Test name
Test status
Simulation time 848919260 ps
CPU time 2.75 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 198448 kb
Host smart-872ce9d6-9d8f-4988-9d12-c5fa7ab79ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258879315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1258879315
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3658637198
Short name T499
Test name
Test status
Simulation time 139620459 ps
CPU time 1.15 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 196236 kb
Host smart-243beea7-871d-4c12-8fd3-511c5292964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658637198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3658637198
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3009376573
Short name T538
Test name
Test status
Simulation time 264266605 ps
CPU time 1.27 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 196860 kb
Host smart-351a1d3c-9beb-46b7-aa37-f14a84d5db1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009376573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3009376573
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3435085529
Short name T549
Test name
Test status
Simulation time 15763386724 ps
CPU time 166.37 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:51:03 PM PDT 24
Peak memory 198476 kb
Host smart-aaf34f70-57c7-46ed-be39-61940b6809ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435085529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3435085529
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2354888572
Short name T589
Test name
Test status
Simulation time 14571709 ps
CPU time 0.58 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 195448 kb
Host smart-afb36f7a-4da4-43d6-847d-35ae76c36a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354888572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2354888572
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3599304802
Short name T461
Test name
Test status
Simulation time 14387429 ps
CPU time 0.63 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 194344 kb
Host smart-b9adadfc-3977-4110-8120-cd669e81dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599304802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3599304802
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3789317760
Short name T540
Test name
Test status
Simulation time 4829465871 ps
CPU time 22.72 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 197280 kb
Host smart-426d5288-abaf-46b8-b0e8-9c752acb7537
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789317760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3789317760
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1623564376
Short name T402
Test name
Test status
Simulation time 27064782 ps
CPU time 0.67 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 195016 kb
Host smart-84c0b947-746a-446c-a1a0-316ac8d8273a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623564376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1623564376
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2586334953
Short name T237
Test name
Test status
Simulation time 53334988 ps
CPU time 0.95 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 197160 kb
Host smart-146f3ebd-cedb-4ab0-8e7e-5f24379c5596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586334953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2586334953
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1277401700
Short name T428
Test name
Test status
Simulation time 35578723 ps
CPU time 1.47 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 197416 kb
Host smart-b4da6682-b92b-4d6d-9681-5a8e737822df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277401700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1277401700
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.88503155
Short name T520
Test name
Test status
Simulation time 58233328 ps
CPU time 0.92 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 196016 kb
Host smart-01f6be63-8470-4028-9f76-2d72fdf1506f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88503155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.88503155
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.636593097
Short name T332
Test name
Test status
Simulation time 29889126 ps
CPU time 1.05 seconds
Started Aug 02 04:48:10 PM PDT 24
Finished Aug 02 04:48:11 PM PDT 24
Peak memory 197136 kb
Host smart-b06154b6-8698-4ccc-b5db-6bd59dc44022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636593097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.636593097
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2550264653
Short name T559
Test name
Test status
Simulation time 95372022 ps
CPU time 1.13 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:19 PM PDT 24
Peak memory 196656 kb
Host smart-abfe081c-bdde-4874-bc17-4b6f06190f5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550264653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2550264653
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3711284223
Short name T478
Test name
Test status
Simulation time 737309400 ps
CPU time 5.27 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 198436 kb
Host smart-2a1c241d-2e3a-4438-8296-6f8a4bc2e313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711284223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3711284223
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.624300766
Short name T108
Test name
Test status
Simulation time 53741164 ps
CPU time 1.05 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:18 PM PDT 24
Peak memory 197020 kb
Host smart-f2eb4ab5-2f96-4020-a2ba-782e6dbfd68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624300766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.624300766
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1925505284
Short name T434
Test name
Test status
Simulation time 70703528 ps
CPU time 0.87 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:12 PM PDT 24
Peak memory 196844 kb
Host smart-6bde7c87-0fb1-4d5a-8cc9-31e3fb992b3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925505284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1925505284
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1246972827
Short name T314
Test name
Test status
Simulation time 57740062852 ps
CPU time 170.35 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:51:07 PM PDT 24
Peak memory 198784 kb
Host smart-d9bcf3a1-bcb2-44be-89e4-09ea1c690b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246972827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1246972827
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1611057937
Short name T523
Test name
Test status
Simulation time 37207197 ps
CPU time 0.57 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 194544 kb
Host smart-63916f61-60c2-4393-bb04-2776ca1cb650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611057937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1611057937
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2554868570
Short name T175
Test name
Test status
Simulation time 99935893 ps
CPU time 0.75 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 195640 kb
Host smart-0d521300-b9be-4737-a462-2ec7a1ebc3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554868570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2554868570
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.192778689
Short name T492
Test name
Test status
Simulation time 313828557 ps
CPU time 10.51 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198404 kb
Host smart-657b4d6f-54c4-473d-9b57-550b1cf70d9e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192778689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.192778689
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2770761685
Short name T430
Test name
Test status
Simulation time 273588947 ps
CPU time 0.92 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 197676 kb
Host smart-b8e06112-731b-4b71-8d53-0727887ae940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770761685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2770761685
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2755529225
Short name T260
Test name
Test status
Simulation time 77290437 ps
CPU time 0.86 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 196056 kb
Host smart-01a78316-b330-4906-87d1-d708662739d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755529225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2755529225
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2749519256
Short name T693
Test name
Test status
Simulation time 521165965 ps
CPU time 2.73 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 196788 kb
Host smart-62afff45-db7d-44ab-b74f-95bae36007d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749519256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2749519256
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4234362090
Short name T509
Test name
Test status
Simulation time 193696720 ps
CPU time 3.01 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 197712 kb
Host smart-9a7dc13f-84a3-4703-832b-3ff8b5a8cad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234362090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4234362090
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4154444383
Short name T131
Test name
Test status
Simulation time 20476909 ps
CPU time 0.8 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 195952 kb
Host smart-d4dcf0e2-02ca-4b0a-817f-6e2300a56a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154444383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4154444383
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1819241482
Short name T91
Test name
Test status
Simulation time 38759717 ps
CPU time 0.92 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 196380 kb
Host smart-956be559-ba06-460c-ae0a-4f01944253de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819241482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1819241482
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1788108776
Short name T488
Test name
Test status
Simulation time 75208728 ps
CPU time 3.4 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 198440 kb
Host smart-31d6f893-dffe-4446-8eb6-04116be73990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788108776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1788108776
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1547825468
Short name T223
Test name
Test status
Simulation time 49023952 ps
CPU time 0.99 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 196976 kb
Host smart-31132ec8-bee4-480a-ac05-c0e313317806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547825468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1547825468
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3694218391
Short name T508
Test name
Test status
Simulation time 132660586 ps
CPU time 1.42 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 197240 kb
Host smart-46cd91ba-d1d3-40c3-9d01-e7aee8f157ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694218391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3694218391
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2438226169
Short name T391
Test name
Test status
Simulation time 14991553952 ps
CPU time 183.36 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:51:27 PM PDT 24
Peak memory 198596 kb
Host smart-bff36f85-ecb5-43dd-acd9-d1ebdd5fb6cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438226169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2438226169
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.805652912
Short name T425
Test name
Test status
Simulation time 74919617373 ps
CPU time 306.12 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:53:34 PM PDT 24
Peak memory 198748 kb
Host smart-d5213430-224b-4698-94e2-d68b51171523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=805652912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.805652912
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.147481187
Short name T56
Test name
Test status
Simulation time 49256097 ps
CPU time 0.6 seconds
Started Aug 02 04:47:16 PM PDT 24
Finished Aug 02 04:47:17 PM PDT 24
Peak memory 194476 kb
Host smart-53d49337-4642-4bcc-8cf2-df9a18d197b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147481187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.147481187
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2789632529
Short name T229
Test name
Test status
Simulation time 310272537 ps
CPU time 0.92 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 197052 kb
Host smart-edf0a0e1-f4d2-4c7c-8b4b-3ff6d801945f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789632529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2789632529
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1697327957
Short name T648
Test name
Test status
Simulation time 105506027 ps
CPU time 5.6 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:27 PM PDT 24
Peak memory 198496 kb
Host smart-6f3350ac-4f40-4e59-86a3-091be8896204
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697327957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1697327957
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2446688029
Short name T198
Test name
Test status
Simulation time 136176827 ps
CPU time 0.99 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 197016 kb
Host smart-09bac7d4-b97d-4c0d-be92-9bfd77a655ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446688029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2446688029
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2343842173
Short name T360
Test name
Test status
Simulation time 50657734 ps
CPU time 1 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 196408 kb
Host smart-c88fa169-d706-424a-a77e-8060afa6d60e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343842173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2343842173
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2433592642
Short name T28
Test name
Test status
Simulation time 365746237 ps
CPU time 3.68 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:25 PM PDT 24
Peak memory 198444 kb
Host smart-8dcd6e31-1ecc-4813-9af1-c7686562a046
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433592642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2433592642
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.139156819
Short name T383
Test name
Test status
Simulation time 299072429 ps
CPU time 1.88 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 196464 kb
Host smart-9de10157-0e2b-4eb7-b9e4-959e6a00e7ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139156819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.139156819
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3778310802
Short name T532
Test name
Test status
Simulation time 178853855 ps
CPU time 0.94 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 196336 kb
Host smart-115619ee-34d3-45c0-97c5-d2155d42589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778310802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3778310802
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1037247909
Short name T498
Test name
Test status
Simulation time 41516084 ps
CPU time 1.06 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 197212 kb
Host smart-c3a204d6-396f-4b0f-8562-dc067e0d260b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037247909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1037247909
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.740962978
Short name T313
Test name
Test status
Simulation time 215195074 ps
CPU time 4.36 seconds
Started Aug 02 04:47:17 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 198420 kb
Host smart-fc4c876e-10ed-419b-9b24-20b16627e31a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740962978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.740962978
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3016642524
Short name T52
Test name
Test status
Simulation time 328604383 ps
CPU time 0.92 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 215460 kb
Host smart-c25fb91d-e8f3-4c48-ba4e-16164374bc9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016642524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3016642524
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2017633689
Short name T418
Test name
Test status
Simulation time 30853559 ps
CPU time 0.89 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 195800 kb
Host smart-9f7dda6c-6c2f-48ee-8077-a3bdeebda9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017633689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2017633689
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3931147096
Short name T558
Test name
Test status
Simulation time 129612423 ps
CPU time 1.08 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 196104 kb
Host smart-d6e3193c-42e5-4ef6-83dc-78958db942e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931147096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3931147096
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2212532226
Short name T3
Test name
Test status
Simulation time 9682152842 ps
CPU time 103.92 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:49:03 PM PDT 24
Peak memory 198640 kb
Host smart-570c863d-7d33-4383-8143-6d4c665bed01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212532226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2212532226
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3630265912
Short name T47
Test name
Test status
Simulation time 140740326008 ps
CPU time 2462.09 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 198916 kb
Host smart-a5f7cdda-9a2b-4cc9-b1f1-b3a9d8749841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3630265912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3630265912
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.411217444
Short name T614
Test name
Test status
Simulation time 50303593 ps
CPU time 0.6 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 194556 kb
Host smart-a5370763-8b56-4266-b913-e6a060acf402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411217444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.411217444
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1979046321
Short name T378
Test name
Test status
Simulation time 113647558 ps
CPU time 0.84 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 197636 kb
Host smart-a3aaa6b1-8cd6-4227-ac24-d3a3e50cae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979046321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1979046321
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1208077675
Short name T522
Test name
Test status
Simulation time 226537356 ps
CPU time 6.49 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 198368 kb
Host smart-0c29a671-048b-48fc-a363-8801b5ad1a3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208077675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1208077675
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3536402674
Short name T256
Test name
Test status
Simulation time 340287996 ps
CPU time 1.09 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 197048 kb
Host smart-1eb4f284-ae14-4189-95be-ab69b2035899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536402674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3536402674
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3609810144
Short name T271
Test name
Test status
Simulation time 130363814 ps
CPU time 1.17 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:16 PM PDT 24
Peak memory 196480 kb
Host smart-a4d57100-6705-4af2-98f6-6bc897beb364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609810144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3609810144
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2917235375
Short name T477
Test name
Test status
Simulation time 223445511 ps
CPU time 3.63 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 198508 kb
Host smart-f5c33e55-75f9-40bd-9f14-df09c51b563f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917235375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2917235375
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1111056244
Short name T293
Test name
Test status
Simulation time 68043963 ps
CPU time 1.62 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196340 kb
Host smart-76dd836b-6e89-4951-84f0-b7a6a5e0ec6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111056244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1111056244
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2455280972
Short name T359
Test name
Test status
Simulation time 24161803 ps
CPU time 1 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 196288 kb
Host smart-5f0c13a9-ba93-40e4-b10e-06eb609d2dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455280972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2455280972
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2635745735
Short name T435
Test name
Test status
Simulation time 17377387 ps
CPU time 0.83 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 196436 kb
Host smart-38bbda10-f3f9-48ce-ac5d-063cfffaaa26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635745735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2635745735
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2013371431
Short name T290
Test name
Test status
Simulation time 742292257 ps
CPU time 3.15 seconds
Started Aug 02 04:48:18 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 198416 kb
Host smart-365b3a2d-22a1-4bfe-ade6-b59df0fc6a41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013371431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2013371431
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.643543035
Short name T168
Test name
Test status
Simulation time 53397314 ps
CPU time 1.04 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 196376 kb
Host smart-be33f0cb-88d1-4d9d-98c3-aa1c18ff3880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643543035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.643543035
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.531095576
Short name T664
Test name
Test status
Simulation time 140551875 ps
CPU time 1.29 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 197208 kb
Host smart-0bda6fc6-0a10-44aa-b135-5cc65c9823c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531095576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.531095576
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.112951891
Short name T699
Test name
Test status
Simulation time 65444700598 ps
CPU time 176.32 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:51:22 PM PDT 24
Peak memory 198636 kb
Host smart-621ac6de-9e11-4b81-950d-7db834ea1d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112951891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.112951891
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2838843758
Short name T165
Test name
Test status
Simulation time 32384579 ps
CPU time 0.56 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:21 PM PDT 24
Peak memory 194384 kb
Host smart-fe78fda1-ab2d-4a87-9edf-2ae8c39b91ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838843758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2838843758
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3408420407
Short name T213
Test name
Test status
Simulation time 110383885 ps
CPU time 0.76 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 195748 kb
Host smart-a4622fc4-ece2-48b5-8b74-3e56e800efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408420407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3408420407
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1725724026
Short name T695
Test name
Test status
Simulation time 7429129879 ps
CPU time 27.04 seconds
Started Aug 02 04:48:16 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 197436 kb
Host smart-eafd0b74-aefa-46c2-abc8-1816be47d6c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725724026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1725724026
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.162851299
Short name T553
Test name
Test status
Simulation time 179791029 ps
CPU time 0.82 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 197016 kb
Host smart-0630914a-b3bf-43c9-9cdf-6c80c147cbb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162851299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.162851299
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3960215524
Short name T145
Test name
Test status
Simulation time 126642546 ps
CPU time 1.34 seconds
Started Aug 02 04:48:20 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 197020 kb
Host smart-55e04548-1a63-448e-a0d8-cf5979fe50a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960215524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3960215524
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1642758482
Short name T206
Test name
Test status
Simulation time 302753706 ps
CPU time 3.25 seconds
Started Aug 02 04:48:11 PM PDT 24
Finished Aug 02 04:48:14 PM PDT 24
Peak memory 198532 kb
Host smart-34f98a09-b285-430e-901d-8a0a47968ab8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642758482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1642758482
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3848388570
Short name T259
Test name
Test status
Simulation time 145458397 ps
CPU time 2.82 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:48:22 PM PDT 24
Peak memory 198560 kb
Host smart-adb872c9-6857-44a8-a3e1-0814237bc155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848388570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3848388570
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1663808733
Short name T142
Test name
Test status
Simulation time 21372158 ps
CPU time 0.7 seconds
Started Aug 02 04:48:19 PM PDT 24
Finished Aug 02 04:48:20 PM PDT 24
Peak memory 195640 kb
Host smart-3eac4b1a-dd6e-4993-bf08-db73ae70287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663808733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1663808733
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.602799877
Short name T623
Test name
Test status
Simulation time 106016594 ps
CPU time 1.1 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 197080 kb
Host smart-b6483e07-b1de-44db-9d79-c8afd8d32e70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602799877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.602799877
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1243342130
Short name T112
Test name
Test status
Simulation time 527645945 ps
CPU time 1.35 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 198492 kb
Host smart-302bceac-aa1e-4fa6-b3a6-8a78690b6bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243342130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1243342130
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2678382431
Short name T309
Test name
Test status
Simulation time 89959542 ps
CPU time 0.8 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 195760 kb
Host smart-fdf17f42-a6cf-4858-8dc0-e1dd458e453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678382431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2678382431
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3245666589
Short name T690
Test name
Test status
Simulation time 123015051 ps
CPU time 1.03 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:23 PM PDT 24
Peak memory 196316 kb
Host smart-22f7b163-1c14-4820-97a7-6b4b0e0ee05c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245666589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3245666589
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.757016995
Short name T10
Test name
Test status
Simulation time 22246664333 ps
CPU time 139.41 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:50:43 PM PDT 24
Peak memory 198636 kb
Host smart-7d2ca693-ec43-45ad-9cd6-8bf186f1e880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757016995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.757016995
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1230340696
Short name T496
Test name
Test status
Simulation time 61330242917 ps
CPU time 1529.4 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 198788 kb
Host smart-46d05642-2120-4b1f-a29b-e488e7b7e09f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1230340696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1230340696
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2226305923
Short name T214
Test name
Test status
Simulation time 25040509 ps
CPU time 0.62 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 195020 kb
Host smart-107db278-8dab-44a9-9021-8d065f4d57d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226305923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2226305923
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1668013192
Short name T126
Test name
Test status
Simulation time 244436364 ps
CPU time 0.74 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 194552 kb
Host smart-9988d1fd-4de0-4a7e-bdeb-3321cb0f5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668013192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1668013192
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3456655197
Short name T75
Test name
Test status
Simulation time 1482736158 ps
CPU time 18.89 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 197188 kb
Host smart-31c84a70-451e-4d9f-b715-91e92b83f277
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456655197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3456655197
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1945367531
Short name T511
Test name
Test status
Simulation time 581818145 ps
CPU time 1.04 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 197156 kb
Host smart-fa2ace88-fdc8-41f1-a42d-00845842c08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945367531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1945367531
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2715154356
Short name T39
Test name
Test status
Simulation time 208881428 ps
CPU time 1.49 seconds
Started Aug 02 04:48:15 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 198508 kb
Host smart-61b09772-de1d-446c-9c3a-46ec22237f80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715154356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2715154356
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.859369472
Short name T179
Test name
Test status
Simulation time 19308154 ps
CPU time 0.89 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 196604 kb
Host smart-dc73a2a8-7766-40b8-a467-164b1d959cf1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859369472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.859369472
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1046443669
Short name T570
Test name
Test status
Simulation time 152740549 ps
CPU time 1.19 seconds
Started Aug 02 04:48:17 PM PDT 24
Finished Aug 02 04:48:19 PM PDT 24
Peak memory 196620 kb
Host smart-9dfb2270-1d15-4730-924b-7d930b10c498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046443669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1046443669
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3060355505
Short name T34
Test name
Test status
Simulation time 76621395 ps
CPU time 0.95 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 197224 kb
Host smart-da015c17-558a-4da0-aee4-9f05f9bb6351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060355505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3060355505
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.542881000
Short name T682
Test name
Test status
Simulation time 34610566 ps
CPU time 0.91 seconds
Started Aug 02 04:48:25 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 196264 kb
Host smart-0a427714-8393-407a-824d-54f3c584dba5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542881000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.542881000
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.979636203
Short name T596
Test name
Test status
Simulation time 342502520 ps
CPU time 3.49 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 198360 kb
Host smart-795c3a40-dbe1-407b-b27b-f51ddd028266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979636203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.979636203
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2994903663
Short name T194
Test name
Test status
Simulation time 252379366 ps
CPU time 1.3 seconds
Started Aug 02 04:48:21 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 196696 kb
Host smart-744ec810-26df-4ee2-b49d-aba5e13ccd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994903663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2994903663
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3723248014
Short name T328
Test name
Test status
Simulation time 346014610 ps
CPU time 1.44 seconds
Started Aug 02 04:48:12 PM PDT 24
Finished Aug 02 04:48:13 PM PDT 24
Peak memory 196600 kb
Host smart-0e7c13c3-dfaf-43fc-8cfc-68304d70caa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723248014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3723248014
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.466209075
Short name T302
Test name
Test status
Simulation time 11208405371 ps
CPU time 154.94 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:51:08 PM PDT 24
Peak memory 198636 kb
Host smart-3fb702af-a1de-4bc9-96b2-5ecff146d29f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466209075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.466209075
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.98793901
Short name T489
Test name
Test status
Simulation time 23412244 ps
CPU time 0.58 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 194400 kb
Host smart-8a9e1f6c-0df0-4741-9f74-23ac4c213307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98793901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.98793901
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1853277783
Short name T452
Test name
Test status
Simulation time 39290210 ps
CPU time 0.81 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 195872 kb
Host smart-df3359ab-c4c3-47b7-b357-86c61982c6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853277783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1853277783
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3298794585
Short name T399
Test name
Test status
Simulation time 552533556 ps
CPU time 19.75 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:48 PM PDT 24
Peak memory 198572 kb
Host smart-b67d28d7-a882-4731-b1b1-156ef505b8f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298794585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3298794585
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.641095646
Short name T239
Test name
Test status
Simulation time 49993476 ps
CPU time 0.78 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 196208 kb
Host smart-dac45789-297b-441e-a3c6-58b92947b2cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641095646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.641095646
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2833746657
Short name T95
Test name
Test status
Simulation time 104580230 ps
CPU time 1.06 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 196468 kb
Host smart-8ede7a23-fbe8-4d64-893d-d778d2ae5aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833746657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2833746657
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.66339252
Short name T38
Test name
Test status
Simulation time 59367903 ps
CPU time 2.33 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 198532 kb
Host smart-b9a7b4ae-ca5c-44df-84d0-3053f467c530
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66339252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_intr_with_filter_rand_intr_event.66339252
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.751058800
Short name T156
Test name
Test status
Simulation time 767298665 ps
CPU time 3.35 seconds
Started Aug 02 04:48:34 PM PDT 24
Finished Aug 02 04:48:38 PM PDT 24
Peak memory 198524 kb
Host smart-6b152103-1a10-4adc-aee1-fe879b610a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751058800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
751058800
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1362451364
Short name T392
Test name
Test status
Simulation time 39524824 ps
CPU time 0.87 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 196964 kb
Host smart-59f9d6d5-4ea6-4560-ab87-02da7f05b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362451364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1362451364
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.259853629
Short name T417
Test name
Test status
Simulation time 98727713 ps
CPU time 1 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 197104 kb
Host smart-292ec649-44be-49c7-83a1-d2f35688a86d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259853629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.259853629
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3281078871
Short name T644
Test name
Test status
Simulation time 277261595 ps
CPU time 1.88 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 198384 kb
Host smart-d2b0e1a6-492b-414b-a7d9-0b323466f0e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281078871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3281078871
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2170669930
Short name T261
Test name
Test status
Simulation time 253889613 ps
CPU time 1.27 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196736 kb
Host smart-6af4ece9-28d9-4e79-8e81-eac55444a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170669930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2170669930
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1689031354
Short name T321
Test name
Test status
Simulation time 74296193 ps
CPU time 1.29 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 197148 kb
Host smart-6619ec25-5f57-4d90-8cf1-db6ae4a508e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689031354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1689031354
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1760270549
Short name T325
Test name
Test status
Simulation time 30367097415 ps
CPU time 139.09 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:50:43 PM PDT 24
Peak memory 198764 kb
Host smart-bed90b6a-11e7-43dc-bd6d-e5c39864c60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760270549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1760270549
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3954537235
Short name T448
Test name
Test status
Simulation time 15570516 ps
CPU time 0.57 seconds
Started Aug 02 04:48:39 PM PDT 24
Finished Aug 02 04:48:40 PM PDT 24
Peak memory 194628 kb
Host smart-0a5ded1f-9013-46a2-a3d1-4ffd7632964f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954537235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3954537235
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2669778622
Short name T412
Test name
Test status
Simulation time 17264248 ps
CPU time 0.66 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 194640 kb
Host smart-6cb4e811-8603-4abd-ae51-11c96605e37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669778622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2669778622
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2147680493
Short name T536
Test name
Test status
Simulation time 612423192 ps
CPU time 18.49 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:41 PM PDT 24
Peak memory 197236 kb
Host smart-63ee7f4e-2304-4936-9b4c-fd494b2cc9be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147680493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2147680493
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3343369207
Short name T656
Test name
Test status
Simulation time 765543544 ps
CPU time 0.94 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198176 kb
Host smart-f733c3b1-3339-4323-ab09-c02183a8b42b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343369207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3343369207
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2709290037
Short name T133
Test name
Test status
Simulation time 33747873 ps
CPU time 1.09 seconds
Started Aug 02 04:48:35 PM PDT 24
Finished Aug 02 04:48:37 PM PDT 24
Peak memory 196316 kb
Host smart-21d01cc2-b7d1-4353-98bc-835141d5e10c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709290037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2709290037
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1850122037
Short name T43
Test name
Test status
Simulation time 51157673 ps
CPU time 1.57 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196924 kb
Host smart-8fa1a64b-396d-49bb-8491-09d7f51f6a94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850122037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1850122037
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2070024408
Short name T411
Test name
Test status
Simulation time 276288362 ps
CPU time 2.69 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 198488 kb
Host smart-da25c220-790d-4ffa-a1f9-d0e7042594e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070024408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2070024408
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1671702057
Short name T13
Test name
Test status
Simulation time 29646819 ps
CPU time 1.05 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 197228 kb
Host smart-a4f9a8b2-eb98-412a-9037-8224f4802ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671702057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1671702057
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3411947305
Short name T443
Test name
Test status
Simulation time 68688983 ps
CPU time 1.42 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 197176 kb
Host smart-c8d9496a-6ea5-4536-8e4c-89111efc31c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411947305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3411947305
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1580866502
Short name T407
Test name
Test status
Simulation time 252870188 ps
CPU time 3.72 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:48:35 PM PDT 24
Peak memory 198468 kb
Host smart-233b0958-7156-4d75-b42e-9c1957d5aa73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580866502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1580866502
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2738896022
Short name T634
Test name
Test status
Simulation time 98998714 ps
CPU time 0.77 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 196288 kb
Host smart-7bfc1a54-6970-4d16-be8b-1a44ff26f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738896022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2738896022
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.43464461
Short name T659
Test name
Test status
Simulation time 562325481 ps
CPU time 1.19 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 196996 kb
Host smart-c9e22ab0-9b79-49a8-8711-dba95c259982
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43464461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.43464461
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2313036358
Short name T555
Test name
Test status
Simulation time 27461493876 ps
CPU time 189.68 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:51:40 PM PDT 24
Peak memory 198732 kb
Host smart-53d4597f-90fd-4be9-8a5c-dbc3a044e440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313036358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2313036358
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2570632414
Short name T269
Test name
Test status
Simulation time 10284927 ps
CPU time 0.56 seconds
Started Aug 02 04:48:25 PM PDT 24
Finished Aug 02 04:48:26 PM PDT 24
Peak memory 194468 kb
Host smart-fa183978-8b85-4871-a8f9-20238218d8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570632414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2570632414
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1979546359
Short name T432
Test name
Test status
Simulation time 159877024 ps
CPU time 0.9 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 197896 kb
Host smart-0ba78447-6452-4664-a499-0445e3429d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979546359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1979546359
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.74724829
Short name T189
Test name
Test status
Simulation time 2096520201 ps
CPU time 23 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 196996 kb
Host smart-1dea823d-82b0-423a-b90d-c8c81ba33672
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74724829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress
.74724829
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3122594409
Short name T83
Test name
Test status
Simulation time 37361711 ps
CPU time 0.68 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 195736 kb
Host smart-3b4a1660-2c48-48c6-a971-6640de480a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122594409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3122594409
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.31299351
Short name T505
Test name
Test status
Simulation time 248990262 ps
CPU time 0.88 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196312 kb
Host smart-0d8d16b3-3497-43e1-abb0-df9527b8a090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.31299351
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.859111185
Short name T167
Test name
Test status
Simulation time 485006033 ps
CPU time 2.64 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198540 kb
Host smart-4ca1c314-e5b3-4fe2-823f-fbe3f30f789e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859111185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.859111185
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.368188232
Short name T526
Test name
Test status
Simulation time 351652582 ps
CPU time 3.07 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 197820 kb
Host smart-5e973f0e-cd05-407e-a050-6fa58e5cf3f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368188232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
368188232
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3382397215
Short name T683
Test name
Test status
Simulation time 91122864 ps
CPU time 1.1 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 196612 kb
Host smart-1cc5cf6b-ca3a-43ba-9ec2-41325b0851be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382397215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3382397215
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2291420217
Short name T620
Test name
Test status
Simulation time 75818465 ps
CPU time 0.76 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 195856 kb
Host smart-d370dd19-585f-453f-a2d6-dd454b3f7805
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291420217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2291420217
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2884449472
Short name T613
Test name
Test status
Simulation time 30773928 ps
CPU time 1.3 seconds
Started Aug 02 04:48:25 PM PDT 24
Finished Aug 02 04:48:26 PM PDT 24
Peak memory 198496 kb
Host smart-ca48f97e-b149-4bde-bafa-1e0cf9c96bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884449472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2884449472
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.150808175
Short name T306
Test name
Test status
Simulation time 155184961 ps
CPU time 0.93 seconds
Started Aug 02 04:48:23 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 196732 kb
Host smart-7d716992-cc77-4731-8b74-4fd1b4ffe52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150808175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.150808175
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2102801393
Short name T507
Test name
Test status
Simulation time 176434851 ps
CPU time 1.11 seconds
Started Aug 02 04:48:22 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 196456 kb
Host smart-7160c579-c77e-45a4-8c5a-d1ba0d9c8528
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102801393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2102801393
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.154761549
Short name T568
Test name
Test status
Simulation time 20156982133 ps
CPU time 115.05 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:50:21 PM PDT 24
Peak memory 198724 kb
Host smart-15689a46-99f2-419e-9094-6909390e5142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154761549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.154761549
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.437770771
Short name T462
Test name
Test status
Simulation time 121175012829 ps
CPU time 674.13 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:59:41 PM PDT 24
Peak memory 198892 kb
Host smart-4f16c393-eaa8-4282-abb3-391c1c9e33d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=437770771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.437770771
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4198091841
Short name T518
Test name
Test status
Simulation time 61346305 ps
CPU time 0.56 seconds
Started Aug 02 04:48:25 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 194436 kb
Host smart-eadc7e5b-fc6f-45e0-894d-8e7dc9a5dc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198091841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4198091841
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3787377571
Short name T474
Test name
Test status
Simulation time 42642273 ps
CPU time 0.62 seconds
Started Aug 02 04:48:25 PM PDT 24
Finished Aug 02 04:48:26 PM PDT 24
Peak memory 194476 kb
Host smart-f2ed4e22-fb19-4327-bf37-8ce2e6feb57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787377571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3787377571
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.311360155
Short name T257
Test name
Test status
Simulation time 291841201 ps
CPU time 4.17 seconds
Started Aug 02 04:48:35 PM PDT 24
Finished Aug 02 04:48:40 PM PDT 24
Peak memory 197212 kb
Host smart-9d3c1e41-ae69-42db-a178-50e5180fcee0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311360155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.311360155
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1334684004
Short name T442
Test name
Test status
Simulation time 155519081 ps
CPU time 1.17 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:26 PM PDT 24
Peak memory 196668 kb
Host smart-658bbb83-3a66-4925-ae88-a8090d85f173
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334684004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1334684004
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2187806750
Short name T607
Test name
Test status
Simulation time 94835003 ps
CPU time 1.24 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:27 PM PDT 24
Peak memory 198612 kb
Host smart-e7a8c927-b0b6-44ff-bf17-c9959b150816
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187806750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2187806750
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.609266684
Short name T14
Test name
Test status
Simulation time 250181234 ps
CPU time 1.51 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196692 kb
Host smart-6861f8de-8a52-432a-90d2-9df71bf89099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609266684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
609266684
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1453999843
Short name T406
Test name
Test status
Simulation time 61796642 ps
CPU time 0.86 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:25 PM PDT 24
Peak memory 197800 kb
Host smart-80e27b56-6bbd-4b18-b8e3-6f9b4b0295c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453999843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1453999843
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.301437757
Short name T447
Test name
Test status
Simulation time 971163053 ps
CPU time 1.31 seconds
Started Aug 02 04:48:24 PM PDT 24
Finished Aug 02 04:48:26 PM PDT 24
Peak memory 198580 kb
Host smart-65d21f68-31b6-4d2a-b67c-9e0c218af792
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301437757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.301437757
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.773182708
Short name T234
Test name
Test status
Simulation time 151193719 ps
CPU time 2.53 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198580 kb
Host smart-7377dbe2-c693-4502-9a2a-8fbb85222a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773182708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.773182708
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2954666596
Short name T164
Test name
Test status
Simulation time 103375694 ps
CPU time 1.26 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 197444 kb
Host smart-95627bef-ea02-4124-a12c-008d8206940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954666596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2954666596
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3785232768
Short name T85
Test name
Test status
Simulation time 797467824 ps
CPU time 1.22 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 197244 kb
Host smart-49e58e00-58b1-4006-a5c5-05b98b2e92a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785232768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3785232768
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1523202850
Short name T379
Test name
Test status
Simulation time 9200902135 ps
CPU time 49.46 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:49:16 PM PDT 24
Peak memory 198652 kb
Host smart-0b463843-4108-4af2-ba9a-2010d80b9ea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523202850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1523202850
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3575690903
Short name T350
Test name
Test status
Simulation time 40076971 ps
CPU time 0.58 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:29 PM PDT 24
Peak memory 194304 kb
Host smart-832990e5-595d-4b5d-ae09-9a72eaf20983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575690903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3575690903
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2984262361
Short name T355
Test name
Test status
Simulation time 36705805 ps
CPU time 0.89 seconds
Started Aug 02 04:48:27 PM PDT 24
Finished Aug 02 04:48:28 PM PDT 24
Peak memory 197044 kb
Host smart-e36392df-a514-48a9-9e89-8aaec522715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984262361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2984262361
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.76773968
Short name T429
Test name
Test status
Simulation time 308175503 ps
CPU time 16.24 seconds
Started Aug 02 04:48:38 PM PDT 24
Finished Aug 02 04:48:54 PM PDT 24
Peak memory 196020 kb
Host smart-c461a64c-fb01-4a72-b287-6d402b89d965
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76773968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.76773968
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1795390092
Short name T20
Test name
Test status
Simulation time 43540527 ps
CPU time 0.73 seconds
Started Aug 02 04:48:46 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 196204 kb
Host smart-d98d84ad-6199-4754-9def-08bfee62002a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795390092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1795390092
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.238899243
Short name T382
Test name
Test status
Simulation time 159761095 ps
CPU time 1.12 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 197104 kb
Host smart-252a5e6c-e198-44c3-b80f-d4afbd580ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238899243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.238899243
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1414776195
Short name T502
Test name
Test status
Simulation time 305922366 ps
CPU time 3.08 seconds
Started Aug 02 04:48:26 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 198528 kb
Host smart-98923c22-f990-4386-908a-982fc71e2b5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414776195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1414776195
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1439359556
Short name T318
Test name
Test status
Simulation time 489835411 ps
CPU time 3.08 seconds
Started Aug 02 04:48:28 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 198528 kb
Host smart-8bbbe947-cd80-4d66-b890-98e3390a8061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439359556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1439359556
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.971899900
Short name T545
Test name
Test status
Simulation time 126252848 ps
CPU time 1.25 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 196420 kb
Host smart-0d1329cf-07f0-4906-9384-eb355dcffbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971899900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.971899900
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1199466906
Short name T21
Test name
Test status
Simulation time 40869070 ps
CPU time 0.67 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 194856 kb
Host smart-f432cb0a-99e9-4377-a245-02974d68a544
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199466906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1199466906
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1913564389
Short name T148
Test name
Test status
Simulation time 643768104 ps
CPU time 5.16 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 198496 kb
Host smart-938081ed-8653-45c6-9a28-487cd64f7371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913564389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1913564389
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1482769635
Short name T556
Test name
Test status
Simulation time 119913335 ps
CPU time 1.09 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 196096 kb
Host smart-48b38b34-e8ae-4b06-9d02-75be2ce2d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482769635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1482769635
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3442563698
Short name T177
Test name
Test status
Simulation time 187582229 ps
CPU time 0.93 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 196864 kb
Host smart-29f94782-0dc9-4f03-9a5c-08c2d54912c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442563698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3442563698
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.912054842
Short name T200
Test name
Test status
Simulation time 211710215598 ps
CPU time 175.25 seconds
Started Aug 02 04:48:36 PM PDT 24
Finished Aug 02 04:51:31 PM PDT 24
Peak memory 198504 kb
Host smart-1a1a7fc6-e4c9-4237-a977-6db4099a5b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912054842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.912054842
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2468090499
Short name T691
Test name
Test status
Simulation time 42443803 ps
CPU time 0.56 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:55 PM PDT 24
Peak memory 194316 kb
Host smart-90d0f15f-af74-49a9-8bac-a5fed77f1cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468090499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2468090499
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2704841769
Short name T687
Test name
Test status
Simulation time 94795916 ps
CPU time 0.75 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 195616 kb
Host smart-721940df-1284-4814-bdf0-4fe13c7ed7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704841769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2704841769
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.554902669
Short name T593
Test name
Test status
Simulation time 866157556 ps
CPU time 27.95 seconds
Started Aug 02 04:48:35 PM PDT 24
Finished Aug 02 04:49:03 PM PDT 24
Peak memory 197160 kb
Host smart-f2c197f5-ddef-45c7-b780-41fa541741cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554902669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.554902669
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2364870044
Short name T650
Test name
Test status
Simulation time 63243791 ps
CPU time 1.07 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 196788 kb
Host smart-26d54430-bdd9-40c5-8106-67442eeffd6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364870044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2364870044
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2147053780
Short name T273
Test name
Test status
Simulation time 73415565 ps
CPU time 0.79 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:31 PM PDT 24
Peak memory 195968 kb
Host smart-39bebd74-b4f0-4024-a271-27b5a32c52b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147053780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2147053780
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3439270731
Short name T394
Test name
Test status
Simulation time 23344568 ps
CPU time 0.98 seconds
Started Aug 02 04:48:29 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 196888 kb
Host smart-63940bc0-120b-460c-acbd-eac7ef12b815
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439270731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3439270731
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3483622011
Short name T436
Test name
Test status
Simulation time 128030578 ps
CPU time 1.16 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 196760 kb
Host smart-2762c626-cc15-49e5-a25d-dd080c704b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483622011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3483622011
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2806754779
Short name T380
Test name
Test status
Simulation time 114261215 ps
CPU time 0.81 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 196544 kb
Host smart-dabebd74-2c5d-4df0-9f85-e8bafae32c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806754779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2806754779
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4090300768
Short name T449
Test name
Test status
Simulation time 33016628 ps
CPU time 0.91 seconds
Started Aug 02 04:48:37 PM PDT 24
Finished Aug 02 04:48:38 PM PDT 24
Peak memory 196892 kb
Host smart-1908c82d-65f2-405d-aa2c-a315af0e6ed5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090300768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4090300768
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.270422666
Short name T283
Test name
Test status
Simulation time 211585514 ps
CPU time 2.5 seconds
Started Aug 02 04:48:30 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198524 kb
Host smart-9fd11b68-2ca1-4d43-8aeb-cbb02dd0b31f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270422666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.270422666
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3412109133
Short name T250
Test name
Test status
Simulation time 485306542 ps
CPU time 0.83 seconds
Started Aug 02 04:48:31 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 195944 kb
Host smart-76adea76-a5bc-446b-b373-a356df04bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412109133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3412109133
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.351079202
Short name T337
Test name
Test status
Simulation time 205553124 ps
CPU time 1.55 seconds
Started Aug 02 04:48:35 PM PDT 24
Finished Aug 02 04:48:36 PM PDT 24
Peak memory 197432 kb
Host smart-3f114435-7cdf-4e9e-b472-fdb779d22387
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351079202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.351079202
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2823402797
Short name T668
Test name
Test status
Simulation time 19758706742 ps
CPU time 128.13 seconds
Started Aug 02 04:48:44 PM PDT 24
Finished Aug 02 04:50:52 PM PDT 24
Peak memory 198640 kb
Host smart-3f53d771-a1f1-49d4-aa93-877ea7dc4a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823402797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2823402797
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3880759094
Short name T642
Test name
Test status
Simulation time 180288881243 ps
CPU time 564.76 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:57:57 PM PDT 24
Peak memory 198792 kb
Host smart-24a653eb-7f94-4fba-80d7-8f30633b6540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3880759094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3880759094
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.832746482
Short name T326
Test name
Test status
Simulation time 40227208 ps
CPU time 0.56 seconds
Started Aug 02 04:48:40 PM PDT 24
Finished Aug 02 04:48:41 PM PDT 24
Peak memory 194360 kb
Host smart-f4abcc05-0d70-4241-9073-3e51e5786688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832746482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.832746482
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.615733001
Short name T247
Test name
Test status
Simulation time 72651864 ps
CPU time 0.65 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 194548 kb
Host smart-c5993294-96e8-4791-9e97-f27bd96c802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615733001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.615733001
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1004400829
Short name T578
Test name
Test status
Simulation time 919433739 ps
CPU time 27.35 seconds
Started Aug 02 04:48:31 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 197236 kb
Host smart-7885e5d7-b564-4d2a-bc85-2f496ffdbc1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004400829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1004400829
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3764315468
Short name T551
Test name
Test status
Simulation time 176887309 ps
CPU time 0.87 seconds
Started Aug 02 04:48:50 PM PDT 24
Finished Aug 02 04:48:51 PM PDT 24
Peak memory 196492 kb
Host smart-c5c69b82-3089-43e1-86d6-0a33591d20d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764315468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3764315468
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1409287804
Short name T348
Test name
Test status
Simulation time 28352290 ps
CPU time 0.91 seconds
Started Aug 02 04:48:48 PM PDT 24
Finished Aug 02 04:48:49 PM PDT 24
Peak memory 197956 kb
Host smart-95e516e5-744c-4acc-83ad-846d8897084a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409287804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1409287804
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1837140742
Short name T193
Test name
Test status
Simulation time 866011812 ps
CPU time 3.11 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:36 PM PDT 24
Peak memory 198476 kb
Host smart-1fdfdf00-b913-412b-bedf-88f4af0bf858
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837140742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1837140742
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1493080257
Short name T336
Test name
Test status
Simulation time 308311554 ps
CPU time 1.87 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 196372 kb
Host smart-59f8efb5-aca7-493e-8ca7-671cc8f2664f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493080257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1493080257
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2021056348
Short name T41
Test name
Test status
Simulation time 454297577 ps
CPU time 1.3 seconds
Started Aug 02 04:48:37 PM PDT 24
Finished Aug 02 04:48:39 PM PDT 24
Peak memory 197468 kb
Host smart-7d59ccc7-6330-4e68-8d73-90c710af461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021056348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2021056348
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3672461941
Short name T421
Test name
Test status
Simulation time 23142357 ps
CPU time 0.73 seconds
Started Aug 02 04:48:48 PM PDT 24
Finished Aug 02 04:48:48 PM PDT 24
Peak memory 196656 kb
Host smart-37ecdfe8-74ad-48ea-911c-81eefa500998
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672461941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3672461941
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_smoke.3721348419
Short name T277
Test name
Test status
Simulation time 75225638 ps
CPU time 1.19 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:56 PM PDT 24
Peak memory 197396 kb
Host smart-e0360c48-0d24-4d6f-895f-53b9d009b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721348419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3721348419
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1591621665
Short name T163
Test name
Test status
Simulation time 178704621 ps
CPU time 1.03 seconds
Started Aug 02 04:48:47 PM PDT 24
Finished Aug 02 04:48:48 PM PDT 24
Peak memory 196048 kb
Host smart-043c50a1-d5f6-4245-97d8-bef062a57ad1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591621665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1591621665
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2457698658
Short name T514
Test name
Test status
Simulation time 85052407528 ps
CPU time 125.51 seconds
Started Aug 02 04:48:44 PM PDT 24
Finished Aug 02 04:50:50 PM PDT 24
Peak memory 198632 kb
Host smart-380220b3-2a8a-454e-b9ea-ab2ffdc0653e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457698658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2457698658
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.630546756
Short name T451
Test name
Test status
Simulation time 36687311 ps
CPU time 0.56 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 194372 kb
Host smart-0c3b53bd-14b9-4f7d-90f0-d248591885a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630546756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.630546756
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4176851452
Short name T187
Test name
Test status
Simulation time 47407440 ps
CPU time 0.71 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:19 PM PDT 24
Peak memory 195596 kb
Host smart-e717911e-4372-4472-a3cd-f84d9ba69450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176851452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4176851452
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.33151305
Short name T316
Test name
Test status
Simulation time 898413503 ps
CPU time 27.05 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:45 PM PDT 24
Peak memory 198408 kb
Host smart-4069e64c-bd4d-4890-92ee-4d322bc96e5d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress.33151305
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1609562277
Short name T111
Test name
Test status
Simulation time 52914806 ps
CPU time 0.86 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 197376 kb
Host smart-95ed4c45-c40a-406d-a571-69745eee10fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609562277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1609562277
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4264850573
Short name T298
Test name
Test status
Simulation time 76458527 ps
CPU time 1.25 seconds
Started Aug 02 04:47:23 PM PDT 24
Finished Aug 02 04:47:25 PM PDT 24
Peak memory 197052 kb
Host smart-efb7be73-ec80-4397-b390-243048a3088c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264850573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4264850573
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1264070406
Short name T441
Test name
Test status
Simulation time 171560040 ps
CPU time 3.37 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:23 PM PDT 24
Peak memory 198680 kb
Host smart-3e6f3a58-844d-441a-8923-da97ce3050ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264070406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1264070406
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1336878619
Short name T678
Test name
Test status
Simulation time 101111026 ps
CPU time 1.94 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 196728 kb
Host smart-ab0a66b9-c44c-4496-8fde-70652140525a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336878619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1336878619
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3715583637
Short name T697
Test name
Test status
Simulation time 302513406 ps
CPU time 1.2 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 196272 kb
Host smart-c60c1bbd-eb26-446d-91c4-0c62fdf9b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715583637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3715583637
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.167429473
Short name T365
Test name
Test status
Simulation time 90454740 ps
CPU time 1.3 seconds
Started Aug 02 04:47:24 PM PDT 24
Finished Aug 02 04:47:25 PM PDT 24
Peak memory 198552 kb
Host smart-c8e5f718-7f34-4e04-9897-ab4001b881f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167429473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.167429473
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4202759378
Short name T69
Test name
Test status
Simulation time 279599850 ps
CPU time 3.26 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 198432 kb
Host smart-0f8fb9cc-6278-4d89-bcd7-75604d79310f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202759378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4202759378
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.333631024
Short name T64
Test name
Test status
Simulation time 38530867 ps
CPU time 0.8 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 214480 kb
Host smart-2646a009-8560-4ddc-8d9d-5fbb06071673
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333631024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.333631024
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2403275832
Short name T615
Test name
Test status
Simulation time 88210506 ps
CPU time 1.34 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 198528 kb
Host smart-dd5b7b76-603c-4956-9b1e-aec0a0e1c72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403275832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2403275832
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3669620401
Short name T500
Test name
Test status
Simulation time 323403435 ps
CPU time 1.38 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 198472 kb
Host smart-f22afbd3-5dcc-452c-acab-56568cadf368
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669620401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3669620401
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.39921866
Short name T707
Test name
Test status
Simulation time 2389971330 ps
CPU time 65.08 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 198816 kb
Host smart-0860d372-92a5-40bd-b90a-8e56d5b4c278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39921866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpi
o_stress_all.39921866
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3363466909
Short name T76
Test name
Test status
Simulation time 138977910217 ps
CPU time 1195.08 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 05:07:23 PM PDT 24
Peak memory 198796 kb
Host smart-8e556acc-52bd-4cf1-944f-5a88825bbe20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3363466909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3363466909
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3886397774
Short name T390
Test name
Test status
Simulation time 13202781 ps
CPU time 0.55 seconds
Started Aug 02 04:48:44 PM PDT 24
Finished Aug 02 04:48:45 PM PDT 24
Peak memory 195124 kb
Host smart-e444865f-d799-4b0d-9936-77fabd91ea3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886397774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3886397774
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1653469846
Short name T579
Test name
Test status
Simulation time 58189862 ps
CPU time 0.67 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:48:32 PM PDT 24
Peak memory 194540 kb
Host smart-e87f724c-e143-48b8-9378-e3bf4fcbfe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653469846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1653469846
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3362943385
Short name T31
Test name
Test status
Simulation time 561565354 ps
CPU time 19.12 seconds
Started Aug 02 04:48:40 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 197356 kb
Host smart-374cea88-5b9b-4b63-8040-6cab4018be48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362943385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3362943385
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1926046095
Short name T186
Test name
Test status
Simulation time 1018597052 ps
CPU time 1.02 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:48:53 PM PDT 24
Peak memory 198248 kb
Host smart-d9c133a8-e2c7-4e4e-9d5d-a34e83ceed1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926046095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1926046095
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1262842676
Short name T680
Test name
Test status
Simulation time 395580831 ps
CPU time 1.32 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 197524 kb
Host smart-01d1c789-7a2d-4d1f-b27e-854650953309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262842676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1262842676
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1814516542
Short name T192
Test name
Test status
Simulation time 197377708 ps
CPU time 1.89 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 198528 kb
Host smart-d75d507f-a81f-4ede-9af2-81b0a12429b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814516542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1814516542
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.880179413
Short name T267
Test name
Test status
Simulation time 165708445 ps
CPU time 1.92 seconds
Started Aug 02 04:48:49 PM PDT 24
Finished Aug 02 04:48:51 PM PDT 24
Peak memory 196276 kb
Host smart-bbd3aac8-7527-4bae-ae2c-7b1d8bb49952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880179413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
880179413
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2738945527
Short name T327
Test name
Test status
Simulation time 44843498 ps
CPU time 0.98 seconds
Started Aug 02 04:48:43 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 196396 kb
Host smart-ca0b79f3-4ebc-44fc-a8a7-7b88ac393d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738945527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2738945527
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4096993132
Short name T340
Test name
Test status
Simulation time 117877712 ps
CPU time 0.76 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 195880 kb
Host smart-f6256ef4-060d-47b6-9461-e1fb2d5a6d14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096993132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4096993132
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4248955404
Short name T254
Test name
Test status
Simulation time 1566000951 ps
CPU time 4.88 seconds
Started Aug 02 04:48:53 PM PDT 24
Finished Aug 02 04:48:58 PM PDT 24
Peak memory 198444 kb
Host smart-93605407-59ce-4998-ac86-9904e7ca286a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248955404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4248955404
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.113996733
Short name T334
Test name
Test status
Simulation time 116452159 ps
CPU time 1.04 seconds
Started Aug 02 04:48:34 PM PDT 24
Finished Aug 02 04:48:35 PM PDT 24
Peak memory 196172 kb
Host smart-0ccb3b4c-4113-4a67-b21e-0d2b70ecab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113996733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.113996733
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2404301824
Short name T90
Test name
Test status
Simulation time 101751134 ps
CPU time 1.07 seconds
Started Aug 02 04:48:34 PM PDT 24
Finished Aug 02 04:48:35 PM PDT 24
Peak memory 196944 kb
Host smart-39d3ebe5-3e92-4bb1-9011-452c4c9d17da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404301824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2404301824
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1320513969
Short name T415
Test name
Test status
Simulation time 6753267035 ps
CPU time 95.58 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:50:18 PM PDT 24
Peak memory 198596 kb
Host smart-6256ad19-3859-4351-a96e-5aefb4663f00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320513969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1320513969
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.298336925
Short name T46
Test name
Test status
Simulation time 141464409647 ps
CPU time 2668.66 seconds
Started Aug 02 04:48:50 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 198836 kb
Host smart-e1ee3996-a9eb-450f-9b95-fd1f5b297d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=298336925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.298336925
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.142644443
Short name T149
Test name
Test status
Simulation time 15919819 ps
CPU time 0.56 seconds
Started Aug 02 04:48:44 PM PDT 24
Finished Aug 02 04:48:45 PM PDT 24
Peak memory 194372 kb
Host smart-f3cee121-b8f8-46f6-9199-0461e283abf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142644443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.142644443
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.17131103
Short name T621
Test name
Test status
Simulation time 70615989 ps
CPU time 0.71 seconds
Started Aug 02 04:48:47 PM PDT 24
Finished Aug 02 04:48:48 PM PDT 24
Peak memory 195460 kb
Host smart-e9b79267-7cfc-40dd-8cc9-24fe04433092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17131103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.17131103
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3399243331
Short name T159
Test name
Test status
Simulation time 2706878580 ps
CPU time 24.69 seconds
Started Aug 02 04:48:32 PM PDT 24
Finished Aug 02 04:48:57 PM PDT 24
Peak memory 197144 kb
Host smart-87b22910-f42c-4268-abbd-7139e4dac327
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399243331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3399243331
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.814791204
Short name T410
Test name
Test status
Simulation time 137015063 ps
CPU time 0.85 seconds
Started Aug 02 04:48:45 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 197020 kb
Host smart-e27b7511-9aa2-4430-b19f-c0cc452afda3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814791204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.814791204
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2938935802
Short name T287
Test name
Test status
Simulation time 37941520 ps
CPU time 0.91 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 197844 kb
Host smart-eef18c8a-1b6c-4fa8-9d96-97466a54d18d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938935802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2938935802
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.332134913
Short name T196
Test name
Test status
Simulation time 53615905 ps
CPU time 2.15 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 196972 kb
Host smart-c0bc55e7-b6a4-459f-a3ab-c55e7a90e72f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332134913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.332134913
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1582568315
Short name T626
Test name
Test status
Simulation time 578651698 ps
CPU time 3.47 seconds
Started Aug 02 04:48:50 PM PDT 24
Finished Aug 02 04:48:53 PM PDT 24
Peak memory 198480 kb
Host smart-f4a1a388-a491-4c69-980d-4a91d10b884e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582568315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1582568315
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3365682331
Short name T35
Test name
Test status
Simulation time 15007759 ps
CPU time 0.68 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 194756 kb
Host smart-684a5492-8d55-48e4-8418-1385f3919dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365682331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3365682331
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2475748702
Short name T221
Test name
Test status
Simulation time 120845377 ps
CPU time 1.29 seconds
Started Aug 02 04:48:37 PM PDT 24
Finished Aug 02 04:48:39 PM PDT 24
Peak memory 198488 kb
Host smart-95d3c446-fe1e-4117-9a7e-600bc06ed11d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475748702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2475748702
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1792925214
Short name T530
Test name
Test status
Simulation time 32331448 ps
CPU time 1.43 seconds
Started Aug 02 04:48:51 PM PDT 24
Finished Aug 02 04:48:53 PM PDT 24
Peak memory 198488 kb
Host smart-65dc730d-e61e-4695-872a-fb39ac48e858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792925214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1792925214
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1637576711
Short name T630
Test name
Test status
Simulation time 70008696 ps
CPU time 1.13 seconds
Started Aug 02 04:48:43 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 196100 kb
Host smart-49dbaf9a-0b92-4991-b6e8-020c29c47894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637576711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1637576711
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4171165818
Short name T161
Test name
Test status
Simulation time 33375273 ps
CPU time 0.97 seconds
Started Aug 02 04:48:33 PM PDT 24
Finished Aug 02 04:48:34 PM PDT 24
Peak memory 196812 kb
Host smart-69fc2efb-d2f3-47cc-9fe8-8c39317d0b92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171165818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4171165818
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1422940512
Short name T301
Test name
Test status
Simulation time 1504774633 ps
CPU time 35.66 seconds
Started Aug 02 04:48:49 PM PDT 24
Finished Aug 02 04:49:24 PM PDT 24
Peak memory 198556 kb
Host smart-243f75a4-d8e9-49f3-b41c-ab4037b70dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422940512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1422940512
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3365276875
Short name T517
Test name
Test status
Simulation time 13351621 ps
CPU time 0.57 seconds
Started Aug 02 04:48:37 PM PDT 24
Finished Aug 02 04:48:37 PM PDT 24
Peak memory 194020 kb
Host smart-bfeb5e61-f7cd-4ac3-a798-3149ad9be2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365276875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3365276875
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2626365024
Short name T571
Test name
Test status
Simulation time 38069489 ps
CPU time 0.93 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 196532 kb
Host smart-1f7253e4-5671-4137-850a-84a2c1a3383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626365024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2626365024
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3054377379
Short name T524
Test name
Test status
Simulation time 587429739 ps
CPU time 20.23 seconds
Started Aug 02 04:48:45 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 196788 kb
Host smart-621089d7-5107-450a-84fb-563d3e384e2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054377379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3054377379
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2268559718
Short name T671
Test name
Test status
Simulation time 44137736 ps
CPU time 0.75 seconds
Started Aug 02 04:48:56 PM PDT 24
Finished Aug 02 04:48:57 PM PDT 24
Peak memory 196292 kb
Host smart-604b5f88-c62a-473d-8f9a-4148e436080d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268559718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2268559718
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.710760924
Short name T588
Test name
Test status
Simulation time 52778407 ps
CPU time 1.35 seconds
Started Aug 02 04:48:47 PM PDT 24
Finished Aug 02 04:48:49 PM PDT 24
Peak memory 198508 kb
Host smart-e6ebfb59-bbbb-4bc1-960d-b39b45a024cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710760924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.710760924
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3382624982
Short name T515
Test name
Test status
Simulation time 508229262 ps
CPU time 3.3 seconds
Started Aug 02 04:48:44 PM PDT 24
Finished Aug 02 04:48:47 PM PDT 24
Peak memory 198548 kb
Host smart-8d476efa-a430-40a3-b9a6-b037f265758c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382624982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3382624982
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1556559238
Short name T513
Test name
Test status
Simulation time 76744807 ps
CPU time 2.21 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:48:55 PM PDT 24
Peak memory 197480 kb
Host smart-86c2cd2e-d3f7-4394-8102-90cbab8076c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556559238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1556559238
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2793010602
Short name T539
Test name
Test status
Simulation time 38545574 ps
CPU time 0.7 seconds
Started Aug 02 04:48:45 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 194808 kb
Host smart-79dc7dfe-fe49-4fd4-8c12-a0050ef2db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793010602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2793010602
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.496848212
Short name T202
Test name
Test status
Simulation time 38651736 ps
CPU time 1.19 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 04:48:43 PM PDT 24
Peak memory 196224 kb
Host smart-18fdff27-2961-4e9e-ad6f-ad85aec9f226
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496848212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.496848212
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1008166504
Short name T4
Test name
Test status
Simulation time 423147202 ps
CPU time 5.03 seconds
Started Aug 02 04:48:43 PM PDT 24
Finished Aug 02 04:48:48 PM PDT 24
Peak memory 198392 kb
Host smart-092d999b-c11c-4d1d-a4bf-2e0a53701bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008166504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1008166504
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1601448611
Short name T125
Test name
Test status
Simulation time 66501277 ps
CPU time 0.91 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:56 PM PDT 24
Peak memory 196132 kb
Host smart-15f4cf8d-b648-480b-9b80-9c4db47f0bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601448611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1601448611
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.849268700
Short name T419
Test name
Test status
Simulation time 46011911 ps
CPU time 0.92 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 196168 kb
Host smart-b65f5184-2784-4765-86e6-28578bfbeba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849268700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.849268700
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3796075505
Short name T2
Test name
Test status
Simulation time 17456299571 ps
CPU time 218.12 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:52:20 PM PDT 24
Peak memory 198620 kb
Host smart-67d60ed0-8b7d-437e-85da-b1226bb48224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796075505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3796075505
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1927034699
Short name T422
Test name
Test status
Simulation time 1546491376067 ps
CPU time 2108.5 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 207124 kb
Host smart-2d4f1f78-a04c-4338-a4ca-f1402e7c1e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1927034699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1927034699
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3082262104
Short name T597
Test name
Test status
Simulation time 17470354 ps
CPU time 0.58 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:02 PM PDT 24
Peak memory 195136 kb
Host smart-0451443f-829b-47e1-be7b-043b501c234c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082262104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3082262104
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1314588781
Short name T241
Test name
Test status
Simulation time 79684618 ps
CPU time 0.91 seconds
Started Aug 02 04:48:49 PM PDT 24
Finished Aug 02 04:48:50 PM PDT 24
Peak memory 196356 kb
Host smart-3b012df5-ab82-41a0-9c53-fcc7c01a1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314588781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1314588781
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.891256573
Short name T42
Test name
Test status
Simulation time 2140875765 ps
CPU time 10.73 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:49:03 PM PDT 24
Peak memory 198584 kb
Host smart-eb222e33-90e5-4c7c-aae7-2bdda7a71b7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891256573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.891256573
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2958961485
Short name T297
Test name
Test status
Simulation time 85391568 ps
CPU time 1.1 seconds
Started Aug 02 04:48:48 PM PDT 24
Finished Aug 02 04:48:49 PM PDT 24
Peak memory 197092 kb
Host smart-61d9cd1d-2718-4bfe-8d57-69ca70a75bfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958961485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2958961485
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3757584428
Short name T527
Test name
Test status
Simulation time 90577851 ps
CPU time 1.35 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 198556 kb
Host smart-013709d3-6f9d-489c-83d7-8431f07a0ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757584428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3757584428
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2805967632
Short name T401
Test name
Test status
Simulation time 192052659 ps
CPU time 1.83 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 198576 kb
Host smart-cc6296d2-fc44-4327-95f7-84a060809115
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805967632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2805967632
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.813279492
Short name T672
Test name
Test status
Simulation time 167392336 ps
CPU time 2.43 seconds
Started Aug 02 04:49:03 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 198616 kb
Host smart-ec4679c1-4472-4cad-b2df-0a36c79d89e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813279492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
813279492
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4006870920
Short name T408
Test name
Test status
Simulation time 61605941 ps
CPU time 1.2 seconds
Started Aug 02 04:48:53 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 196600 kb
Host smart-f452b7bc-a36c-443d-ab28-54f955b72388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006870920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4006870920
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3515760988
Short name T171
Test name
Test status
Simulation time 77734925 ps
CPU time 0.73 seconds
Started Aug 02 04:48:46 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 195840 kb
Host smart-84c0464e-3947-40c7-94a2-c9a810bbf74f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515760988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3515760988
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.80640992
Short name T216
Test name
Test status
Simulation time 482074257 ps
CPU time 5.86 seconds
Started Aug 02 04:48:48 PM PDT 24
Finished Aug 02 04:48:54 PM PDT 24
Peak memory 198464 kb
Host smart-28aa7979-5b53-4dbf-9176-0b3940e54477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80640992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand
om_long_reg_writes_reg_reads.80640992
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2419991471
Short name T494
Test name
Test status
Simulation time 116587197 ps
CPU time 1.1 seconds
Started Aug 02 04:48:39 PM PDT 24
Finished Aug 02 04:48:40 PM PDT 24
Peak memory 196732 kb
Host smart-497000f4-907e-4530-b94c-4770456ffe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419991471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2419991471
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1463601642
Short name T487
Test name
Test status
Simulation time 281611904 ps
CPU time 1.17 seconds
Started Aug 02 04:48:50 PM PDT 24
Finished Aug 02 04:48:51 PM PDT 24
Peak memory 196276 kb
Host smart-6d4fc6be-275e-4e11-9ef3-f9452ca8240d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463601642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1463601642
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4115140799
Short name T344
Test name
Test status
Simulation time 21791227276 ps
CPU time 153.77 seconds
Started Aug 02 04:48:57 PM PDT 24
Finished Aug 02 04:51:31 PM PDT 24
Peak memory 198592 kb
Host smart-b1e4622e-2867-4345-8f66-318def08fd5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115140799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4115140799
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2431453645
Short name T209
Test name
Test status
Simulation time 14557905 ps
CPU time 0.57 seconds
Started Aug 02 04:48:41 PM PDT 24
Finished Aug 02 04:48:41 PM PDT 24
Peak memory 193844 kb
Host smart-1583f814-409c-448a-92f1-5913b8f8ebe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431453645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2431453645
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1898033509
Short name T581
Test name
Test status
Simulation time 24059424 ps
CPU time 0.69 seconds
Started Aug 02 04:48:49 PM PDT 24
Finished Aug 02 04:48:50 PM PDT 24
Peak memory 195364 kb
Host smart-b9a1494c-ff53-4f60-bb72-97ef978e139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898033509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1898033509
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2704542049
Short name T352
Test name
Test status
Simulation time 217767627 ps
CPU time 5.52 seconds
Started Aug 02 04:48:49 PM PDT 24
Finished Aug 02 04:48:55 PM PDT 24
Peak memory 198572 kb
Host smart-efec2214-5967-4218-9492-cd135421c88a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704542049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2704542049
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3780291344
Short name T566
Test name
Test status
Simulation time 1233609862 ps
CPU time 1 seconds
Started Aug 02 04:48:45 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 197100 kb
Host smart-828c862e-5170-4d0c-8b8b-086bd814b70a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780291344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3780291344
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2789501456
Short name T130
Test name
Test status
Simulation time 28430815 ps
CPU time 0.85 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:48:53 PM PDT 24
Peak memory 196800 kb
Host smart-44757b13-5007-43ba-b9f8-72916666f964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789501456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2789501456
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1235869393
Short name T166
Test name
Test status
Simulation time 289847150 ps
CPU time 3.07 seconds
Started Aug 02 04:48:54 PM PDT 24
Finished Aug 02 04:48:57 PM PDT 24
Peak memory 198656 kb
Host smart-e8251629-fc6e-40f1-a80a-dc932c05cf58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235869393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1235869393
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.223445037
Short name T331
Test name
Test status
Simulation time 159462991 ps
CPU time 1.34 seconds
Started Aug 02 04:48:47 PM PDT 24
Finished Aug 02 04:48:49 PM PDT 24
Peak memory 196640 kb
Host smart-c509e075-64d2-4076-943c-1777cba268d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223445037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
223445037
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.400872322
Short name T423
Test name
Test status
Simulation time 331540367 ps
CPU time 1.2 seconds
Started Aug 02 04:48:51 PM PDT 24
Finished Aug 02 04:48:52 PM PDT 24
Peak memory 197552 kb
Host smart-6cc3d26e-509f-4f56-8e1e-a1d9989ed784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400872322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.400872322
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.581734308
Short name T673
Test name
Test status
Simulation time 44484550 ps
CPU time 1.08 seconds
Started Aug 02 04:48:50 PM PDT 24
Finished Aug 02 04:48:51 PM PDT 24
Peak memory 197000 kb
Host smart-8613485d-76d4-4b22-8a8b-9e0bbd8e5799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581734308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.581734308
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1284547682
Short name T6
Test name
Test status
Simulation time 375468440 ps
CPU time 4.54 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:47 PM PDT 24
Peak memory 198504 kb
Host smart-1c81da29-03db-47d3-9fec-92a902a911af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284547682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1284547682
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.582921906
Short name T236
Test name
Test status
Simulation time 24894027 ps
CPU time 0.86 seconds
Started Aug 02 04:48:45 PM PDT 24
Finished Aug 02 04:48:46 PM PDT 24
Peak memory 196828 kb
Host smart-f9969565-0dee-4906-81c7-a53a65ed408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582921906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.582921906
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2041921802
Short name T32
Test name
Test status
Simulation time 83122473 ps
CPU time 1.18 seconds
Started Aug 02 04:48:42 PM PDT 24
Finished Aug 02 04:48:44 PM PDT 24
Peak memory 196700 kb
Host smart-3f8c038a-b5b7-48ff-bf6a-2ad5f3aea76c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041921802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2041921802
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1715147607
Short name T653
Test name
Test status
Simulation time 24422786477 ps
CPU time 167.56 seconds
Started Aug 02 04:48:57 PM PDT 24
Finished Aug 02 04:51:45 PM PDT 24
Peak memory 198728 kb
Host smart-64cc746b-73b8-484c-bf52-00ed566bb30e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715147607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1715147607
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3273633934
Short name T78
Test name
Test status
Simulation time 53325797338 ps
CPU time 582.43 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:58:34 PM PDT 24
Peak memory 198828 kb
Host smart-aed7e387-5699-43aa-ada8-1449764f735d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3273633934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3273633934
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3258209333
Short name T146
Test name
Test status
Simulation time 24338478 ps
CPU time 0.58 seconds
Started Aug 02 04:49:08 PM PDT 24
Finished Aug 02 04:49:09 PM PDT 24
Peak memory 195128 kb
Host smart-5bf826c7-46f3-4cbf-b4a9-18898e1f3938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258209333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3258209333
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1722843603
Short name T481
Test name
Test status
Simulation time 193511889 ps
CPU time 0.9 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:02 PM PDT 24
Peak memory 196888 kb
Host smart-ee7fdbf9-31d4-4883-8e86-64b02a323f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722843603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1722843603
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3715382037
Short name T308
Test name
Test status
Simulation time 549448143 ps
CPU time 13.73 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:18 PM PDT 24
Peak memory 198468 kb
Host smart-4a52068d-a1a7-44a5-a1cf-40501a9aac69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715382037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3715382037
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4294136781
Short name T669
Test name
Test status
Simulation time 205032807 ps
CPU time 0.84 seconds
Started Aug 02 04:48:58 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 196232 kb
Host smart-6635102d-116a-47b8-b91e-beced66d2f96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294136781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4294136781
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2646586999
Short name T652
Test name
Test status
Simulation time 165733440 ps
CPU time 0.96 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:56 PM PDT 24
Peak memory 196412 kb
Host smart-e8529e8a-276c-45e8-9fb4-07f56b332037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646586999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2646586999
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2636387847
Short name T86
Test name
Test status
Simulation time 23551418 ps
CPU time 0.97 seconds
Started Aug 02 04:48:51 PM PDT 24
Finished Aug 02 04:48:52 PM PDT 24
Peak memory 196888 kb
Host smart-394e26d0-c8fe-4fc0-890d-9f96caeec02f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636387847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2636387847
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1913737560
Short name T712
Test name
Test status
Simulation time 46662143 ps
CPU time 0.91 seconds
Started Aug 02 04:48:58 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 196016 kb
Host smart-c9c11b2a-8fd5-45a0-aca5-7a43dc71062c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913737560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1913737560
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3090960584
Short name T371
Test name
Test status
Simulation time 48176332 ps
CPU time 1.01 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 196392 kb
Host smart-6c36ca8d-6f05-4eae-950b-34a0acf04b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090960584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3090960584
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2665348649
Short name T70
Test name
Test status
Simulation time 64381419 ps
CPU time 0.82 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:02 PM PDT 24
Peak memory 197708 kb
Host smart-11b268cd-b98c-41ca-8221-d012f9af96a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665348649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2665348649
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2282854621
Short name T24
Test name
Test status
Simulation time 72266500 ps
CPU time 3.46 seconds
Started Aug 02 04:49:03 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 198388 kb
Host smart-a96ea09b-61dd-49a4-bac9-df52a89240df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282854621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2282854621
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2776656357
Short name T688
Test name
Test status
Simulation time 69288343 ps
CPU time 1.4 seconds
Started Aug 02 04:48:52 PM PDT 24
Finished Aug 02 04:48:53 PM PDT 24
Peak memory 197116 kb
Host smart-090d3a7a-9376-4d88-aa02-438ceb77537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776656357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2776656357
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1569391766
Short name T469
Test name
Test status
Simulation time 47399709 ps
CPU time 1.17 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:02 PM PDT 24
Peak memory 196436 kb
Host smart-65d46f27-3a32-4634-8481-b624ca07d52a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569391766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1569391766
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1829222781
Short name T531
Test name
Test status
Simulation time 86535831826 ps
CPU time 66.41 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:50:07 PM PDT 24
Peak memory 198712 kb
Host smart-091325c5-19ab-473f-95c3-fdebe69fee44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829222781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1829222781
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3753457016
Short name T77
Test name
Test status
Simulation time 30133328732 ps
CPU time 479.26 seconds
Started Aug 02 04:50:09 PM PDT 24
Finished Aug 02 04:58:08 PM PDT 24
Peak memory 198200 kb
Host smart-796cc6e4-80a6-4cad-87fc-65c9b4deb51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3753457016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3753457016
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.4198027630
Short name T706
Test name
Test status
Simulation time 16509793 ps
CPU time 0.57 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:56 PM PDT 24
Peak memory 195076 kb
Host smart-55e1f4a3-5227-4e4f-a7b9-7fa1dbb0daa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198027630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4198027630
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2684124571
Short name T577
Test name
Test status
Simulation time 19245655 ps
CPU time 0.76 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 195808 kb
Host smart-02fd2ee7-75f1-46c1-8785-b7eec02d1d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684124571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2684124571
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.348027371
Short name T701
Test name
Test status
Simulation time 1575047534 ps
CPU time 12.52 seconds
Started Aug 02 04:50:09 PM PDT 24
Finished Aug 02 04:50:21 PM PDT 24
Peak memory 197936 kb
Host smart-d0bfb376-a2e8-4678-91b8-c9e0eb44ccc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348027371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.348027371
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3169659140
Short name T369
Test name
Test status
Simulation time 35193739 ps
CPU time 0.74 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 197096 kb
Host smart-2aafb3b6-6ea8-41c4-ab29-1005f0184cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169659140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3169659140
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1692751029
Short name T157
Test name
Test status
Simulation time 124813242 ps
CPU time 1.4 seconds
Started Aug 02 04:49:07 PM PDT 24
Finished Aug 02 04:49:09 PM PDT 24
Peak memory 197300 kb
Host smart-92d04e96-271e-4562-b980-5d00b45e0553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692751029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1692751029
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.265642598
Short name T220
Test name
Test status
Simulation time 316460674 ps
CPU time 3.05 seconds
Started Aug 02 04:48:56 PM PDT 24
Finished Aug 02 04:48:59 PM PDT 24
Peak memory 198560 kb
Host smart-90204e79-ecbb-4ff7-a3c9-99b87277aae7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265642598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.265642598
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2569022473
Short name T416
Test name
Test status
Simulation time 72913931 ps
CPU time 1.73 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 196904 kb
Host smart-4e7531ac-7ebc-4ea5-b44c-93c4d7a9b00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569022473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2569022473
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.530111646
Short name T40
Test name
Test status
Simulation time 266543432 ps
CPU time 1.19 seconds
Started Aug 02 04:49:00 PM PDT 24
Finished Aug 02 04:49:01 PM PDT 24
Peak memory 196292 kb
Host smart-88e14aa9-7c48-427d-aecc-7bb2c7d179e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530111646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.530111646
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.971061633
Short name T552
Test name
Test status
Simulation time 32261015 ps
CPU time 0.86 seconds
Started Aug 02 04:49:06 PM PDT 24
Finished Aug 02 04:49:07 PM PDT 24
Peak memory 195924 kb
Host smart-7569cd51-aeb0-44ba-a828-c409f5b8e167
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971061633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.971061633
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.524895188
Short name T185
Test name
Test status
Simulation time 164541556 ps
CPU time 1.81 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:07 PM PDT 24
Peak memory 198552 kb
Host smart-2fb4ca6c-2686-434d-8d77-55e5711e09d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524895188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.524895188
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3970561854
Short name T285
Test name
Test status
Simulation time 144723745 ps
CPU time 0.98 seconds
Started Aug 02 04:49:00 PM PDT 24
Finished Aug 02 04:49:01 PM PDT 24
Peak memory 196224 kb
Host smart-e860b87a-37a3-4c82-8553-ba4e7ed1fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970561854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3970561854
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2045916662
Short name T576
Test name
Test status
Simulation time 56071724 ps
CPU time 1 seconds
Started Aug 02 04:48:55 PM PDT 24
Finished Aug 02 04:48:57 PM PDT 24
Peak memory 196712 kb
Host smart-228c73fa-6a58-4985-9bf4-6cbff3fc824f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045916662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2045916662
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2234800807
Short name T8
Test name
Test status
Simulation time 6650497773 ps
CPU time 68.91 seconds
Started Aug 02 04:48:57 PM PDT 24
Finished Aug 02 04:50:06 PM PDT 24
Peak memory 198700 kb
Host smart-0e813062-f601-4236-9e12-b36a1561832d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234800807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2234800807
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1383751715
Short name T101
Test name
Test status
Simulation time 281748949139 ps
CPU time 1705.43 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 05:17:29 PM PDT 24
Peak memory 198724 kb
Host smart-f29e4fc7-dffd-4bfa-b74e-e835a193aa09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1383751715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1383751715
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2486332529
Short name T666
Test name
Test status
Simulation time 21656125 ps
CPU time 0.54 seconds
Started Aug 02 04:49:00 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 194408 kb
Host smart-f1590202-62a6-4cd1-ac37-3f7ab939a37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486332529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2486332529
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.749004929
Short name T191
Test name
Test status
Simulation time 17737408 ps
CPU time 0.68 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 195156 kb
Host smart-fbc177fa-7952-433e-9347-9c1e5c8a0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749004929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.749004929
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3760029305
Short name T610
Test name
Test status
Simulation time 396269496 ps
CPU time 19.52 seconds
Started Aug 02 04:49:02 PM PDT 24
Finished Aug 02 04:49:22 PM PDT 24
Peak memory 197276 kb
Host smart-9911387f-e772-45cd-b16c-12d2d609419e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760029305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3760029305
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3275390138
Short name T18
Test name
Test status
Simulation time 50019901 ps
CPU time 0.79 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 196148 kb
Host smart-c186b901-9c67-4859-a630-812d6c59cd5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275390138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3275390138
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3175009643
Short name T439
Test name
Test status
Simulation time 655243282 ps
CPU time 1.4 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 197572 kb
Host smart-6e5b0b27-09fd-43ae-8004-74fb61d42ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175009643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3175009643
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.258361416
Short name T503
Test name
Test status
Simulation time 39479037 ps
CPU time 1.58 seconds
Started Aug 02 04:48:53 PM PDT 24
Finished Aug 02 04:48:55 PM PDT 24
Peak memory 196924 kb
Host smart-5580234c-c7c6-4ba7-8a07-0aa56e8d6257
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258361416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.258361416
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1168532839
Short name T67
Test name
Test status
Simulation time 159459432 ps
CPU time 3.38 seconds
Started Aug 02 04:49:03 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 197592 kb
Host smart-da507162-ad56-4750-bd42-074e84dc2546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168532839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1168532839
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3397881208
Short name T426
Test name
Test status
Simulation time 29084892 ps
CPU time 0.75 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 195804 kb
Host smart-d5582293-c92e-427d-9d5a-098a6accbcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397881208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3397881208
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.681013121
Short name T713
Test name
Test status
Simulation time 28408329 ps
CPU time 0.78 seconds
Started Aug 02 04:49:02 PM PDT 24
Finished Aug 02 04:49:03 PM PDT 24
Peak memory 195956 kb
Host smart-417fbcfa-5c03-4b45-9be7-cf485560b175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681013121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.681013121
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3874550718
Short name T617
Test name
Test status
Simulation time 243387664 ps
CPU time 2.79 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:04 PM PDT 24
Peak memory 198460 kb
Host smart-634cddc7-f5f2-4eb1-8ae2-52d6ad8329f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874550718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3874550718
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4001705439
Short name T182
Test name
Test status
Simulation time 110267658 ps
CPU time 0.9 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 196868 kb
Host smart-d2f9d745-9120-4afd-b32f-c891415587a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001705439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4001705439
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.117325078
Short name T647
Test name
Test status
Simulation time 156733582 ps
CPU time 1.05 seconds
Started Aug 02 04:49:04 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 196876 kb
Host smart-7fefc6e6-2aba-444b-8280-ed994d19a443
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117325078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.117325078
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4000882313
Short name T606
Test name
Test status
Simulation time 12790200219 ps
CPU time 182.77 seconds
Started Aug 02 04:49:07 PM PDT 24
Finished Aug 02 04:52:10 PM PDT 24
Peak memory 198692 kb
Host smart-b15ec875-be5f-4ea7-ae20-e9b2481a6d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000882313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4000882313
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1413624036
Short name T243
Test name
Test status
Simulation time 205231910 ps
CPU time 0.92 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 196176 kb
Host smart-95e00c21-778f-48f9-acd9-aa571279aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413624036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1413624036
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2578907058
Short name T338
Test name
Test status
Simulation time 85097996 ps
CPU time 3.97 seconds
Started Aug 02 04:48:57 PM PDT 24
Finished Aug 02 04:49:01 PM PDT 24
Peak memory 195972 kb
Host smart-00f2f71f-91c2-475d-95ee-4aa313f6ff54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578907058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2578907058
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2675212984
Short name T299
Test name
Test status
Simulation time 95144156 ps
CPU time 0.9 seconds
Started Aug 02 04:49:02 PM PDT 24
Finished Aug 02 04:49:03 PM PDT 24
Peak memory 197088 kb
Host smart-68578264-ad00-480f-88ef-050791612270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675212984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2675212984
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2812995869
Short name T590
Test name
Test status
Simulation time 108373953 ps
CPU time 0.83 seconds
Started Aug 02 04:49:09 PM PDT 24
Finished Aug 02 04:49:10 PM PDT 24
Peak memory 197024 kb
Host smart-2c34d910-ba84-476f-8d38-8c65ee2d02fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812995869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2812995869
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1047476111
Short name T629
Test name
Test status
Simulation time 91163848 ps
CPU time 3.43 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:08 PM PDT 24
Peak memory 198576 kb
Host smart-decd2839-de65-4ee3-a64d-07a57402a824
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047476111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1047476111
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3205564010
Short name T686
Test name
Test status
Simulation time 302479914 ps
CPU time 1.98 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:07 PM PDT 24
Peak memory 196468 kb
Host smart-897c79dd-f8c7-4129-a288-8fe977b73c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205564010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3205564010
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2177974650
Short name T33
Test name
Test status
Simulation time 421378438 ps
CPU time 1.27 seconds
Started Aug 02 04:48:48 PM PDT 24
Finished Aug 02 04:48:50 PM PDT 24
Peak memory 198580 kb
Host smart-bb3cb61f-f3c5-44ac-8e42-5de5e56c6811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177974650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2177974650
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4287471858
Short name T210
Test name
Test status
Simulation time 92872075 ps
CPU time 0.98 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:49:02 PM PDT 24
Peak memory 197224 kb
Host smart-4f1959b1-064c-447d-8c83-7e8b8a23a152
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287471858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4287471858
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2279226204
Short name T7
Test name
Test status
Simulation time 349336979 ps
CPU time 1.48 seconds
Started Aug 02 04:49:02 PM PDT 24
Finished Aug 02 04:49:09 PM PDT 24
Peak memory 198408 kb
Host smart-2baf42c6-7236-4366-8774-ac4f4d0dc537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279226204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2279226204
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2143109777
Short name T501
Test name
Test status
Simulation time 189203503 ps
CPU time 0.78 seconds
Started Aug 02 04:49:09 PM PDT 24
Finished Aug 02 04:49:10 PM PDT 24
Peak memory 196496 kb
Host smart-9c6bf9e3-aacd-4099-90af-19febe47c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143109777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2143109777
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4019516059
Short name T468
Test name
Test status
Simulation time 59120949 ps
CPU time 1.19 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 196096 kb
Host smart-5c1d568e-f13c-49cf-abb0-a007a4f174c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019516059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4019516059
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1411928779
Short name T696
Test name
Test status
Simulation time 4939484351 ps
CPU time 110.18 seconds
Started Aug 02 04:49:57 PM PDT 24
Finished Aug 02 04:51:48 PM PDT 24
Peak memory 197716 kb
Host smart-f388855c-b802-4db9-bc51-02f7326a5051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411928779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1411928779
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2398545360
Short name T335
Test name
Test status
Simulation time 51851585 ps
CPU time 0.57 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 194348 kb
Host smart-5ff992f8-5e5a-48bc-8589-99641b57041b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398545360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2398545360
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.4213692676
Short name T674
Test name
Test status
Simulation time 103308980 ps
CPU time 0.94 seconds
Started Aug 02 04:48:59 PM PDT 24
Finished Aug 02 04:49:00 PM PDT 24
Peak memory 197560 kb
Host smart-bdda598e-7555-4b0c-90e5-e393a8134a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213692676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.4213692676
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1342890954
Short name T679
Test name
Test status
Simulation time 3009269493 ps
CPU time 25.74 seconds
Started Aug 02 04:49:16 PM PDT 24
Finished Aug 02 04:49:42 PM PDT 24
Peak memory 197552 kb
Host smart-4639f8ca-bd7a-483f-928d-007682ff5c13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342890954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1342890954
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4293545472
Short name T377
Test name
Test status
Simulation time 58133184 ps
CPU time 0.63 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:05 PM PDT 24
Peak memory 195300 kb
Host smart-5db3e218-0e4f-47ab-9a8b-7943c940ca89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293545472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4293545472
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1132448969
Short name T548
Test name
Test status
Simulation time 180398707 ps
CPU time 1.12 seconds
Started Aug 02 04:49:07 PM PDT 24
Finished Aug 02 04:49:09 PM PDT 24
Peak memory 197132 kb
Host smart-eb447a62-5896-4241-b539-e42423ed5ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132448969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1132448969
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2798085078
Short name T184
Test name
Test status
Simulation time 44230720 ps
CPU time 1.12 seconds
Started Aug 02 04:49:05 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 198056 kb
Host smart-5923a28c-ac3e-4604-84fa-b5989022cde8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798085078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2798085078
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3600032826
Short name T288
Test name
Test status
Simulation time 255088485 ps
CPU time 1.63 seconds
Started Aug 02 04:49:08 PM PDT 24
Finished Aug 02 04:49:10 PM PDT 24
Peak memory 197308 kb
Host smart-fc9fd054-3d8c-4aa6-9969-297a07ab7db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600032826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3600032826
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.463540732
Short name T286
Test name
Test status
Simulation time 34042836 ps
CPU time 1.1 seconds
Started Aug 02 04:49:08 PM PDT 24
Finished Aug 02 04:49:09 PM PDT 24
Peak memory 197052 kb
Host smart-890d1e1b-4939-4553-beb0-82c73b84a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463540732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.463540732
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2767108810
Short name T413
Test name
Test status
Simulation time 20456601 ps
CPU time 0.65 seconds
Started Aug 02 04:49:10 PM PDT 24
Finished Aug 02 04:49:11 PM PDT 24
Peak memory 194680 kb
Host smart-65c1e9e1-15f8-440d-a76e-17a60723b737
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767108810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2767108810
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.176305212
Short name T493
Test name
Test status
Simulation time 233189263 ps
CPU time 2.03 seconds
Started Aug 02 04:49:20 PM PDT 24
Finished Aug 02 04:49:22 PM PDT 24
Peak memory 198372 kb
Host smart-207e8a54-10cb-4948-b074-05c15398cd51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176305212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.176305212
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.937183393
Short name T403
Test name
Test status
Simulation time 263003095 ps
CPU time 1.05 seconds
Started Aug 02 04:49:12 PM PDT 24
Finished Aug 02 04:49:13 PM PDT 24
Peak memory 197000 kb
Host smart-467b3c0a-0f25-4baf-93c4-c8f39fc61661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937183393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.937183393
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.269907804
Short name T628
Test name
Test status
Simulation time 556799773 ps
CPU time 1.14 seconds
Started Aug 02 04:49:10 PM PDT 24
Finished Aug 02 04:49:11 PM PDT 24
Peak memory 197008 kb
Host smart-37100d12-fd55-4159-891c-a7b863f2f0a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269907804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.269907804
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.236243585
Short name T73
Test name
Test status
Simulation time 39787965362 ps
CPU time 108.32 seconds
Started Aug 02 04:49:01 PM PDT 24
Finished Aug 02 04:50:49 PM PDT 24
Peak memory 198640 kb
Host smart-d1a8fda6-3d6a-45c3-9b40-d3c885389111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236243585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.236243585
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3581905886
Short name T12
Test name
Test status
Simulation time 18998135 ps
CPU time 0.58 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:21 PM PDT 24
Peak memory 194496 kb
Host smart-86880eba-3d0e-4c76-96db-ffbe2779df8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581905886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3581905886
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3517202458
Short name T180
Test name
Test status
Simulation time 72461017 ps
CPU time 0.88 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 197068 kb
Host smart-7a2853a0-91a4-4830-829f-1941ab1edd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517202458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3517202458
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2470386138
Short name T30
Test name
Test status
Simulation time 639979178 ps
CPU time 22.48 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:51 PM PDT 24
Peak memory 198440 kb
Host smart-1773063b-f16a-437d-88e4-89c794e77027
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470386138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2470386138
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1116167630
Short name T479
Test name
Test status
Simulation time 37857386 ps
CPU time 0.67 seconds
Started Aug 02 04:47:26 PM PDT 24
Finished Aug 02 04:47:27 PM PDT 24
Peak memory 195016 kb
Host smart-a8b135d9-929c-4021-b8ab-cd825898f847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116167630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1116167630
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2203349901
Short name T127
Test name
Test status
Simulation time 114604862 ps
CPU time 1.33 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 197612 kb
Host smart-7e97e9b6-b917-4783-a45d-19e015dd817f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203349901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2203349901
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4113078357
Short name T547
Test name
Test status
Simulation time 43131076 ps
CPU time 1.68 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 198472 kb
Host smart-b065a014-f949-4524-872b-adf27dd1e3d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113078357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4113078357
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2241049433
Short name T17
Test name
Test status
Simulation time 159737959 ps
CPU time 2.97 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 197720 kb
Host smart-3bb6152d-1ff9-4214-ad24-1d490b5a164a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241049433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2241049433
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3533599068
Short name T624
Test name
Test status
Simulation time 28603465 ps
CPU time 0.77 seconds
Started Aug 02 04:47:28 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 196676 kb
Host smart-7f663767-6fa2-4b47-ae0a-1dc9003ae899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533599068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3533599068
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2424714717
Short name T580
Test name
Test status
Simulation time 110655964 ps
CPU time 1.08 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 196480 kb
Host smart-a3325a9e-f33d-4e29-8be5-77f0f905e7ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424714717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2424714717
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2814286810
Short name T393
Test name
Test status
Simulation time 1440985073 ps
CPU time 2.66 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 198448 kb
Host smart-3cc329e6-9dd3-4ba5-a902-7f5fdf904c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814286810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2814286810
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1485176989
Short name T342
Test name
Test status
Simulation time 47196723 ps
CPU time 0.93 seconds
Started Aug 02 04:47:19 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 196776 kb
Host smart-81c25b36-7502-45ee-bdaf-300a6cb65355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485176989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1485176989
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.280834495
Short name T665
Test name
Test status
Simulation time 53433815 ps
CPU time 0.96 seconds
Started Aug 02 04:47:23 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 196152 kb
Host smart-66d18e29-f7eb-4674-9bb3-7139a78580d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280834495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.280834495
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1619308272
Short name T132
Test name
Test status
Simulation time 14404127788 ps
CPU time 177.45 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:50:31 PM PDT 24
Peak memory 198764 kb
Host smart-0f7b21b8-bc3b-4ed0-9a49-dd4cb0a1aa9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619308272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1619308272
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2278574622
Short name T79
Test name
Test status
Simulation time 19071029970 ps
CPU time 555.4 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:56:47 PM PDT 24
Peak memory 198840 kb
Host smart-8bfe77fd-1990-4f55-bf67-764764564d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2278574622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2278574622
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3049125439
Short name T284
Test name
Test status
Simulation time 17467355 ps
CPU time 0.58 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 195200 kb
Host smart-61f2ef08-245a-4f1b-a6fa-40444d052931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049125439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3049125439
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2672211752
Short name T310
Test name
Test status
Simulation time 38468614 ps
CPU time 0.75 seconds
Started Aug 02 04:47:27 PM PDT 24
Finished Aug 02 04:47:28 PM PDT 24
Peak memory 195808 kb
Host smart-41dc485b-05f4-4233-9309-a38e25a48aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672211752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2672211752
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3467773599
Short name T637
Test name
Test status
Simulation time 655572660 ps
CPU time 3.98 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 196320 kb
Host smart-c50533e3-779d-434f-90c6-8f0a4e86ff8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467773599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3467773599
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3766027370
Short name T258
Test name
Test status
Simulation time 432335209 ps
CPU time 1.01 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 197048 kb
Host smart-41ae5fbd-6bc8-4754-afe8-7ea24e6373fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766027370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3766027370
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3375867005
Short name T395
Test name
Test status
Simulation time 448663584 ps
CPU time 1.2 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:34 PM PDT 24
Peak memory 196320 kb
Host smart-88bb018e-0545-477c-9db7-38e59e2d7f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375867005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3375867005
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4173138025
Short name T235
Test name
Test status
Simulation time 1278131097 ps
CPU time 2.7 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196856 kb
Host smart-b03dfad6-8e44-4a61-885f-f7e9666afde5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173138025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4173138025
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4128265178
Short name T700
Test name
Test status
Simulation time 40162390 ps
CPU time 0.91 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 196512 kb
Host smart-2376d1d2-7afb-41d4-aa8b-d020c2f3d715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128265178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4128265178
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.825699206
Short name T265
Test name
Test status
Simulation time 81926831 ps
CPU time 0.95 seconds
Started Aug 02 04:47:21 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 196476 kb
Host smart-cf318cc6-86dd-499a-8ce4-9565f6074b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825699206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.825699206
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.766519407
Short name T655
Test name
Test status
Simulation time 131834071 ps
CPU time 0.94 seconds
Started Aug 02 04:47:18 PM PDT 24
Finished Aug 02 04:47:20 PM PDT 24
Peak memory 197140 kb
Host smart-5a933ded-d60c-49dc-ba06-7b7b080a80fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766519407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.766519407
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4284076004
Short name T347
Test name
Test status
Simulation time 8547639958 ps
CPU time 6.18 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:47:43 PM PDT 24
Peak memory 198648 kb
Host smart-3eda7e14-b3a2-4906-85c7-7a67f7e74c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284076004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.4284076004
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2454215613
Short name T618
Test name
Test status
Simulation time 234115224 ps
CPU time 1.16 seconds
Started Aug 02 04:47:20 PM PDT 24
Finished Aug 02 04:47:22 PM PDT 24
Peak memory 197092 kb
Host smart-f7cb2e23-5fe7-4852-bd0d-a194c2ded92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454215613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2454215613
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1105256902
Short name T147
Test name
Test status
Simulation time 147522302 ps
CPU time 1.08 seconds
Started Aug 02 04:47:23 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 196200 kb
Host smart-3e4197e9-5eb6-4eb4-b0d0-201f84501efc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105256902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1105256902
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.331642285
Short name T351
Test name
Test status
Simulation time 2713728481 ps
CPU time 69.46 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:48:39 PM PDT 24
Peak memory 198720 kb
Host smart-df6c523e-cdcb-4b35-92f1-2637a7a15f3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331642285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.331642285
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2882718589
Short name T657
Test name
Test status
Simulation time 18656290 ps
CPU time 0.55 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 194336 kb
Host smart-2721a650-303b-4168-a76e-264fcdf0ed0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882718589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2882718589
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1471455235
Short name T109
Test name
Test status
Simulation time 48346660 ps
CPU time 0.77 seconds
Started Aug 02 04:47:36 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 195804 kb
Host smart-cedd039b-f64d-4591-b112-42325b21e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471455235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1471455235
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.437947223
Short name T598
Test name
Test status
Simulation time 1566915581 ps
CPU time 13.24 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:49 PM PDT 24
Peak memory 195988 kb
Host smart-fd9c6305-fcba-4eaa-b016-2837ab719838
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437947223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.437947223
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.382515566
Short name T710
Test name
Test status
Simulation time 28670490 ps
CPU time 0.65 seconds
Started Aug 02 04:47:39 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 195076 kb
Host smart-65487d85-4efb-44bd-aa96-5f5827df7b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382515566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.382515566
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1298015587
Short name T54
Test name
Test status
Simulation time 33870975 ps
CPU time 0.96 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 196656 kb
Host smart-59941d0a-9c6b-4143-8bec-28660abeac3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298015587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1298015587
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2029808471
Short name T396
Test name
Test status
Simulation time 278466856 ps
CPU time 3.09 seconds
Started Aug 02 04:47:41 PM PDT 24
Finished Aug 02 04:47:44 PM PDT 24
Peak memory 198552 kb
Host smart-70288707-a93d-4276-818c-25093b413f7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029808471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2029808471
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3008486830
Short name T218
Test name
Test status
Simulation time 756147319 ps
CPU time 2.76 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 196972 kb
Host smart-6295c8b2-af7b-4235-b33f-6cb714a64e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008486830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3008486830
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4049863390
Short name T170
Test name
Test status
Simulation time 68044585 ps
CPU time 1.22 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 197560 kb
Host smart-056d8842-a8a8-4632-89a1-3195317b909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049863390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4049863390
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.916600995
Short name T96
Test name
Test status
Simulation time 206946549 ps
CPU time 1.13 seconds
Started Aug 02 04:47:36 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 196576 kb
Host smart-9a5d46cf-dc0a-4e18-980e-75b117c65778
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916600995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.916600995
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2432973551
Short name T173
Test name
Test status
Simulation time 160406885 ps
CPU time 1.68 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 198456 kb
Host smart-6609ef16-a67b-4fd7-aa95-afcbc2308fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432973551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2432973551
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2515876231
Short name T188
Test name
Test status
Simulation time 771371815 ps
CPU time 1.23 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 197320 kb
Host smart-7e7872fe-e753-454a-9244-b232843d30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515876231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2515876231
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3013008128
Short name T482
Test name
Test status
Simulation time 108940945 ps
CPU time 1.05 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 196144 kb
Host smart-429afe5a-5fff-4093-9f0a-0e46155b22a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013008128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3013008128
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.709021245
Short name T373
Test name
Test status
Simulation time 109054483070 ps
CPU time 78.43 seconds
Started Aug 02 04:47:36 PM PDT 24
Finished Aug 02 04:48:54 PM PDT 24
Peak memory 198664 kb
Host smart-41a7e34f-cf1a-484e-aeb4-fa54bac7910d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709021245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.709021245
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2059071833
Short name T81
Test name
Test status
Simulation time 197932859174 ps
CPU time 1567.73 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 05:13:39 PM PDT 24
Peak memory 198760 kb
Host smart-f7452a67-3fa7-4737-ad5b-a385292ccad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2059071833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2059071833
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3710945202
Short name T71
Test name
Test status
Simulation time 36807419 ps
CPU time 0.54 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:34 PM PDT 24
Peak memory 194480 kb
Host smart-3b03b2e3-1720-406a-9791-1d90ebb8ef49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710945202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3710945202
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2563087460
Short name T497
Test name
Test status
Simulation time 21684547 ps
CPU time 0.65 seconds
Started Aug 02 04:47:36 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 194492 kb
Host smart-02d2a2ce-910b-4272-a15f-5992ea22fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563087460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2563087460
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2848954031
Short name T25
Test name
Test status
Simulation time 3527349744 ps
CPU time 24.68 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:55 PM PDT 24
Peak memory 197932 kb
Host smart-fde851e1-f4e9-4ff1-a97f-19181b8cb463
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848954031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2848954031
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2507086621
Short name T212
Test name
Test status
Simulation time 246946369 ps
CPU time 0.86 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 197288 kb
Host smart-5259bff3-b706-4d7c-8724-e52f3bb1bcb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507086621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2507086621
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1661461620
Short name T450
Test name
Test status
Simulation time 89513475 ps
CPU time 1.29 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:32 PM PDT 24
Peak memory 198572 kb
Host smart-b2a6b9fd-8f61-480b-826e-ea7503862c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661461620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1661461620
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1973890146
Short name T631
Test name
Test status
Simulation time 111983717 ps
CPU time 2.19 seconds
Started Aug 02 04:47:32 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 198716 kb
Host smart-0413fae2-4d15-4278-8f37-47bd39a0cf7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973890146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1973890146
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3808182602
Short name T670
Test name
Test status
Simulation time 93481618 ps
CPU time 2.79 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 196324 kb
Host smart-3745303f-d68f-48ef-9c53-d8697ddc17cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808182602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3808182602
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1026838062
Short name T144
Test name
Test status
Simulation time 16529107 ps
CPU time 0.71 seconds
Started Aug 02 04:47:29 PM PDT 24
Finished Aug 02 04:47:30 PM PDT 24
Peak memory 194756 kb
Host smart-24058e1d-b070-402d-b1be-5760e0a45321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026838062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1026838062
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1887243849
Short name T616
Test name
Test status
Simulation time 299757254 ps
CPU time 1.17 seconds
Started Aug 02 04:47:35 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 197328 kb
Host smart-8a7aa0b0-ae9d-4605-b0a1-255aca289ca4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887243849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1887243849
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2292339373
Short name T228
Test name
Test status
Simulation time 292063864 ps
CPU time 1.72 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 198500 kb
Host smart-3c577dcc-0d9b-4299-bcee-b2b35e27f0a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292339373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2292339373
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3285372679
Short name T172
Test name
Test status
Simulation time 33559649 ps
CPU time 0.97 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 196392 kb
Host smart-691946a3-3d41-4c28-b35a-8c39d52062a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285372679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3285372679
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2684079252
Short name T400
Test name
Test status
Simulation time 158983053 ps
CPU time 1.19 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:47:39 PM PDT 24
Peak memory 197008 kb
Host smart-7f7d9337-2b07-410c-b7ce-ebf4df599530
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684079252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2684079252
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3622563333
Short name T255
Test name
Test status
Simulation time 42051266798 ps
CPU time 118.56 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:49:33 PM PDT 24
Peak memory 198832 kb
Host smart-e9dde887-8a02-4ca5-b177-c571b1cce86c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622563333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3622563333
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2264488511
Short name T295
Test name
Test status
Simulation time 51444763 ps
CPU time 0.56 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:33 PM PDT 24
Peak memory 194340 kb
Host smart-9b08b3fb-bf70-4033-abc0-3e6867e3c419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264488511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2264488511
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3658202207
Short name T372
Test name
Test status
Simulation time 63942928 ps
CPU time 0.81 seconds
Started Aug 02 04:47:30 PM PDT 24
Finished Aug 02 04:47:31 PM PDT 24
Peak memory 196380 kb
Host smart-0ecf33d4-0c08-4bc2-9c3a-aafcd39f3852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658202207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3658202207
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2508957644
Short name T72
Test name
Test status
Simulation time 5802936204 ps
CPU time 23.1 seconds
Started Aug 02 04:47:31 PM PDT 24
Finished Aug 02 04:47:54 PM PDT 24
Peak memory 197960 kb
Host smart-0a8cb96b-377e-4050-a0e8-deeba8583212
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508957644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2508957644
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2217347136
Short name T29
Test name
Test status
Simulation time 127912296 ps
CPU time 0.68 seconds
Started Aug 02 04:47:41 PM PDT 24
Finished Aug 02 04:47:42 PM PDT 24
Peak memory 195200 kb
Host smart-afe5a2fa-601a-443d-acd2-57b753d4c7c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217347136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2217347136
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2151963565
Short name T197
Test name
Test status
Simulation time 39021415 ps
CPU time 1.08 seconds
Started Aug 02 04:47:26 PM PDT 24
Finished Aug 02 04:47:27 PM PDT 24
Peak memory 196468 kb
Host smart-735ea11c-a923-4b01-b22b-5380e392cede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151963565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2151963565
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3575891955
Short name T26
Test name
Test status
Simulation time 63278074 ps
CPU time 1.32 seconds
Started Aug 02 04:47:37 PM PDT 24
Finished Aug 02 04:47:38 PM PDT 24
Peak memory 196940 kb
Host smart-e0e25e22-73e4-47bf-85e1-861b9a4cb15b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575891955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3575891955
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1632446248
Short name T405
Test name
Test status
Simulation time 328148201 ps
CPU time 2.42 seconds
Started Aug 02 04:47:33 PM PDT 24
Finished Aug 02 04:47:36 PM PDT 24
Peak memory 198556 kb
Host smart-07dd59cf-03a3-4542-9fd4-40a4a5420240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632446248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1632446248
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2255647522
Short name T84
Test name
Test status
Simulation time 288247202 ps
CPU time 1.13 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 196320 kb
Host smart-78097fd4-ade7-45d6-9ebe-539f1565bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255647522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2255647522
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3125122794
Short name T583
Test name
Test status
Simulation time 104303297 ps
CPU time 1.17 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 197004 kb
Host smart-cb746127-2b4e-4ab2-be79-3e2411e1fc96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125122794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3125122794
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2161476885
Short name T389
Test name
Test status
Simulation time 317078010 ps
CPU time 4.02 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:43 PM PDT 24
Peak memory 198352 kb
Host smart-a646c41c-bff6-4e75-93a0-031e72f850c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161476885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2161476885
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1907003113
Short name T44
Test name
Test status
Simulation time 231490193 ps
CPU time 1.2 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:47:40 PM PDT 24
Peak memory 196676 kb
Host smart-a2d62e92-447a-4ee0-9fe5-8c8c9e1f50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907003113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1907003113
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1308871541
Short name T554
Test name
Test status
Simulation time 123321920 ps
CPU time 0.94 seconds
Started Aug 02 04:47:34 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 196196 kb
Host smart-2390c740-e961-42de-ac55-1ebb3c6d5621
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308871541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1308871541
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2895894709
Short name T409
Test name
Test status
Simulation time 7271727148 ps
CPU time 90.29 seconds
Started Aug 02 04:47:38 PM PDT 24
Finished Aug 02 04:49:08 PM PDT 24
Peak memory 198752 kb
Host smart-8424e766-abcb-4831-bcce-932a97f9ffcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895894709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2895894709
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1319789924
Short name T856
Test name
Test status
Simulation time 43460795 ps
CPU time 0.96 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196292 kb
Host smart-27a620c6-7b58-46b3-b0d1-3bb5fd8a2d74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1319789924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1319789924
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1647122680
Short name T848
Test name
Test status
Simulation time 77117304 ps
CPU time 0.84 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:16 PM PDT 24
Peak memory 195072 kb
Host smart-93514866-ce89-4eed-8c07-034b65fcebaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647122680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1647122680
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1037267268
Short name T922
Test name
Test status
Simulation time 63748031 ps
CPU time 1.29 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 197828 kb
Host smart-1e9ecf6d-2591-4cec-ad9e-8448df2ee13b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1037267268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1037267268
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644694698
Short name T934
Test name
Test status
Simulation time 39703043 ps
CPU time 1.13 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196476 kb
Host smart-303fbecf-a182-4cff-8835-9741c8942808
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644694698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3644694698
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2467747860
Short name T932
Test name
Test status
Simulation time 260103424 ps
CPU time 1.14 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:26 PM PDT 24
Peak memory 195440 kb
Host smart-e83743f9-850c-4bca-94e9-833d73066924
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2467747860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2467747860
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17546972
Short name T863
Test name
Test status
Simulation time 118409060 ps
CPU time 1.16 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:45 PM PDT 24
Peak memory 197812 kb
Host smart-99a4054e-cb87-46d1-a0f5-5295109b1ca8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.17546972
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.239701881
Short name T885
Test name
Test status
Simulation time 65171023 ps
CPU time 1.1 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 195920 kb
Host smart-959cd84c-cc9b-444b-b4e5-e5ed3768f7ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=239701881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.239701881
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.562561478
Short name T890
Test name
Test status
Simulation time 66578190 ps
CPU time 1.25 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 196052 kb
Host smart-317b08e8-ed6f-45ad-9cb3-b56118a0d05f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562561478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.562561478
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.662709705
Short name T847
Test name
Test status
Simulation time 273118223 ps
CPU time 1.24 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 197132 kb
Host smart-4acd5ebd-cba0-4523-8360-1d48c11e10a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=662709705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.662709705
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125630782
Short name T855
Test name
Test status
Simulation time 105797470 ps
CPU time 0.91 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:43 PM PDT 24
Peak memory 196880 kb
Host smart-a4e3edf1-7940-40fc-8d1d-3407fa9b3d6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125630782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3125630782
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3792474160
Short name T919
Test name
Test status
Simulation time 114833987 ps
CPU time 0.71 seconds
Started Aug 02 04:24:27 PM PDT 24
Finished Aug 02 04:24:28 PM PDT 24
Peak memory 194716 kb
Host smart-83a90fac-06ac-4572-8704-dea1b803a088
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3792474160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3792474160
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3102456724
Short name T850
Test name
Test status
Simulation time 240215086 ps
CPU time 1.01 seconds
Started Aug 02 04:23:26 PM PDT 24
Finished Aug 02 04:23:27 PM PDT 24
Peak memory 195492 kb
Host smart-6f9cd7d0-515b-47a5-9940-6884f7ec74bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102456724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3102456724
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1164268345
Short name T928
Test name
Test status
Simulation time 451915131 ps
CPU time 1.11 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:25 PM PDT 24
Peak memory 196504 kb
Host smart-4a09c2df-96ef-497f-934a-57991dd265cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1164268345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1164268345
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402544994
Short name T861
Test name
Test status
Simulation time 768478559 ps
CPU time 1.22 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 196276 kb
Host smart-9bf746d8-3dd4-4398-adb4-4aaa3f9f75f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402544994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3402544994
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.240035211
Short name T900
Test name
Test status
Simulation time 412950767 ps
CPU time 0.92 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:32 PM PDT 24
Peak memory 191056 kb
Host smart-a2b855cc-adca-458d-bea1-54d7b5c24106
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=240035211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.240035211
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4206941726
Short name T870
Test name
Test status
Simulation time 57223748 ps
CPU time 0.98 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:26 PM PDT 24
Peak memory 195328 kb
Host smart-a883bb3d-61f1-41dd-b9f6-5bb6b4d4f33d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206941726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4206941726
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.5838399
Short name T880
Test name
Test status
Simulation time 132796154 ps
CPU time 1.02 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:27 PM PDT 24
Peak memory 195812 kb
Host smart-48c1aa3d-6ccf-40c5-91fe-29022a87bb04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=5838399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.5838399
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1116926975
Short name T897
Test name
Test status
Simulation time 115990325 ps
CPU time 1.08 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:27 PM PDT 24
Peak memory 195232 kb
Host smart-229ed9d2-e3a2-4173-bd76-38a3c4ab25b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116926975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1116926975
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.472758959
Short name T891
Test name
Test status
Simulation time 47777603 ps
CPU time 0.95 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 195692 kb
Host smart-ad153371-1ec2-4779-80e0-0b5828050419
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=472758959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.472758959
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2275027118
Short name T887
Test name
Test status
Simulation time 122432963 ps
CPU time 0.73 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:42 PM PDT 24
Peak memory 195248 kb
Host smart-b8adaf48-240f-4a1d-a4ab-c9c27ff12919
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275027118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2275027118
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.329317255
Short name T868
Test name
Test status
Simulation time 44154752 ps
CPU time 1.15 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:42 PM PDT 24
Peak memory 195452 kb
Host smart-4622a27e-7ba6-4ebf-bb1e-83a4e8801651
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=329317255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.329317255
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211004478
Short name T935
Test name
Test status
Simulation time 95607579 ps
CPU time 1.44 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:45 PM PDT 24
Peak memory 196512 kb
Host smart-db57b487-4367-4649-b1b4-4df570d51e83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211004478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2211004478
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.200345532
Short name T906
Test name
Test status
Simulation time 183502817 ps
CPU time 0.97 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:42 PM PDT 24
Peak memory 195732 kb
Host smart-313b9318-811f-4794-a29c-9476d0ace00b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=200345532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.200345532
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618604142
Short name T888
Test name
Test status
Simulation time 25200402 ps
CPU time 0.79 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:42 PM PDT 24
Peak memory 195032 kb
Host smart-b4520edf-a5b1-42d0-972f-c27a4e40a1bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618604142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.618604142
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3087894526
Short name T845
Test name
Test status
Simulation time 72594010 ps
CPU time 1.13 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196364 kb
Host smart-f6b0f313-5d86-407c-a682-af8e00daada4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3087894526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3087894526
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1386548179
Short name T893
Test name
Test status
Simulation time 47724966 ps
CPU time 1.3 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196768 kb
Host smart-dd33c7ac-4701-493b-81e0-a42cc061390f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386548179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1386548179
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1514112109
Short name T898
Test name
Test status
Simulation time 184080209 ps
CPU time 1.32 seconds
Started Aug 02 04:24:41 PM PDT 24
Finished Aug 02 04:24:43 PM PDT 24
Peak memory 196356 kb
Host smart-20e3c035-a15e-460d-8eed-cacb309aeb5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1514112109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1514112109
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1938854692
Short name T917
Test name
Test status
Simulation time 77308290 ps
CPU time 1.06 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:45 PM PDT 24
Peak memory 196544 kb
Host smart-10c64bda-4939-42ea-a56b-c2346ffa9bb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938854692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1938854692
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2231189707
Short name T937
Test name
Test status
Simulation time 219497250 ps
CPU time 0.83 seconds
Started Aug 02 04:24:27 PM PDT 24
Finished Aug 02 04:24:28 PM PDT 24
Peak memory 195092 kb
Host smart-9369d305-5f0e-4156-9fe8-1429b0f156f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2231189707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2231189707
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3665815468
Short name T896
Test name
Test status
Simulation time 304170849 ps
CPU time 1.28 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 196492 kb
Host smart-8ae15b14-43d6-4363-8445-f3b975c26b80
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665815468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3665815468
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2847466844
Short name T881
Test name
Test status
Simulation time 61937284 ps
CPU time 0.78 seconds
Started Aug 02 04:24:46 PM PDT 24
Finished Aug 02 04:24:47 PM PDT 24
Peak memory 195796 kb
Host smart-c61e3cf1-5ccc-459f-9657-56b513e5b33e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2847466844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2847466844
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4156163475
Short name T899
Test name
Test status
Simulation time 51549145 ps
CPU time 0.99 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 196452 kb
Host smart-3ded5544-f1e9-4020-afea-bd6a34dd5523
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156163475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4156163475
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2782984865
Short name T871
Test name
Test status
Simulation time 324632833 ps
CPU time 1.38 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 195700 kb
Host smart-5ad56712-a1fd-4583-98df-d622bea8bec7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2782984865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2782984865
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484606902
Short name T882
Test name
Test status
Simulation time 40763940 ps
CPU time 0.68 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 193868 kb
Host smart-0e7ac801-2fc1-4cf0-b5ac-c4fed060bf13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484606902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1484606902
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.6766605
Short name T864
Test name
Test status
Simulation time 239846204 ps
CPU time 1.11 seconds
Started Aug 02 04:23:58 PM PDT 24
Finished Aug 02 04:24:00 PM PDT 24
Peak memory 196432 kb
Host smart-0d686416-450d-4dca-89d9-2bab77abbd74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=6766605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.6766605
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.72496810
Short name T866
Test name
Test status
Simulation time 57809633 ps
CPU time 1.05 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 195352 kb
Host smart-6305dd5d-d97e-488d-9eeb-374dd6107f36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72496810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.72496810
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4214038381
Short name T883
Test name
Test status
Simulation time 107967756 ps
CPU time 1.18 seconds
Started Aug 02 04:24:01 PM PDT 24
Finished Aug 02 04:24:02 PM PDT 24
Peak memory 196596 kb
Host smart-8ead9c7a-64b4-4ea9-981d-d087c65cb10e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4214038381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4214038381
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.148539988
Short name T926
Test name
Test status
Simulation time 42937111 ps
CPU time 1.31 seconds
Started Aug 02 04:25:02 PM PDT 24
Finished Aug 02 04:25:05 PM PDT 24
Peak memory 194600 kb
Host smart-b142783e-3726-4844-8f7c-b72d6ddf687a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148539988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.148539988
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1825157056
Short name T901
Test name
Test status
Simulation time 69615044 ps
CPU time 1.3 seconds
Started Aug 02 04:24:11 PM PDT 24
Finished Aug 02 04:24:12 PM PDT 24
Peak memory 195544 kb
Host smart-f82b1a38-477f-4d3e-b9ef-f65a32beca2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1825157056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1825157056
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3014236040
Short name T944
Test name
Test status
Simulation time 16256482 ps
CPU time 0.67 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:25:19 PM PDT 24
Peak memory 194056 kb
Host smart-d02c4dd8-26a2-4fdd-9f36-82a92be0f8bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014236040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3014236040
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4130394938
Short name T915
Test name
Test status
Simulation time 42802432 ps
CPU time 1.18 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:25:19 PM PDT 24
Peak memory 196576 kb
Host smart-f6dc1932-5675-4bbd-baf2-41fe28bf2a9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4130394938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4130394938
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.243569847
Short name T943
Test name
Test status
Simulation time 108829086 ps
CPU time 0.7 seconds
Started Aug 02 04:25:17 PM PDT 24
Finished Aug 02 04:25:18 PM PDT 24
Peak memory 194836 kb
Host smart-8dcbd068-fcf9-46bc-8059-159af864a436
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243569847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.243569847
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1171836862
Short name T894
Test name
Test status
Simulation time 513036036 ps
CPU time 1.4 seconds
Started Aug 02 04:24:13 PM PDT 24
Finished Aug 02 04:24:15 PM PDT 24
Peak memory 196612 kb
Host smart-3244690d-c20c-4478-a8b5-a278aab14a8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1171836862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1171836862
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2266246879
Short name T879
Test name
Test status
Simulation time 168530811 ps
CPU time 0.96 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:27 PM PDT 24
Peak memory 196336 kb
Host smart-3f0e6e5c-d8f4-493b-855b-86cfe3279558
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266246879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2266246879
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1353864345
Short name T924
Test name
Test status
Simulation time 42126142 ps
CPU time 0.9 seconds
Started Aug 02 04:24:24 PM PDT 24
Finished Aug 02 04:24:25 PM PDT 24
Peak memory 194432 kb
Host smart-f280a97f-8aa9-4dd6-b0a7-847f2b2a872a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1353864345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1353864345
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2957811612
Short name T913
Test name
Test status
Simulation time 91815628 ps
CPU time 1.34 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196752 kb
Host smart-3ac633d7-bf0c-4057-9848-8df2d9fe0e45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957811612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2957811612
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1625357812
Short name T920
Test name
Test status
Simulation time 143209032 ps
CPU time 1.13 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196400 kb
Host smart-eddafa3b-6045-45e0-963e-4fe343716893
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1625357812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1625357812
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3801189804
Short name T930
Test name
Test status
Simulation time 106923210 ps
CPU time 1.13 seconds
Started Aug 02 04:23:22 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 196524 kb
Host smart-22106124-6c90-49fa-baef-c1e60db9adf9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801189804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3801189804
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3285050902
Short name T940
Test name
Test status
Simulation time 295089828 ps
CPU time 1.36 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:27 PM PDT 24
Peak memory 198072 kb
Host smart-04c5e91f-009c-429d-a082-8e56e8dbd2e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3285050902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3285050902
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3532746983
Short name T892
Test name
Test status
Simulation time 62740759 ps
CPU time 1.27 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196460 kb
Host smart-046fc4ae-911e-4136-bddb-4d47b65bbd3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532746983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3532746983
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.316680903
Short name T857
Test name
Test status
Simulation time 70156593 ps
CPU time 1.16 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196668 kb
Host smart-b0c4f5e3-0cba-40b9-a051-a2947ca7f321
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=316680903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.316680903
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.830982528
Short name T877
Test name
Test status
Simulation time 53455496 ps
CPU time 0.92 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196248 kb
Host smart-d759267a-7a61-4cb8-b46f-7de2f981db29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830982528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.830982528
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3857408007
Short name T907
Test name
Test status
Simulation time 699173631 ps
CPU time 1.07 seconds
Started Aug 02 04:23:23 PM PDT 24
Finished Aug 02 04:23:24 PM PDT 24
Peak memory 196504 kb
Host smart-82a21af7-9f14-4567-b85b-54da0af0080d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3857408007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3857408007
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.497018757
Short name T862
Test name
Test status
Simulation time 85288062 ps
CPU time 1.28 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196544 kb
Host smart-9a3efc8d-6327-4369-95f5-aec9c4a03956
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497018757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.497018757
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3628619294
Short name T939
Test name
Test status
Simulation time 48647904 ps
CPU time 0.93 seconds
Started Aug 02 04:23:24 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196696 kb
Host smart-500f87c2-3733-4c3e-894e-1c4c6a28409e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3628619294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3628619294
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2516671490
Short name T921
Test name
Test status
Simulation time 107504819 ps
CPU time 0.84 seconds
Started Aug 02 04:24:55 PM PDT 24
Finished Aug 02 04:24:56 PM PDT 24
Peak memory 196224 kb
Host smart-8615b9e7-ad6a-4e90-99ef-3b1ba5c3a319
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516671490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2516671490
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3092920568
Short name T910
Test name
Test status
Simulation time 54552099 ps
CPU time 0.92 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 196380 kb
Host smart-fb2f62ad-e4b3-4730-abad-4f205c868375
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3092920568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3092920568
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2096461963
Short name T914
Test name
Test status
Simulation time 53920496 ps
CPU time 1 seconds
Started Aug 02 04:23:28 PM PDT 24
Finished Aug 02 04:23:29 PM PDT 24
Peak memory 197884 kb
Host smart-c1f58f8d-00e1-4030-add6-18f22a3498ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096461963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2096461963
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4079097281
Short name T853
Test name
Test status
Simulation time 216506067 ps
CPU time 1.02 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 196384 kb
Host smart-aa9c7174-2695-4d0d-a3ca-f888bad593de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4079097281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4079097281
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3730410530
Short name T889
Test name
Test status
Simulation time 159227300 ps
CPU time 1.17 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 197532 kb
Host smart-1bd08586-efd1-4c59-8b7e-e22efc5763f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730410530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3730410530
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2409867211
Short name T873
Test name
Test status
Simulation time 42013119 ps
CPU time 1.09 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 195960 kb
Host smart-fbfed019-18d7-4ef1-a0ea-af52b4c1c6f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2409867211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2409867211
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2992059680
Short name T884
Test name
Test status
Simulation time 133121873 ps
CPU time 1.26 seconds
Started Aug 02 04:23:36 PM PDT 24
Finished Aug 02 04:23:37 PM PDT 24
Peak memory 195548 kb
Host smart-db0747d7-990a-4c20-9e47-8059226aa855
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992059680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2992059680
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4268877827
Short name T912
Test name
Test status
Simulation time 98005769 ps
CPU time 1.42 seconds
Started Aug 02 04:23:27 PM PDT 24
Finished Aug 02 04:23:28 PM PDT 24
Peak memory 196628 kb
Host smart-1a8f61b7-576e-43ed-9b69-9254e866755b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4268877827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4268877827
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.758417759
Short name T903
Test name
Test status
Simulation time 64900036 ps
CPU time 0.84 seconds
Started Aug 02 04:24:42 PM PDT 24
Finished Aug 02 04:24:43 PM PDT 24
Peak memory 194844 kb
Host smart-7c796077-5cb1-4dbd-9c8e-b2f61958d33c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758417759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.758417759
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.301817561
Short name T902
Test name
Test status
Simulation time 135791845 ps
CPU time 1.25 seconds
Started Aug 02 04:23:37 PM PDT 24
Finished Aug 02 04:23:38 PM PDT 24
Peak memory 195664 kb
Host smart-957300d5-3ec6-4acb-b50e-9003b9aa121c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=301817561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.301817561
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021260113
Short name T938
Test name
Test status
Simulation time 360193719 ps
CPU time 1.34 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 195672 kb
Host smart-3f6d1d5b-d989-4603-906b-c74bcc987586
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021260113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4021260113
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3599518642
Short name T860
Test name
Test status
Simulation time 72302126 ps
CPU time 1.18 seconds
Started Aug 02 04:23:25 PM PDT 24
Finished Aug 02 04:23:26 PM PDT 24
Peak memory 196512 kb
Host smart-1b2b1b4f-38ae-4f73-a027-9231e08de79a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3599518642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3599518642
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1616670306
Short name T923
Test name
Test status
Simulation time 25397439 ps
CPU time 0.83 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 194688 kb
Host smart-46e6182f-cb7a-4d85-8a09-e2868703e7a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616670306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1616670306
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4038014565
Short name T916
Test name
Test status
Simulation time 111299882 ps
CPU time 1.08 seconds
Started Aug 02 04:23:22 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 196488 kb
Host smart-f2098482-4a7c-4a54-91f6-fafcfaaf7290
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4038014565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4038014565
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122380304
Short name T895
Test name
Test status
Simulation time 50788637 ps
CPU time 0.95 seconds
Started Aug 02 04:23:22 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 195492 kb
Host smart-ead4d850-110d-4042-9e0d-1c2a429cfab1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122380304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2122380304
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3287807460
Short name T931
Test name
Test status
Simulation time 168523288 ps
CPU time 0.93 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 195012 kb
Host smart-358a158a-847a-4b13-8b47-79a951a8d4d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3287807460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3287807460
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4105291212
Short name T941
Test name
Test status
Simulation time 58472523 ps
CPU time 0.85 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 196160 kb
Host smart-6d80e24e-8c05-4351-aaff-45200369f9fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105291212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4105291212
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1982885804
Short name T878
Test name
Test status
Simulation time 63885582 ps
CPU time 1.12 seconds
Started Aug 02 04:24:44 PM PDT 24
Finished Aug 02 04:24:46 PM PDT 24
Peak memory 197288 kb
Host smart-8ad63811-d4aa-4984-814f-de9b924dd472
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1982885804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1982885804
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2884068029
Short name T911
Test name
Test status
Simulation time 49970046 ps
CPU time 0.75 seconds
Started Aug 02 04:24:30 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 193788 kb
Host smart-9279b171-c140-47a5-98c6-af7fcc662d75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884068029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2884068029
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1705514634
Short name T849
Test name
Test status
Simulation time 35756612 ps
CPU time 0.74 seconds
Started Aug 02 04:24:25 PM PDT 24
Finished Aug 02 04:24:26 PM PDT 24
Peak memory 194700 kb
Host smart-ee484f67-8da6-44f4-aff9-051a39f9515b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1705514634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1705514634
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2030214736
Short name T874
Test name
Test status
Simulation time 71556534 ps
CPU time 1.33 seconds
Started Aug 02 04:24:29 PM PDT 24
Finished Aug 02 04:24:31 PM PDT 24
Peak memory 195672 kb
Host smart-bf02d964-0049-4ed6-9a4b-c19912a2ddfb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030214736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2030214736
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2744159908
Short name T865
Test name
Test status
Simulation time 70842066 ps
CPU time 0.99 seconds
Started Aug 02 04:24:45 PM PDT 24
Finished Aug 02 04:24:46 PM PDT 24
Peak memory 197796 kb
Host smart-8d3487d8-5fc5-4090-b7e2-b2cb411a8a8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2744159908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2744159908
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3195603081
Short name T851
Test name
Test status
Simulation time 48959493 ps
CPU time 1.08 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:24:28 PM PDT 24
Peak memory 196244 kb
Host smart-a720bc55-c1ec-46ec-9362-514c97930c27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195603081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3195603081
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3197537498
Short name T876
Test name
Test status
Simulation time 72233869 ps
CPU time 0.88 seconds
Started Aug 02 04:24:46 PM PDT 24
Finished Aug 02 04:24:47 PM PDT 24
Peak memory 197176 kb
Host smart-f3d34071-f1e5-4ded-b968-c3eda5f7f7eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197537498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3197537498
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750460846
Short name T905
Test name
Test status
Simulation time 57099107 ps
CPU time 0.99 seconds
Started Aug 02 04:24:26 PM PDT 24
Finished Aug 02 04:24:27 PM PDT 24
Peak memory 195644 kb
Host smart-4b4348fc-1bd9-4e21-8c8d-6a4b4598433c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750460846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2750460846
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2022959728
Short name T925
Test name
Test status
Simulation time 222270279 ps
CPU time 1.04 seconds
Started Aug 02 04:24:45 PM PDT 24
Finished Aug 02 04:24:46 PM PDT 24
Peak memory 196344 kb
Host smart-ea39915d-ce5a-4479-8e36-1100084cf32b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2022959728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2022959728
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.681434774
Short name T929
Test name
Test status
Simulation time 59717463 ps
CPU time 1.04 seconds
Started Aug 02 04:24:28 PM PDT 24
Finished Aug 02 04:24:30 PM PDT 24
Peak memory 195168 kb
Host smart-81cc7c9a-ad59-406c-bb85-74b3e22b8d1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681434774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.681434774
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.662736621
Short name T909
Test name
Test status
Simulation time 230431581 ps
CPU time 0.91 seconds
Started Aug 02 04:24:43 PM PDT 24
Finished Aug 02 04:24:44 PM PDT 24
Peak memory 197624 kb
Host smart-9bbb3666-e10b-4275-8088-67d9eebca2f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=662736621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.662736621
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2836261570
Short name T846
Test name
Test status
Simulation time 142921853 ps
CPU time 1.02 seconds
Started Aug 02 04:23:59 PM PDT 24
Finished Aug 02 04:24:00 PM PDT 24
Peak memory 195660 kb
Host smart-527bde64-6b3f-4bb0-b89b-984568f9f277
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836261570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2836261570
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3373052390
Short name T904
Test name
Test status
Simulation time 120062621 ps
CPU time 0.94 seconds
Started Aug 02 04:23:59 PM PDT 24
Finished Aug 02 04:24:00 PM PDT 24
Peak memory 196088 kb
Host smart-81684bf7-8601-4847-aa2a-f66120aa3fa1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3373052390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3373052390
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2509828224
Short name T936
Test name
Test status
Simulation time 157200988 ps
CPU time 1.13 seconds
Started Aug 02 04:23:58 PM PDT 24
Finished Aug 02 04:23:59 PM PDT 24
Peak memory 196664 kb
Host smart-7dc5c5c9-dc7c-4880-9270-c146b9f5d1b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509828224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2509828224
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3690243596
Short name T886
Test name
Test status
Simulation time 197830099 ps
CPU time 1.1 seconds
Started Aug 02 04:25:18 PM PDT 24
Finished Aug 02 04:25:19 PM PDT 24
Peak memory 196320 kb
Host smart-da56c086-59bf-4c97-b3e5-583fcf8e4b6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3690243596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3690243596
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787248200
Short name T875
Test name
Test status
Simulation time 319198547 ps
CPU time 1.19 seconds
Started Aug 02 04:24:20 PM PDT 24
Finished Aug 02 04:24:21 PM PDT 24
Peak memory 196828 kb
Host smart-3ee9b1f5-b5d9-42df-b444-3fdcc6409a03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787248200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2787248200
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1615447355
Short name T858
Test name
Test status
Simulation time 61556110 ps
CPU time 1.45 seconds
Started Aug 02 04:24:09 PM PDT 24
Finished Aug 02 04:24:11 PM PDT 24
Peak memory 196664 kb
Host smart-d72a7879-0e3e-4832-9f3f-a02c4e8c06e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1615447355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1615447355
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645983819
Short name T859
Test name
Test status
Simulation time 451460681 ps
CPU time 1.31 seconds
Started Aug 02 04:24:08 PM PDT 24
Finished Aug 02 04:24:09 PM PDT 24
Peak memory 196524 kb
Host smart-4bcce975-7247-414b-9960-e914cece7bd0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645983819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2645983819
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2224587862
Short name T872
Test name
Test status
Simulation time 60570668 ps
CPU time 1.22 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 196796 kb
Host smart-442e5e29-02fc-43ea-93c1-45b0f834f7b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2224587862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2224587862
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1295563109
Short name T927
Test name
Test status
Simulation time 133599159 ps
CPU time 1.13 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 195572 kb
Host smart-ec59621f-dd94-4d10-a777-d25d2b1af65d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295563109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1295563109
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1794073787
Short name T918
Test name
Test status
Simulation time 172189763 ps
CPU time 1.37 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 196624 kb
Host smart-b235409c-6cf6-46ee-992b-e6a7656b7025
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1794073787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1794073787
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2405988735
Short name T854
Test name
Test status
Simulation time 116111023 ps
CPU time 1.15 seconds
Started Aug 02 04:23:21 PM PDT 24
Finished Aug 02 04:23:23 PM PDT 24
Peak memory 196716 kb
Host smart-1f6bb9ba-c203-4a9f-a011-602b2c82311f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405988735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2405988735
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1536555694
Short name T908
Test name
Test status
Simulation time 32328239 ps
CPU time 0.76 seconds
Started Aug 02 04:23:15 PM PDT 24
Finished Aug 02 04:23:16 PM PDT 24
Peak memory 195236 kb
Host smart-04ddc12b-a8fa-4eca-8b4f-1b75bc597679
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1536555694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1536555694
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080662905
Short name T942
Test name
Test status
Simulation time 105539873 ps
CPU time 0.8 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:22 PM PDT 24
Peak memory 195216 kb
Host smart-635df485-2d4f-4c54-bd4e-5786329768ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080662905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3080662905
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4171143821
Short name T869
Test name
Test status
Simulation time 173525348 ps
CPU time 0.94 seconds
Started Aug 02 04:23:16 PM PDT 24
Finished Aug 02 04:23:17 PM PDT 24
Peak memory 196472 kb
Host smart-28b23d83-a594-489f-9c3d-51b64ec6e3f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4171143821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.4171143821
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123048161
Short name T867
Test name
Test status
Simulation time 58084884 ps
CPU time 1.12 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 196416 kb
Host smart-4df05fc3-3b0b-449a-b4c4-c2b25b016daf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123048161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2123048161
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3503635553
Short name T852
Test name
Test status
Simulation time 129528148 ps
CPU time 1.13 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 197952 kb
Host smart-55f68cad-9d6f-47b6-82b4-5cb30640e3ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3503635553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3503635553
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.955173215
Short name T933
Test name
Test status
Simulation time 403567720 ps
CPU time 1.2 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 196540 kb
Host smart-e54e5405-6f40-4d4a-b9d3-c8734beb247c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955173215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.955173215
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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