Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4745162	1			T24	1		T25	46653		T26	201
all_pins[1]	4745162	1			T24	1		T25	46653		T26	201
all_pins[2]	4745162	1			T24	1		T25	46653		T26	201
all_pins[3]	4745162	1			T24	1		T25	46653		T26	201
all_pins[4]	4745162	1			T24	1		T25	46653		T26	201
all_pins[5]	4745162	1			T24	1		T25	46653		T26	201
all_pins[6]	4745162	1			T24	1		T25	46653		T26	201
all_pins[7]	4745162	1			T24	1		T25	46653		T26	201
all_pins[8]	4745162	1			T24	1		T25	46653		T26	201
all_pins[9]	4745162	1			T24	1		T25	46653		T26	201
all_pins[10]	4745162	1			T24	1		T25	46653		T26	201
all_pins[11]	4745162	1			T24	1		T25	46653		T26	201
all_pins[12]	4745162	1			T24	1		T25	46653		T26	201
all_pins[13]	4745162	1			T24	1		T25	46653		T26	201
all_pins[14]	4745162	1			T24	1		T25	46653		T26	201
all_pins[15]	4745162	1			T24	1		T25	46653		T26	201
all_pins[16]	4745162	1			T24	1		T25	46653		T26	201
all_pins[17]	4745162	1			T24	1		T25	46653		T26	201
all_pins[18]	4745162	1			T24	1		T25	46653		T26	201
all_pins[19]	4745162	1			T24	1		T25	46653		T26	201
all_pins[20]	4745162	1			T24	1		T25	46653		T26	201
all_pins[21]	4745162	1			T24	1		T25	46653		T26	201
all_pins[22]	4745162	1			T24	1		T25	46653		T26	201
all_pins[23]	4745162	1			T24	1		T25	46653		T26	201
all_pins[24]	4745162	1			T24	1		T25	46653		T26	201
all_pins[25]	4745162	1			T24	1		T25	46653		T26	201
all_pins[26]	4745162	1			T24	1		T25	46653		T26	201
all_pins[27]	4745162	1			T24	1		T25	46653		T26	201
all_pins[28]	4745162	1			T24	1		T25	46653		T26	201
all_pins[29]	4745162	1			T24	1		T25	46653		T26	201
all_pins[30]	4745162	1			T24	1		T25	46653		T26	201
all_pins[31]	4745162	1			T24	1		T25	46653		T26	201

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	94347311	1			T24	32		T25	928159		T26	4084
values[0x1]	57497873	1			T25	564737		T26	2348		T27	552
transitions[0x0=>0x1]	34470964	1			T25	338659		T26	1406		T27	292
transitions[0x1=>0x0]	34470797	1			T25	338659		T26	1405		T27	291

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2944315	1			T24	1		T25	29283		T26	109
all_pins[0]	values[0x1]	1800847	1			T25	17370		T26	92		T27	19
all_pins[0]	transitions[0x0=>0x1]	1115427	1			T25	10767		T26	48		T27	12
all_pins[0]	transitions[0x1=>0x0]	1108324	1			T25	11109		T26	39		T27	11
all_pins[1]	values[0x0]	2946838	1			T24	1		T25	29031		T26	122
all_pins[1]	values[0x1]	1798324	1			T25	17622		T26	79		T27	12
all_pins[1]	transitions[0x0=>0x1]	1075094	1			T25	10517		T26	31		T27	4
all_pins[1]	transitions[0x1=>0x0]	1077617	1			T25	10265		T26	44		T27	11
all_pins[2]	values[0x0]	2944745	1			T24	1		T25	29145		T26	123
all_pins[2]	values[0x1]	1800417	1			T25	17508		T26	78		T27	21
all_pins[2]	transitions[0x0=>0x1]	1078399	1			T25	10377		T26	44		T27	14
all_pins[2]	transitions[0x1=>0x0]	1076306	1			T25	10491		T26	45		T27	5
all_pins[3]	values[0x0]	2943036	1			T24	1		T25	29328		T26	151
all_pins[3]	values[0x1]	1802126	1			T25	17325		T26	50		T27	21
all_pins[3]	transitions[0x0=>0x1]	1080808	1			T25	10445		T26	32		T27	8
all_pins[3]	transitions[0x1=>0x0]	1079099	1			T25	10628		T26	60		T27	8
all_pins[4]	values[0x0]	2949358	1			T24	1		T25	28725		T26	144
all_pins[4]	values[0x1]	1795804	1			T25	17928		T26	57		T27	21
all_pins[4]	transitions[0x0=>0x1]	1075138	1			T25	11034		T26	37		T27	9
all_pins[4]	transitions[0x1=>0x0]	1081460	1			T25	10431		T26	30		T27	9
all_pins[5]	values[0x0]	2948649	1			T24	1		T25	28741		T26	130
all_pins[5]	values[0x1]	1796513	1			T25	17912		T26	71		T27	12
all_pins[5]	transitions[0x0=>0x1]	1075047	1			T25	10439		T26	34		T27	5
all_pins[5]	transitions[0x1=>0x0]	1074338	1			T25	10455		T26	20		T27	14
all_pins[6]	values[0x0]	2948430	1			T24	1		T25	28608		T26	122
all_pins[6]	values[0x1]	1796732	1			T25	18045		T26	79		T27	18
all_pins[6]	transitions[0x0=>0x1]	1074841	1			T25	10891		T26	58		T27	12
all_pins[6]	transitions[0x1=>0x0]	1074622	1			T25	10758		T26	50		T27	6
all_pins[7]	values[0x0]	2947109	1			T24	1		T25	29011		T26	152
all_pins[7]	values[0x1]	1798053	1			T25	17642		T26	49		T27	13
all_pins[7]	transitions[0x0=>0x1]	1075508	1			T25	10429		T26	32		T27	7
all_pins[7]	transitions[0x1=>0x0]	1074187	1			T25	10832		T26	62		T27	12
all_pins[8]	values[0x0]	2949785	1			T24	1		T25	28671		T26	132
all_pins[8]	values[0x1]	1795377	1			T25	17982		T26	69		T27	17
all_pins[8]	transitions[0x0=>0x1]	1075917	1			T25	10659		T26	50		T27	10
all_pins[8]	transitions[0x1=>0x0]	1078593	1			T25	10319		T26	30		T27	6
all_pins[9]	values[0x0]	2950717	1			T24	1		T25	29200		T26	148
all_pins[9]	values[0x1]	1794445	1			T25	17453		T26	53		T27	15
all_pins[9]	transitions[0x0=>0x1]	1075200	1			T25	10415		T26	38		T27	9
all_pins[9]	transitions[0x1=>0x0]	1076132	1			T25	10944		T26	54		T27	11
all_pins[10]	values[0x0]	2949325	1			T24	1		T25	28747		T26	106
all_pins[10]	values[0x1]	1795837	1			T25	17906		T26	95		T27	22
all_pins[10]	transitions[0x0=>0x1]	1078346	1			T25	10788		T26	69		T27	11
all_pins[10]	transitions[0x1=>0x0]	1076954	1			T25	10335		T26	27		T27	4
all_pins[11]	values[0x0]	2950164	1			T24	1		T25	28853		T26	113
all_pins[11]	values[0x1]	1794998	1			T25	17800		T26	88		T27	14
all_pins[11]	transitions[0x0=>0x1]	1075210	1			T25	10598		T26	43		T27	5
all_pins[11]	transitions[0x1=>0x0]	1076049	1			T25	10704		T26	50		T27	13
all_pins[12]	values[0x0]	2947156	1			T24	1		T25	28119		T26	106
all_pins[12]	values[0x1]	1798006	1			T25	18534		T26	95		T27	19
all_pins[12]	transitions[0x0=>0x1]	1077657	1			T25	11115		T26	44		T27	12
all_pins[12]	transitions[0x1=>0x0]	1074649	1			T25	10381		T26	37		T27	7
all_pins[13]	values[0x0]	2937801	1			T24	1		T25	29048		T26	154
all_pins[13]	values[0x1]	1807361	1			T25	17605		T26	47		T27	19
all_pins[13]	transitions[0x0=>0x1]	1083362	1			T25	10199		T26	15		T27	6
all_pins[13]	transitions[0x1=>0x0]	1074007	1			T25	11128		T26	63		T27	6
all_pins[14]	values[0x0]	2947637	1			T24	1		T25	28758		T26	104
all_pins[14]	values[0x1]	1797525	1			T25	17895		T26	97		T27	17
all_pins[14]	transitions[0x0=>0x1]	1071977	1			T25	10781		T26	76		T27	9
all_pins[14]	transitions[0x1=>0x0]	1081813	1			T25	10491		T26	26		T27	11
all_pins[15]	values[0x0]	2948999	1			T24	1		T25	29789		T26	132
all_pins[15]	values[0x1]	1796163	1			T25	16864		T26	69		T27	18
all_pins[15]	transitions[0x0=>0x1]	1073459	1			T25	10029		T26	32		T27	10
all_pins[15]	transitions[0x1=>0x0]	1074821	1			T25	11060		T26	60		T27	9
all_pins[16]	values[0x0]	2949399	1			T24	1		T25	29098		T26	119
all_pins[16]	values[0x1]	1795763	1			T25	17555		T26	82		T27	19
all_pins[16]	transitions[0x0=>0x1]	1076096	1			T25	10925		T26	61		T27	9
all_pins[16]	transitions[0x1=>0x0]	1076496	1			T25	10234		T26	48		T27	8
all_pins[17]	values[0x0]	2951921	1			T24	1		T25	29040		T26	130
all_pins[17]	values[0x1]	1793241	1			T25	17613		T26	71		T27	22
all_pins[17]	transitions[0x0=>0x1]	1075356	1			T25	10594		T26	38		T27	12
all_pins[17]	transitions[0x1=>0x0]	1077878	1			T25	10536		T26	49		T27	9
all_pins[18]	values[0x0]	2950039	1			T24	1		T25	29676		T26	144
all_pins[18]	values[0x1]	1795123	1			T25	16977		T26	57		T27	14
all_pins[18]	transitions[0x0=>0x1]	1078556	1			T25	10153		T26	27		T27	4
all_pins[18]	transitions[0x1=>0x0]	1076674	1			T25	10789		T26	41		T27	12
all_pins[19]	values[0x0]	2948062	1			T24	1		T25	29410		T26	110
all_pins[19]	values[0x1]	1797100	1			T25	17243		T26	91		T27	16
all_pins[19]	transitions[0x0=>0x1]	1076265	1			T25	10771		T26	61		T27	9
all_pins[19]	transitions[0x1=>0x0]	1074288	1			T25	10505		T26	27		T27	7
all_pins[20]	values[0x0]	2946941	1			T24	1		T25	29352		T26	108
all_pins[20]	values[0x1]	1798221	1			T25	17301		T26	93		T27	19
all_pins[20]	transitions[0x0=>0x1]	1076378	1			T25	10589		T26	41		T27	12
all_pins[20]	transitions[0x1=>0x0]	1075257	1			T25	10531		T26	39		T27	9
all_pins[21]	values[0x0]	2952015	1			T24	1		T25	29107		T26	137
all_pins[21]	values[0x1]	1793147	1			T25	17546		T26	64		T27	18
all_pins[21]	transitions[0x0=>0x1]	1074402	1			T25	10926		T26	32		T27	9
all_pins[21]	transitions[0x1=>0x0]	1079476	1			T25	10681		T26	61		T27	10
all_pins[22]	values[0x0]	2948233	1			T24	1		T25	28964		T26	119
all_pins[22]	values[0x1]	1796929	1			T25	17689		T26	82		T27	13
all_pins[22]	transitions[0x0=>0x1]	1076459	1			T25	10650		T26	45		T27	6
all_pins[22]	transitions[0x1=>0x0]	1072677	1			T25	10507		T26	27		T27	11
all_pins[23]	values[0x0]	2952561	1			T24	1		T25	29029		T26	128
all_pins[23]	values[0x1]	1792601	1			T25	17624		T26	73		T27	22
all_pins[23]	transitions[0x0=>0x1]	1072613	1			T25	10410		T26	55		T27	13
all_pins[23]	transitions[0x1=>0x0]	1076941	1			T25	10475		T26	64		T27	4
all_pins[24]	values[0x0]	2944906	1			T24	1		T25	29424		T26	129
all_pins[24]	values[0x1]	1800256	1			T25	17229		T26	72		T27	16
all_pins[24]	transitions[0x0=>0x1]	1080443	1			T25	10254		T26	37		T27	7
all_pins[24]	transitions[0x1=>0x0]	1072788	1			T25	10649		T26	38		T27	13
all_pins[25]	values[0x0]	2948535	1			T24	1		T25	29347		T26	130
all_pins[25]	values[0x1]	1796627	1			T25	17306		T26	71		T27	18
all_pins[25]	transitions[0x0=>0x1]	1072795	1			T25	10491		T26	34		T27	10
all_pins[25]	transitions[0x1=>0x0]	1076424	1			T25	10414		T26	35		T27	8
all_pins[26]	values[0x0]	2949607	1			T24	1		T25	29076		T26	132
all_pins[26]	values[0x1]	1795555	1			T25	17577		T26	69		T27	9
all_pins[26]	transitions[0x0=>0x1]	1076108	1			T25	10503		T26	40		T27	6
all_pins[26]	transitions[0x1=>0x0]	1077180	1			T25	10232		T26	42		T27	15
all_pins[27]	values[0x0]	2947435	1			T24	1		T25	28863		T26	117
all_pins[27]	values[0x1]	1797727	1			T25	17790		T26	84		T27	17
all_pins[27]	transitions[0x0=>0x1]	1076436	1			T25	10633		T26	47		T27	14
all_pins[27]	transitions[0x1=>0x0]	1074264	1			T25	10420		T26	32		T27	6
all_pins[28]	values[0x0]	2952157	1			T24	1		T25	28530		T26	147
all_pins[28]	values[0x1]	1793005	1			T25	18123		T26	54		T27	18
all_pins[28]	transitions[0x0=>0x1]	1072205	1			T25	10636		T26	39		T27	7
all_pins[28]	transitions[0x1=>0x0]	1076927	1			T25	10303		T26	69		T27	6
all_pins[29]	values[0x0]	2947581	1			T24	1		T25	28349		T26	122
all_pins[29]	values[0x1]	1797581	1			T25	18304		T26	79		T27	16
all_pins[29]	transitions[0x0=>0x1]	1076625	1			T25	10747		T26	60		T27	10
all_pins[29]	transitions[0x1=>0x0]	1072049	1			T25	10566		T26	35		T27	12
all_pins[30]	values[0x0]	2952604	1			T24	1		T25	28896		T26	147
all_pins[30]	values[0x1]	1792558	1			T25	17757		T26	54		T27	18
all_pins[30]	transitions[0x0=>0x1]	1072742	1			T25	10370		T26	33		T27	11
all_pins[30]	transitions[0x1=>0x0]	1077765	1			T25	10917		T26	58		T27	9
all_pins[31]	values[0x0]	2951251	1			T24	1		T25	28941		T26	117
all_pins[31]	values[0x1]	1793911	1			T25	17712		T26	84		T27	19
all_pins[31]	transitions[0x0=>0x1]	1076095	1			T25	10524		T26	73		T27	10
all_pins[31]	transitions[0x1=>0x0]	1074742	1			T25	10569		T26	43		T27	9