Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15542243	1			T24	257		T25	137982		T26	301
all_values[1]	15542243	1			T24	257		T25	137982		T26	301
all_values[2]	15542243	1			T24	257		T25	137982		T26	301
all_values[3]	15542243	1			T24	257		T25	137982		T26	301
all_values[4]	15542243	1			T24	257		T25	137982		T26	301
all_values[5]	15542243	1			T24	257		T25	137982		T26	301
all_values[6]	15542243	1			T24	257		T25	137982		T26	301
all_values[7]	15542243	1			T24	257		T25	137982		T26	301
all_values[8]	15542243	1			T24	257		T25	137982		T26	301
all_values[9]	15542243	1			T24	257		T25	137982		T26	301
all_values[10]	15542243	1			T24	257		T25	137982		T26	301
all_values[11]	15542243	1			T24	257		T25	137982		T26	301
all_values[12]	15542243	1			T24	257		T25	137982		T26	301
all_values[13]	15542243	1			T24	257		T25	137982		T26	301
all_values[14]	15542243	1			T24	257		T25	137982		T26	301
all_values[15]	15542243	1			T24	257		T25	137982		T26	301
all_values[16]	15542243	1			T24	257		T25	137982		T26	301
all_values[17]	15542243	1			T24	257		T25	137982		T26	301
all_values[18]	15542243	1			T24	257		T25	137982		T26	301
all_values[19]	15542243	1			T24	257		T25	137982		T26	301
all_values[20]	15542243	1			T24	257		T25	137982		T26	301
all_values[21]	15542243	1			T24	257		T25	137982		T26	301
all_values[22]	15542243	1			T24	257		T25	137982		T26	301
all_values[23]	15542243	1			T24	257		T25	137982		T26	301
all_values[24]	15542243	1			T24	257		T25	137982		T26	301
all_values[25]	15542243	1			T24	257		T25	137982		T26	301
all_values[26]	15542243	1			T24	257		T25	137982		T26	301
all_values[27]	15542243	1			T24	257		T25	137982		T26	301
all_values[28]	15542243	1			T24	257		T25	137982		T26	301
all_values[29]	15542243	1			T24	257		T25	137982		T26	301
all_values[30]	15542243	1			T24	257		T25	137982		T26	301
all_values[31]	15542243	1			T24	257		T25	137982		T26	301

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282920145

1

T24

8224

T25

222573

T26

4761

auto[1]

214431631

1

T25

218969

T26

4871

T31

1150

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109687263

1

T24

8224

T25

440662

T26

1811

auto[1]

387664513

1

T25

397476

T26

7821

T31

2091

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

491732476

1

T24

8224

T25

435519

T26

9632

auto[1]

5619300

1

T25

60231

T21

42

T1

15234

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2783620	1			T24	257		T25	7177		T26	24
all_values[0]	auto[0]	auto[0]	auto[1]	5960178	1			T25	62981		T26	74		T31	16
all_values[0]	auto[0]	auto[1]	auto[0]	648477	1			T25	6733		T26	39		T31	4
all_values[0]	auto[0]	auto[1]	auto[1]	5974380	1			T25	59228		T26	164		T31	51
all_values[0]	auto[1]	auto[0]	auto[1]	88058	1			T25	958		T21	1		T1	249
all_values[0]	auto[1]	auto[1]	auto[1]	87530	1			T25	905		T1	242		T12	3
all_values[1]	auto[0]	auto[0]	auto[0]	2770579	1			T24	257		T25	7221		T26	23
all_values[1]	auto[0]	auto[0]	auto[1]	5961189	1			T25	60187		T26	124		T31	51
all_values[1]	auto[0]	auto[1]	auto[0]	658732	1			T25	6432		T26	28		T21	8
all_values[1]	auto[0]	auto[1]	auto[1]	5976167	1			T25	62213		T26	126		T31	20
all_values[1]	auto[1]	auto[0]	auto[1]	88156	1			T25	989		T21	1		T1	228
all_values[1]	auto[1]	auto[1]	auto[1]	87420	1			T25	940		T21	1		T1	250
all_values[2]	auto[0]	auto[0]	auto[0]	2781240	1			T24	257		T25	7419		T26	8
all_values[2]	auto[0]	auto[0]	auto[1]	5976442	1			T25	59747		T26	136		T31	54
all_values[2]	auto[0]	auto[1]	auto[0]	648258	1			T25	6026		T26	26		T21	3
all_values[2]	auto[0]	auto[1]	auto[1]	5960376	1			T25	62970		T26	131		T31	17
all_values[2]	auto[1]	auto[0]	auto[1]	87663	1			T25	924		T1	224		T12	3
all_values[2]	auto[1]	auto[1]	auto[1]	88264	1			T25	896		T21	1		T1	219
all_values[3]	auto[0]	auto[0]	auto[0]	2773734	1			T24	257		T25	7007		T26	37
all_values[3]	auto[0]	auto[0]	auto[1]	5979368	1			T25	61923		T26	156		T31	42
all_values[3]	auto[0]	auto[1]	auto[0]	650834	1			T25	5904		T26	23		T21	2
all_values[3]	auto[0]	auto[1]	auto[1]	5963050	1			T25	61296		T26	85		T31	30
all_values[3]	auto[1]	auto[0]	auto[1]	87501	1			T25	945		T21	2		T1	240
all_values[3]	auto[1]	auto[1]	auto[1]	87756	1			T25	907		T21	1		T1	231
all_values[4]	auto[0]	auto[0]	auto[0]	2776688	1			T24	257		T25	6985		T26	23
all_values[4]	auto[0]	auto[0]	auto[1]	5968989	1			T25	59651		T26	130		T31	42
all_values[4]	auto[0]	auto[1]	auto[0]	650348	1			T25	6558		T26	48		T31	6
all_values[4]	auto[0]	auto[1]	auto[1]	5970287	1			T25	62899		T26	100		T31	18
all_values[4]	auto[1]	auto[0]	auto[1]	88727	1			T25	905		T1	209		T12	5
all_values[4]	auto[1]	auto[1]	auto[1]	87204	1			T25	984		T1	268		T12	2
all_values[5]	auto[0]	auto[0]	auto[0]	2768690	1			T24	257		T25	7809		T26	55
all_values[5]	auto[0]	auto[0]	auto[1]	6007619	1			T25	60839		T26	92		T31	1
all_values[5]	auto[0]	auto[1]	auto[0]	653636	1			T25	6518		T26	28		T31	1
all_values[5]	auto[0]	auto[1]	auto[1]	5936723	1			T25	60929		T26	126		T31	70
all_values[5]	auto[1]	auto[0]	auto[1]	88017	1			T25	921		T1	213		T12	2
all_values[5]	auto[1]	auto[1]	auto[1]	87558	1			T25	966		T1	256		T12	3
all_values[6]	auto[0]	auto[0]	auto[0]	2773087	1			T24	257		T25	7153		T26	43
all_values[6]	auto[0]	auto[0]	auto[1]	5962308	1			T25	59248		T26	100		T31	49
all_values[6]	auto[0]	auto[1]	auto[0]	650369	1			T25	6479		T26	30		T1	1108
all_values[6]	auto[0]	auto[1]	auto[1]	5980829	1			T25	63247		T26	128		T31	12
all_values[6]	auto[1]	auto[0]	auto[1]	87951	1			T25	920		T21	3		T1	242
all_values[6]	auto[1]	auto[1]	auto[1]	87699	1			T25	935		T1	237		T12	3
all_values[7]	auto[0]	auto[0]	auto[0]	2778921	1			T24	257		T25	7362		T26	19
all_values[7]	auto[0]	auto[0]	auto[1]	5963787	1			T25	59114		T26	167		T31	50
all_values[7]	auto[0]	auto[1]	auto[0]	651194	1			T25	5999		T26	29		T31	3
all_values[7]	auto[0]	auto[1]	auto[1]	5972344	1			T25	63579		T26	86		T31	15
all_values[7]	auto[1]	auto[0]	auto[1]	87799	1			T25	1022		T21	1		T1	226
all_values[7]	auto[1]	auto[1]	auto[1]	88198	1			T25	906		T1	269		T12	1
all_values[8]	auto[0]	auto[0]	auto[0]	2774339	1			T24	257		T25	6603		T26	47
all_values[8]	auto[0]	auto[0]	auto[1]	5985872	1			T25	63255		T26	102		T31	28
all_values[8]	auto[0]	auto[1]	auto[0]	658465	1			T25	6343		T26	32		T31	6
all_values[8]	auto[0]	auto[1]	auto[1]	5947808	1			T25	59892		T26	120		T31	37
all_values[8]	auto[1]	auto[0]	auto[1]	87836	1			T25	952		T21	1		T1	216
all_values[8]	auto[1]	auto[1]	auto[1]	87923	1			T25	937		T1	244		T12	3
all_values[9]	auto[0]	auto[0]	auto[0]	2783578	1			T24	257		T25	7104		T26	68
all_values[9]	auto[0]	auto[0]	auto[1]	5983361	1			T25	60507		T26	90		T31	22
all_values[9]	auto[0]	auto[1]	auto[0]	651844	1			T25	7532		T26	48		T31	5
all_values[9]	auto[0]	auto[1]	auto[1]	5948373	1			T25	60929		T26	95		T31	41
all_values[9]	auto[1]	auto[0]	auto[1]	87977	1			T25	915		T21	2		T1	244
all_values[9]	auto[1]	auto[1]	auto[1]	87110	1			T25	995		T21	1		T1	219
all_values[10]	auto[0]	auto[0]	auto[0]	2780297	1			T24	257		T25	7488		T26	18
all_values[10]	auto[0]	auto[0]	auto[1]	5988346	1			T25	61203		T26	89		T31	43
all_values[10]	auto[0]	auto[1]	auto[0]	641465	1			T25	6460		T26	27		T21	9
all_values[10]	auto[0]	auto[1]	auto[1]	5956757	1			T25	60948		T26	167		T31	28
all_values[10]	auto[1]	auto[0]	auto[1]	87490	1			T25	917		T21	1		T1	248
all_values[10]	auto[1]	auto[1]	auto[1]	87888	1			T25	966		T1	248		T12	3
all_values[11]	auto[0]	auto[0]	auto[0]	2769008	1			T24	257		T25	6877		T26	32
all_values[11]	auto[0]	auto[0]	auto[1]	5990909	1			T25	60704		T26	83		T31	33
all_values[11]	auto[0]	auto[1]	auto[0]	645791	1			T25	6195		T26	22		T31	7
all_values[11]	auto[0]	auto[1]	auto[1]	5960975	1			T25	62287		T26	164		T31	23
all_values[11]	auto[1]	auto[0]	auto[1]	88185	1			T25	933		T21	1		T1	243
all_values[11]	auto[1]	auto[1]	auto[1]	87375	1			T25	986		T1	218		T12	4
all_values[12]	auto[0]	auto[0]	auto[0]	2784657	1			T24	257		T25	7073		T26	31
all_values[12]	auto[0]	auto[0]	auto[1]	5957115	1			T25	58946		T26	85		T31	27
all_values[12]	auto[0]	auto[1]	auto[0]	650027	1			T25	7042		T26	21		T1	1432
all_values[12]	auto[0]	auto[1]	auto[1]	5974442	1			T25	63003		T26	164		T31	45
all_values[12]	auto[1]	auto[0]	auto[1]	88680	1			T25	974		T1	236		T12	6
all_values[12]	auto[1]	auto[1]	auto[1]	87322	1			T25	944		T1	227		T12	3
all_values[13]	auto[0]	auto[0]	auto[0]	2771150	1			T24	257		T25	7297		T26	26
all_values[13]	auto[0]	auto[0]	auto[1]	5961881	1			T25	64449		T26	178		T31	47
all_values[13]	auto[0]	auto[1]	auto[0]	644886	1			T25	5866		T26	10		T21	1
all_values[13]	auto[0]	auto[1]	auto[1]	5988919	1			T25	58470		T26	87		T31	22
all_values[13]	auto[1]	auto[0]	auto[1]	87612	1			T25	957		T21	1		T1	246
all_values[13]	auto[1]	auto[1]	auto[1]	87795	1			T25	943		T21	1		T1	236
all_values[14]	auto[0]	auto[0]	auto[0]	2771607	1			T24	257		T25	7030		T26	22
all_values[14]	auto[0]	auto[0]	auto[1]	5995812	1			T25	61149		T26	107		T31	48
all_values[14]	auto[0]	auto[1]	auto[0]	649063	1			T25	6506		T26	13		T1	1522
all_values[14]	auto[0]	auto[1]	auto[1]	5950234	1			T25	61487		T26	159		T31	17
all_values[14]	auto[1]	auto[0]	auto[1]	88388	1			T25	839		T21	1		T1	236
all_values[14]	auto[1]	auto[1]	auto[1]	87139	1			T25	971		T1	231		T12	3
all_values[15]	auto[0]	auto[0]	auto[0]	2776728	1			T24	257		T25	7267		T26	40
all_values[15]	auto[0]	auto[0]	auto[1]	5980427	1			T25	65012		T26	107		T31	11
all_values[15]	auto[0]	auto[1]	auto[0]	648988	1			T25	6004		T26	26		T31	3
all_values[15]	auto[0]	auto[1]	auto[1]	5960494	1			T25	57812		T26	128		T31	58
all_values[15]	auto[1]	auto[0]	auto[1]	87850	1			T25	962		T21	1		T1	267
all_values[15]	auto[1]	auto[1]	auto[1]	87756	1			T25	925		T1	236		T12	4
all_values[16]	auto[0]	auto[0]	auto[0]	2784009	1			T24	257		T25	7319		T26	10
all_values[16]	auto[0]	auto[0]	auto[1]	5978586	1			T25	61262		T26	131		T31	44
all_values[16]	auto[0]	auto[1]	auto[0]	649335	1			T25	7596		T26	26		T1	1507
all_values[16]	auto[0]	auto[1]	auto[1]	5954629	1			T25	59942		T26	134		T31	28
all_values[16]	auto[1]	auto[0]	auto[1]	87725	1			T25	958		T21	3		T1	275
all_values[16]	auto[1]	auto[1]	auto[1]	87959	1			T25	905		T1	215		T12	2
all_values[17]	auto[0]	auto[0]	auto[0]	2767440	1			T24	257		T25	7119		T26	36
all_values[17]	auto[0]	auto[0]	auto[1]	5991386	1			T25	63011		T26	117		T31	10
all_values[17]	auto[0]	auto[1]	auto[0]	659817	1			T25	6218		T26	31		T31	3
all_values[17]	auto[0]	auto[1]	auto[1]	5947631	1			T25	59836		T26	117		T31	58
all_values[17]	auto[1]	auto[0]	auto[1]	87803	1			T25	934		T1	276		T12	4
all_values[17]	auto[1]	auto[1]	auto[1]	88166	1			T25	864		T1	222		T12	3
all_values[18]	auto[0]	auto[0]	auto[0]	2774932	1			T24	257		T25	7113		T26	31
all_values[18]	auto[0]	auto[0]	auto[1]	5978665	1			T25	62419		T26	125		T31	43
all_values[18]	auto[0]	auto[1]	auto[0]	647738	1			T25	6126		T26	46		T31	2
all_values[18]	auto[0]	auto[1]	auto[1]	5965814	1			T25	60399		T26	99		T31	27
all_values[18]	auto[1]	auto[0]	auto[1]	87443	1			T25	1007		T21	2		T1	251
all_values[18]	auto[1]	auto[1]	auto[1]	87651	1			T25	918		T1	221		T12	2
all_values[19]	auto[0]	auto[0]	auto[0]	2769657	1			T24	257		T25	7945		T26	39
all_values[19]	auto[0]	auto[0]	auto[1]	6013749	1			T25	61369		T26	100		T31	45
all_values[19]	auto[0]	auto[1]	auto[0]	653011	1			T25	7679		T26	14		T31	2
all_values[19]	auto[0]	auto[1]	auto[1]	5930512	1			T25	59111		T26	148		T31	22
all_values[19]	auto[1]	auto[0]	auto[1]	88638	1			T25	964		T21	1		T1	233
all_values[19]	auto[1]	auto[1]	auto[1]	86676	1			T25	914		T1	242		T12	2
all_values[20]	auto[0]	auto[0]	auto[0]	2778303	1			T24	257		T25	8515		T26	21
all_values[20]	auto[0]	auto[0]	auto[1]	5944876	1			T25	62341		T26	99		T31	9
all_values[20]	auto[0]	auto[1]	auto[0]	646426	1			T25	7117		T26	20		T1	1530
all_values[20]	auto[0]	auto[1]	auto[1]	5997071	1			T25	58118		T26	161		T31	61
all_values[20]	auto[1]	auto[0]	auto[1]	88023	1			T25	993		T21	2		T1	245
all_values[20]	auto[1]	auto[1]	auto[1]	87544	1			T25	898		T1	239		T12	5
all_values[21]	auto[0]	auto[0]	auto[0]	2772097	1			T24	257		T25	7240		T26	34
all_values[21]	auto[0]	auto[0]	auto[1]	5984079	1			T25	59581		T26	144		T31	19
all_values[21]	auto[0]	auto[1]	auto[0]	651848	1			T25	6022		T26	12		T31	4
all_values[21]	auto[0]	auto[1]	auto[1]	5958782	1			T25	63240		T26	111		T31	48
all_values[21]	auto[1]	auto[0]	auto[1]	87935	1			T25	927		T1	248		T12	3
all_values[21]	auto[1]	auto[1]	auto[1]	87502	1			T25	972		T1	231		T12	4
all_values[22]	auto[0]	auto[0]	auto[0]	2781754	1			T24	257		T25	6962		T26	2
all_values[22]	auto[0]	auto[0]	auto[1]	5968848	1			T25	60058		T26	114		T31	58
all_values[22]	auto[0]	auto[1]	auto[0]	656617	1			T25	6675		T26	47		T1	1488
all_values[22]	auto[0]	auto[1]	auto[1]	5959398	1			T25	62392		T26	138		T31	10
all_values[22]	auto[1]	auto[0]	auto[1]	87662	1			T25	917		T21	1		T1	229
all_values[22]	auto[1]	auto[1]	auto[1]	87964	1			T25	978		T1	270		T12	1
all_values[23]	auto[0]	auto[0]	auto[0]	2777133	1			T24	257		T25	7792		T26	38
all_values[23]	auto[0]	auto[0]	auto[1]	5944806	1			T25	62852		T26	104		T31	39
all_values[23]	auto[0]	auto[1]	auto[0]	649800	1			T25	5938		T26	28		T31	6
all_values[23]	auto[0]	auto[1]	auto[1]	5995025	1			T25	59561		T26	131		T31	21
all_values[23]	auto[1]	auto[0]	auto[1]	87604	1			T25	942		T21	1		T1	235
all_values[23]	auto[1]	auto[1]	auto[1]	87875	1			T25	897		T1	224		T12	1
all_values[24]	auto[0]	auto[0]	auto[0]	2783420	1			T24	257		T25	7820		T26	13
all_values[24]	auto[0]	auto[0]	auto[1]	5968930	1			T25	64092		T26	137		T31	15
all_values[24]	auto[0]	auto[1]	auto[0]	648495	1			T25	6070		T26	34		T31	16
all_values[24]	auto[0]	auto[1]	auto[1]	5965938	1			T25	58128		T26	117		T31	40
all_values[24]	auto[1]	auto[0]	auto[1]	87996	1			T25	947		T21	1		T1	253
all_values[24]	auto[1]	auto[1]	auto[1]	87464	1			T25	925		T1	216		T12	3
all_values[25]	auto[0]	auto[0]	auto[0]	2780693	1			T24	257		T25	7132		T26	38
all_values[25]	auto[0]	auto[0]	auto[1]	5987734	1			T25	65025		T26	116		T31	15
all_values[25]	auto[0]	auto[1]	auto[0]	657551	1			T25	6294		T26	33		T31	7
all_values[25]	auto[0]	auto[1]	auto[1]	5940459	1			T25	57608		T26	114		T31	50
all_values[25]	auto[1]	auto[0]	auto[1]	88269	1			T25	951		T21	1		T1	222
all_values[25]	auto[1]	auto[1]	auto[1]	87537	1			T25	972		T21	1		T1	235
all_values[26]	auto[0]	auto[0]	auto[0]	2784565	1			T24	257		T25	7273		T26	37
all_values[26]	auto[0]	auto[0]	auto[1]	6010315	1			T25	61990		T26	135		T31	25
all_values[26]	auto[0]	auto[1]	auto[0]	640115	1			T25	6272		T26	23		T31	12
all_values[26]	auto[0]	auto[1]	auto[1]	5931963	1			T25	60560		T26	106		T31	34
all_values[26]	auto[1]	auto[0]	auto[1]	88004	1			T25	933		T21	1		T1	286
all_values[26]	auto[1]	auto[1]	auto[1]	87281	1			T25	954		T1	197		T12	3
all_values[27]	auto[0]	auto[0]	auto[0]	2787259	1			T24	257		T25	6549		T26	8
all_values[27]	auto[0]	auto[0]	auto[1]	5942410	1			T25	64277		T26	135		T31	14
all_values[27]	auto[0]	auto[1]	auto[0]	655239	1			T25	6397		T26	24		T31	4
all_values[27]	auto[0]	auto[1]	auto[1]	5981715	1			T25	58859		T26	134		T31	51
all_values[27]	auto[1]	auto[0]	auto[1]	87850	1			T25	970		T21	2		T1	234
all_values[27]	auto[1]	auto[1]	auto[1]	87770	1			T25	930		T1	237		T12	3
all_values[28]	auto[0]	auto[0]	auto[0]	2779367	1			T24	257		T25	8002		T26	21
all_values[28]	auto[0]	auto[0]	auto[1]	5971084	1			T25	60620		T26	151		T31	35
all_values[28]	auto[0]	auto[1]	auto[0]	646107	1			T25	6479		T26	26		T31	5
all_values[28]	auto[0]	auto[1]	auto[1]	5969539	1			T25	61017		T26	103		T31	11
all_values[28]	auto[1]	auto[0]	auto[1]	88168	1			T25	918		T1	253		T12	6
all_values[28]	auto[1]	auto[1]	auto[1]	87978	1			T25	946		T1	235		T12	2
all_values[29]	auto[0]	auto[0]	auto[0]	2778226	1			T24	257		T25	6926		T26	24
all_values[29]	auto[0]	auto[0]	auto[1]	5960047	1			T25	56977		T26	113		T31	28
all_values[29]	auto[0]	auto[1]	auto[0]	653673	1			T25	7212		T26	29		T1	1396
all_values[29]	auto[0]	auto[1]	auto[1]	5974649	1			T25	64979		T26	135		T31	31
all_values[29]	auto[1]	auto[0]	auto[1]	87948	1			T25	878		T21	2		T1	271
all_values[29]	auto[1]	auto[1]	auto[1]	87700	1			T25	1010		T1	201		T12	3
all_values[30]	auto[0]	auto[0]	auto[0]	2778451	1			T24	257		T25	7408		T26	33
all_values[30]	auto[0]	auto[0]	auto[1]	5981868	1			T25	58186		T26	160		T31	35
all_values[30]	auto[0]	auto[1]	auto[0]	649940	1			T25	6809		T26	21		T31	3
all_values[30]	auto[0]	auto[1]	auto[1]	5956476	1			T25	63694		T26	87		T31	33
all_values[30]	auto[1]	auto[0]	auto[1]	87678	1			T25	971		T21	2		T1	254
all_values[30]	auto[1]	auto[1]	auto[1]	87830	1			T25	914		T1	240		T12	2
all_values[31]	auto[0]	auto[0]	auto[0]	2774320	1			T24	257		T25	6941		T26	31
all_values[31]	auto[0]	auto[0]	auto[1]	5984870	1			T25	59647		T26	128		T31	42
all_values[31]	auto[0]	auto[1]	auto[0]	649625	1			T25	6233		T26	15		T1	1496
all_values[31]	auto[0]	auto[1]	auto[1]	5957598	1			T25	63276		T26	127		T31	22
all_values[31]	auto[1]	auto[0]	auto[1]	88104	1			T25	938		T21	1		T1	259
all_values[31]	auto[1]	auto[1]	auto[1]	87726	1			T25	947		T1	187		T12	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal