Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[1]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[2]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[3]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[4]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[5]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[6]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[7]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[8]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[9]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[10]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[11]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[12]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[13]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[14]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[15]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[16]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[17]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[18]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[19]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[20]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[21]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[22]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[23]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[24]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[25]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[26]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[27]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[28]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[29]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[30]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[31]	15291444	1			T24	437		T25	136911		T26	131

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300113918

1

T24

4128

T25

291379

T26

2079

auto[1]

189212290

1

T24

9856

T25

146735

T26

2113

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390694623

1

T24

8339

T25

334898

T26

4192

auto[1]

98631585

1

T24

5645

T25

103216

T29

228

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361909655

1

T24

8359

T25

304879

T26

4192

auto[1]

127416553

1

T24

5625

T25

133235

T29

1827

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5770950	1			T24	42		T25	51086		T26	59
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3989371	1			T24	117		T25	27978		T26	72
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1546708	1			T24	86		T25	16040		T29	6
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2068256	1			T25	24472		T29	21		T33	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	373917	1			T24	94		T25	1567		T29	60
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1542242	1			T24	98		T25	15768		T29	2
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5761966	1			T24	37		T25	51377		T26	79
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4001021	1			T24	141		T25	28039		T26	52
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1557031	1			T24	111		T25	16146		T29	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2062136	1			T25	24014		T29	8		T21	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	373905	1			T24	74		T25	1702		T29	24
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1535385	1			T24	74		T25	15633		T29	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5752090	1			T24	43		T25	50802		T26	59
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4007468	1			T24	112		T25	28139		T26	72
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1549054	1			T24	110		T25	15848		T29	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2071508	1			T25	24283		T29	17		T33	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	372051	1			T24	86		T25	1647		T29	97
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1539273	1			T24	86		T25	16192		T29	7
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5744535	1			T24	38		T25	50609		T26	68
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4008942	1			T24	136		T25	27908		T26	63
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1552398	1			T24	92		T25	16499		T29	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2068038	1			T25	23641		T29	12		T33	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	373298	1			T24	95		T25	1691		T29	56
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1544233	1			T24	76		T25	16563		T29	6
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5756862	1			T24	32		T25	51214		T26	80
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4003338	1			T24	128		T25	28177		T26	51
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1545888	1			T24	97		T25	16501		T22	31
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2070049	1			T25	23545		T29	26		T33	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	373315	1			T24	72		T25	1621		T29	90
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1541992	1			T24	108		T25	15853		T29	5
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5752967	1			T24	36		T25	51473		T26	65
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4002506	1			T24	133		T25	28271		T26	66
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1556099	1			T24	88		T25	16343		T22	38
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2063588	1			T25	23154		T29	11		T33	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	372753	1			T24	96		T25	1538		T29	64
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1543531	1			T24	84		T25	16132		T29	3
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5747261	1			T24	36		T25	50615		T26	64
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4006709	1			T24	154		T25	28188		T26	67
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1556220	1			T24	88		T25	16350		T29	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2071662	1			T25	23540		T29	14		T33	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	371678	1			T24	82		T25	1786		T29	44
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1537914	1			T24	77		T25	16432		T29	7
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5767457	1			T24	43		T25	51278		T26	75
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3995243	1			T24	123		T25	28097		T26	56
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1549724	1			T24	87		T25	15894		T29	7
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2065317	1			T25	23757		T33	10		T22	113
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	374789	1			T24	98		T25	1670		T33	46
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1538914	1			T24	86		T25	16215		T33	11
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5749917	1			T24	38		T25	50988		T26	60
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4004237	1			T24	153		T25	28263		T26	71
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1541928	1			T24	82		T25	16155		T29	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2079177	1			T25	23920		T29	25		T33	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	374018	1			T24	90		T25	1601		T29	86
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1542167	1			T24	74		T25	15984		T29	10
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5763765	1			T24	39		T25	50374		T26	59
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3993692	1			T24	143		T25	27934		T26	72
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1546300	1			T24	84		T25	16534		T29	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2074955	1			T25	24399		T29	3		T33	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	374278	1			T24	99		T25	1720		T29	31
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1538454	1			T24	72		T25	15950		T33	6
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5753917	1			T24	39		T25	50469		T26	75
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4005696	1			T24	109		T25	28122		T26	56
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1551540	1			T24	77		T25	16321		T29	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2069086	1			T25	24428		T29	13		T33	7
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	373139	1			T24	92		T25	1685		T29	74
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1538066	1			T24	120		T25	15886		T33	2
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5757134	1			T24	36		T25	51266		T26	78
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4000889	1			T24	132		T25	27967		T26	53
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1545832	1			T24	93		T25	16068		T33	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2075442	1			T25	24237		T29	7		T33	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	376953	1			T24	96		T25	1650		T29	31
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1535194	1			T24	80		T25	15723		T29	2
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5758479	1			T24	36		T25	50805		T26	50
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4007616	1			T24	122		T25	27867		T26	81
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1549085	1			T24	88		T25	16350		T29	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2068933	1			T25	24027		T29	7		T33	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	372878	1			T24	74		T25	1665		T29	46
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1534453	1			T24	117		T25	16197		T29	3
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5754066	1			T24	40		T25	51092		T26	74
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4006913	1			T24	150		T25	28215		T26	57
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1552641	1			T24	87		T25	16303		T29	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2069672	1			T25	23506		T29	15		T33	7
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	374291	1			T24	86		T25	1658		T29	45
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1533861	1			T24	74		T25	16137		T29	5
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5753034	1			T24	40		T25	50962		T26	75
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4006847	1			T24	137		T25	28224		T26	56
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1544284	1			T24	112		T25	16153		T29	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2074758	1			T25	23987		T29	6		T21	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	372556	1			T24	80		T25	1673		T29	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1539965	1			T24	68		T25	15912		T29	4
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5748924	1			T24	35		T25	51762		T26	58
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4009220	1			T24	117		T25	28076		T26	73
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1553588	1			T24	113		T25	16476		T29	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2068127	1			T25	23304		T29	14		T21	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	372963	1			T24	100		T25	1558		T29	42
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1538622	1			T24	72		T25	15735		T21	27
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5760126	1			T24	38		T25	51531		T26	55
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4004199	1			T24	104		T25	27949		T26	76
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1548611	1			T24	83		T25	16135		T29	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2072603	1			T25	23586		T29	11		T33	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	373462	1			T24	106		T25	1520		T29	23
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1532443	1			T24	106		T25	16190		T33	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5747555	1			T24	36		T25	51105		T26	56
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4011947	1			T24	150		T25	28084		T26	75
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1539302	1			T24	115		T25	16129		T29	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2085685	1			T25	23718		T33	10		T21	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	375187	1			T24	58		T25	1677		T33	53
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1531768	1			T24	78		T25	16198		T33	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5759313	1			T24	37		T25	51040		T26	52
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4010159	1			T24	145		T25	28213		T26	79
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1545082	1			T24	84		T25	16326		T29	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2073468	1			T25	23454		T29	8		T33	3
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	374010	1			T24	106		T25	1669		T29	53
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1529412	1			T24	65		T25	16209		T29	4
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5761553	1			T24	37		T25	51245		T26	73
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4002479	1			T24	123		T25	28315		T26	58
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1542140	1			T24	86		T25	16003		T29	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2080318	1			T25	23518		T29	12		T33	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	375332	1			T24	101		T25	1667		T29	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1529622	1			T24	90		T25	16163		T21	11
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5756364	1			T24	36		T25	50726		T26	45
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4010325	1			T24	118		T25	28110		T26	86
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1545003	1			T24	100		T25	16004		T29	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2076404	1			T25	24035		T29	11		T33	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	372840	1			T24	86		T25	1769		T29	27
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1530508	1			T24	97		T25	16267		T29	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5753207	1			T24	35		T25	50714		T26	63
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4000778	1			T24	153		T25	27817		T26	68
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1544584	1			T24	98		T25	16187		T29	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2084478	1			T25	24032		T29	6		T33	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	375497	1			T24	84		T25	1621		T29	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1532900	1			T24	67		T25	16540		T29	4
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5760053	1			T24	36		T25	50467		T26	62
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4002530	1			T24	114		T25	28260		T26	69
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1540241	1			T24	92		T25	16381		T29	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2079683	1			T25	24080		T29	10		T33	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	374574	1			T24	98		T25	1648		T29	27
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1534363	1			T24	97		T25	16075		T33	3
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5755837	1			T24	45		T25	51208		T26	67
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4011155	1			T24	136		T25	28206		T26	64
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1548218	1			T24	56		T25	16069		T29	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2071694	1			T25	23921		T29	21		T33	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	372884	1			T24	108		T25	1627		T29	68
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1531656	1			T24	92		T25	15880		T29	4
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5763733	1			T24	38		T25	51109		T26	70
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3999929	1			T24	150		T25	28146		T26	61
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1549273	1			T24	74		T25	16180		T29	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2075032	1			T25	23497		T29	12		T33	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	374076	1			T24	105		T25	1703		T29	46
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1529401	1			T24	70		T25	16276		T29	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5765431	1			T24	40		T25	50956		T26	72
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4013446	1			T24	150		T25	28316		T26	59
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1544616	1			T24	68		T25	15817		T29	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2065969	1			T25	24090		T29	17		T33	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	370848	1			T24	103		T25	1701		T29	61
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1531134	1			T24	76		T25	16031		T29	6
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5770435	1			T24	35		T25	50861		T26	60
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3998263	1			T24	121		T25	28041		T26	71
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1542230	1			T24	74		T25	16406		T33	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2074117	1			T25	23943		T29	12		T33	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	374890	1			T24	101		T25	1694		T29	50
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1531509	1			T24	106		T25	15966		T29	3
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5770352	1			T24	41		T25	51157		T26	71
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3999811	1			T24	113		T25	28180		T26	60
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1541915	1			T24	92		T25	16055		T29	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2071090	1			T25	23486		T29	8		T33	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	374651	1			T24	94		T25	1648		T29	17
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1533625	1			T24	97		T25	16385		T33	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5771026	1			T24	37		T25	51195		T26	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3997330	1			T24	137		T25	27952		T26	62
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1546404	1			T24	96		T25	15647		T29	4
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2072468	1			T25	24193		T33	8		T21	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	374687	1			T24	91		T25	1713		T33	21
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1529529	1			T24	76		T25	16211		T33	6
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5751651	1			T24	38		T25	50570		T26	65
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4008075	1			T24	136		T25	28256		T26	66
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1544996	1			T24	80		T25	16095		T29	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2076089	1			T25	24025		T29	16		T33	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	375624	1			T24	94		T25	1758		T29	43
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1535009	1			T24	89		T25	16207		T29	6
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5762687	1			T24	44		T25	51126		T26	59
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4008781	1			T24	139		T25	27965		T26	72
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1544148	1			T24	106		T25	15893		T29	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2077196	1			T25	23982		T29	15		T33	17
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	370669	1			T24	62		T25	1797		T29	74
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1527963	1			T24	86		T25	16148		T29	4
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5767857	1			T24	40		T25	51262		T26	62
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4001780	1			T24	135		T25	27856		T26	69
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1543373	1			T24	106		T25	15914		T22	40
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2077960	1			T25	24359		T29	5		T33	18
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	372453	1			T24	74		T25	1633		T29	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1528021	1			T24	82		T25	15887		T29	3

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal