Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[1]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[2]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[3]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[4]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[5]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[6]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[7]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[8]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[9]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[10]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[11]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[12]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[13]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[14]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[15]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[16]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[17]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[18]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[19]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[20]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[21]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[22]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[23]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[24]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[25]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[26]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[27]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[28]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[29]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[30]	15291444	1			T24	437		T25	136911		T26	131
bins_for_gpio_bits[31]	15291444	1			T24	437		T25	136911		T26	131

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300113918

1

T24

4128

T25

291379

T26

2079

auto[1]

189212290

1

T24

9856

T25

146735

T26

2113

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300105054

1

T24

4137

T25

291378

T26

2079

auto[1]

189221154

1

T24

9847

T25

146737

T26

2113

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9112058	1			T24	105		T25	88850		T26	59
bins_for_gpio_bits[0]	auto[0]	auto[1]	273546	1			T24	23		T25	2747		T29	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	273856	1			T24	23		T25	2748		T29	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	5631984	1			T24	286		T25	42566		T26	72
bins_for_gpio_bits[1]	auto[0]	auto[0]	9107548	1			T24	124		T25	88839		T26	79
bins_for_gpio_bits[1]	auto[0]	auto[1]	273328	1			T24	25		T25	2697		T29	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	273585	1			T24	24		T25	2698		T29	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5636983	1			T24	264		T25	42677		T26	52
bins_for_gpio_bits[2]	auto[0]	auto[0]	9097802	1			T24	131		T25	88048		T26	59
bins_for_gpio_bits[2]	auto[0]	auto[1]	274597	1			T24	22		T25	2885		T29	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	274850	1			T24	22		T25	2885		T29	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	5644195	1			T24	262		T25	43093		T26	72
bins_for_gpio_bits[3]	auto[0]	auto[0]	9089491	1			T24	107		T25	87845		T26	68
bins_for_gpio_bits[3]	auto[0]	auto[1]	275212	1			T24	23		T25	2904		T29	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	275480	1			T24	23		T25	2904		T29	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5651261	1			T24	284		T25	43258		T26	63
bins_for_gpio_bits[4]	auto[0]	auto[0]	9098089	1			T24	102		T25	88444		T26	80
bins_for_gpio_bits[4]	auto[0]	auto[1]	274444	1			T24	28		T25	2815		T22	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	274710	1			T24	27		T25	2816		T22	7
bins_for_gpio_bits[4]	auto[1]	auto[1]	5644201	1			T24	280		T25	42836		T26	51
bins_for_gpio_bits[5]	auto[0]	auto[0]	9098371	1			T24	101		T25	88193		T26	65
bins_for_gpio_bits[5]	auto[0]	auto[1]	273969	1			T24	23		T25	2777		T21	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	274283	1			T24	23		T25	2777		T21	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5644821	1			T24	290		T25	43164		T26	66
bins_for_gpio_bits[6]	auto[0]	auto[0]	9099842	1			T24	100		T25	87670		T26	64
bins_for_gpio_bits[6]	auto[0]	auto[1]	275001	1			T24	24		T25	2835		T29	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	275301	1			T24	24		T25	2835		T29	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	5641300	1			T24	289		T25	43571		T26	67
bins_for_gpio_bits[7]	auto[0]	auto[0]	9108397	1			T24	110		T25	88097		T26	75
bins_for_gpio_bits[7]	auto[0]	auto[1]	273813	1			T24	21		T25	2832		T29	3
bins_for_gpio_bits[7]	auto[1]	auto[0]	274101	1			T24	20		T25	2832		T29	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	5635133	1			T24	286		T25	43150		T26	56
bins_for_gpio_bits[8]	auto[0]	auto[0]	9096183	1			T24	98		T25	88224		T26	60
bins_for_gpio_bits[8]	auto[0]	auto[1]	274568	1			T24	22		T25	2838		T29	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	274839	1			T24	22		T25	2839		T29	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	5645854	1			T24	295		T25	43010		T26	71
bins_for_gpio_bits[9]	auto[0]	auto[0]	9111238	1			T24	103		T25	88420		T26	59
bins_for_gpio_bits[9]	auto[0]	auto[1]	273522	1			T24	20		T25	2886		T29	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	273782	1			T24	20		T25	2887		T29	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5632902	1			T24	294		T25	42718		T26	72
bins_for_gpio_bits[10]	auto[0]	auto[0]	9099341	1			T24	98		T25	88342		T26	75
bins_for_gpio_bits[10]	auto[0]	auto[1]	274925	1			T24	19		T25	2876		T29	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	275202	1			T24	18		T25	2876		T29	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	5641976	1			T24	302		T25	42817		T26	56
bins_for_gpio_bits[11]	auto[0]	auto[0]	9104396	1			T24	105		T25	88755		T26	78
bins_for_gpio_bits[11]	auto[0]	auto[1]	273726	1			T24	25		T25	2816		T33	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	274012	1			T24	24		T25	2816		T33	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5639310	1			T24	283		T25	42524		T26	53
bins_for_gpio_bits[12]	auto[0]	auto[0]	9102655	1			T24	99		T25	88321		T26	50
bins_for_gpio_bits[12]	auto[0]	auto[1]	273573	1			T24	25		T25	2860		T29	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	273842	1			T24	25		T25	2861		T29	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5641374	1			T24	288		T25	42869		T26	81
bins_for_gpio_bits[13]	auto[0]	auto[0]	9102618	1			T24	104		T25	88072		T26	74
bins_for_gpio_bits[13]	auto[0]	auto[1]	273477	1			T24	24		T25	2829		T29	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	273761	1			T24	23		T25	2829		T29	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	5641588	1			T24	286		T25	43181		T26	57
bins_for_gpio_bits[14]	auto[0]	auto[0]	9097513	1			T24	127		T25	88282		T26	75
bins_for_gpio_bits[14]	auto[0]	auto[1]	274282	1			T24	25		T25	2820		T29	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	274563	1			T24	25		T25	2820		T29	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	5645086	1			T24	260		T25	42989		T26	56
bins_for_gpio_bits[15]	auto[0]	auto[0]	9095793	1			T24	128		T25	88775		T26	58
bins_for_gpio_bits[15]	auto[0]	auto[1]	274602	1			T24	21		T25	2767		T29	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	274846	1			T24	20		T25	2767		T29	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	5646203	1			T24	268		T25	42602		T26	73
bins_for_gpio_bits[16]	auto[0]	auto[0]	9106394	1			T24	104		T25	88380		T26	55
bins_for_gpio_bits[16]	auto[0]	auto[1]	274669	1			T24	18		T25	2870		T29	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	274946	1			T24	17		T25	2872		T29	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	5635435	1			T24	298		T25	42789		T26	76
bins_for_gpio_bits[17]	auto[0]	auto[0]	9097831	1			T24	126		T25	88110		T26	56
bins_for_gpio_bits[17]	auto[0]	auto[1]	274415	1			T24	26		T25	2842		T29	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	274711	1			T24	25		T25	2842		T29	3
bins_for_gpio_bits[17]	auto[1]	auto[1]	5644487	1			T24	260		T25	43117		T26	75
bins_for_gpio_bits[18]	auto[0]	auto[0]	9103696	1			T24	99		T25	87963		T26	52
bins_for_gpio_bits[18]	auto[0]	auto[1]	273901	1			T24	22		T25	2856		T29	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	274167	1			T24	22		T25	2857		T29	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5639680	1			T24	294		T25	43235		T26	79
bins_for_gpio_bits[19]	auto[0]	auto[0]	9110021	1			T24	99		T25	87965		T26	73
bins_for_gpio_bits[19]	auto[0]	auto[1]	273730	1			T24	24		T25	2800		T29	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	273990	1			T24	24		T25	2801		T29	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	5633703	1			T24	290		T25	43345		T26	58
bins_for_gpio_bits[20]	auto[0]	auto[0]	9103368	1			T24	112		T25	87923		T26	45
bins_for_gpio_bits[20]	auto[0]	auto[1]	274110	1			T24	24		T25	2841		T29	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	274403	1			T24	24		T25	2842		T29	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	5639563	1			T24	277		T25	43305		T26	86
bins_for_gpio_bits[21]	auto[0]	auto[0]	9107199	1			T24	110		T25	88015		T26	63
bins_for_gpio_bits[21]	auto[0]	auto[1]	274764	1			T24	23		T25	2917		T29	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	275070	1			T24	23		T25	2918		T29	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5634411	1			T24	281		T25	43061		T26	68
bins_for_gpio_bits[22]	auto[0]	auto[0]	9104922	1			T24	104		T25	88109		T26	62
bins_for_gpio_bits[22]	auto[0]	auto[1]	274789	1			T24	24		T25	2818		T29	3
bins_for_gpio_bits[22]	auto[1]	auto[0]	275055	1			T24	24		T25	2819		T29	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	5636678	1			T24	285		T25	43165		T26	69
bins_for_gpio_bits[23]	auto[0]	auto[0]	9101435	1			T24	87		T25	88428		T26	67
bins_for_gpio_bits[23]	auto[0]	auto[1]	274027	1			T24	14		T25	2770		T29	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	274314	1			T24	14		T25	2770		T29	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5641668	1			T24	322		T25	42943		T26	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	9113596	1			T24	89		T25	87944		T26	70
bins_for_gpio_bits[24]	auto[0]	auto[1]	274173	1			T24	23		T25	2840		T29	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	274442	1			T24	23		T25	2842		T29	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	5629233	1			T24	302		T25	43285		T26	61
bins_for_gpio_bits[25]	auto[0]	auto[0]	9101926	1			T24	85		T25	88013		T26	72
bins_for_gpio_bits[25]	auto[0]	auto[1]	273818	1			T24	23		T25	2849		T29	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	274090	1			T24	23		T25	2850		T29	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	5641610	1			T24	306		T25	43199		T26	59
bins_for_gpio_bits[26]	auto[0]	auto[0]	9111780	1			T24	86		T25	88333		T26	60
bins_for_gpio_bits[26]	auto[0]	auto[1]	274691	1			T24	23		T25	2877		T33	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	275002	1			T24	23		T25	2877		T33	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5629971	1			T24	305		T25	42824		T26	71
bins_for_gpio_bits[27]	auto[0]	auto[0]	9109614	1			T24	112		T25	87827		T26	71
bins_for_gpio_bits[27]	auto[0]	auto[1]	273502	1			T24	21		T25	2870		T29	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	273743	1			T24	21		T25	2871		T29	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	5634585	1			T24	283		T25	43343		T26	60
bins_for_gpio_bits[28]	auto[0]	auto[0]	9115395	1			T24	114		T25	88209		T26	69
bins_for_gpio_bits[28]	auto[0]	auto[1]	274231	1			T24	19		T25	2825		T29	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	274503	1			T24	19		T25	2826		T29	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	5627315	1			T24	285		T25	43051		T26	62
bins_for_gpio_bits[29]	auto[0]	auto[0]	9097907	1			T24	96		T25	87816		T26	65
bins_for_gpio_bits[29]	auto[0]	auto[1]	274578	1			T24	22		T25	2873		T29	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	274829	1			T24	22		T25	2874		T29	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	5644130	1			T24	297		T25	43348		T26	66
bins_for_gpio_bits[30]	auto[0]	auto[0]	9109967	1			T24	123		T25	88208		T26	59
bins_for_gpio_bits[30]	auto[0]	auto[1]	273772	1			T24	27		T25	2793		T29	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	274064	1			T24	27		T25	2793		T29	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	5633641	1			T24	260		T25	43117		T26	72
bins_for_gpio_bits[31]	auto[0]	auto[0]	9115126	1			T24	122		T25	88743		T26	62
bins_for_gpio_bits[31]	auto[0]	auto[1]	273787	1			T24	24		T25	2792		T21	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	274064	1			T24	24		T25	2792		T21	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5628467	1			T24	267		T25	42584		T26	69