Unified Coverage Report :: Group Instance : intr_event_falling_pin26

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8831856

1

T24

257

T25

71116

T26

98

auto[1]

6710387

1

T25

66866

T26

203

T31

55

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14694907

1

T24

257

T25

130000

T26

292

auto[1]

847336

1

T25

7982

T26

9

T31

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8859697

1

T24

257

T25

72963

T26

136

auto[1]

6682546

1

T25

65019

T26

165

T31

21

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2919571

1

T25

28121

T26

42

T31

6

auto[1]

auto[0]

auto[1]

424513

1

T25

4068

T26

2

T21

1

auto[1]

auto[1]

auto[0]

2915639

1

T25

28916

T26

114

T31

14

auto[1]

auto[1]

auto[1]

422823

1

T25

3914

T26

7

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8819924

1

T24

257

T25

68397

T26

147

auto[1]

6722319

1

T25

69585

T26

154

T31

20

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14691575

1

T24

257

T25

129386

T26

294

auto[1]

850668

1

T25

8596

T26

7

T31

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8842169

1

T24

257

T25

69455

T26

118

auto[1]

6700074

1

T25

68527

T26

183

T31

38

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2928807

1

T25

28737

T26

80

T31

30

auto[1]

auto[0]

auto[1]

426616

1

T25

4071

T26

3

T31

1

auto[1]

auto[1]

auto[0]

2920599

1

T25

31194

T26

96

T31

7

auto[1]

auto[1]

auto[1]

424052

1

T25

4525

T26

4

T1

1146

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8856133

1

T24

257

T25

69608

T26

107

auto[1]

6686110

1

T25

68374

T26

194

T31

28

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14695014

1

T24

257

T25

129138

T26

290

auto[1]

847229

1

T25

8844

T26

11

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8857934

1

T24

257

T25

68140

T26

119

auto[1]

6684309

1

T25

69842

T26

182

T31

38

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2915028

1

T25

29887

T26

50

T31

18

auto[1]

auto[0]

auto[1]

424305

1

T25

4316

T26

6

T31

1

auto[1]

auto[1]

auto[0]

2922052

1

T25

31111

T26

121

T31

18

auto[1]

auto[1]

auto[1]

422924

1

T25

4528

T26

5

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8848102

1

T24

257

T25

68514

T26

115

auto[1]

6694141

1

T25

69468

T26

186

T31

30

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14690447

1

T24

257

T25

128971

T26

292

auto[1]

851796

1

T25

9011

T26

9

T21

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8837845

1

T24

257

T25

67703

T26

168

auto[1]

6704398

1

T25

70279

T26

133

T31

25

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2936515

1

T25

29152

T26

64

T31

19

auto[1]

auto[0]

auto[1]

428129

1

T25

4190

T26

7

T21

1

auto[1]

auto[1]

auto[0]

2916087

1

T25

32116

T26

60

T31

6

auto[1]

auto[1]

auto[1]

423667

1

T25

4821

T26

2

T1

1085

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8830452

1

T24

257

T25

66993

T26

116

auto[1]

6711791

1

T25

70989

T26

185

T31

45

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14692627

1

T24

257

T25

129335

T26

296

auto[1]

849616

1

T25

8647

T26

5

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8833239

1

T24

257

T25

69315

T26

178

auto[1]

6709004

1

T25

68667

T26

123

T31

15

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2937175

1

T25

31070

T26

48

T21

7

auto[1]

auto[0]

auto[1]

425375

1

T25

4424

T26

2

T1

1182

auto[1]

auto[1]

auto[0]

2922213

1

T25

28950

T26

70

T31

13

auto[1]

auto[1]

auto[1]

424241

1

T25

4223

T26

3

T31

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8820643

1

T24

257

T25

72703

T26

204

auto[1]

6721600

1

T25

65279

T26

97

T31

22

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14689602

1

T24

257

T25

129569

T26

293

auto[1]

852641

1

T25

8413

T26

8

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8829057

1

T24

257

T25

71073

T26

161

auto[1]

6713186

1

T25

66909

T26

140

T31

27

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2929182

1

T25

30316

T26

95

T31

20

auto[1]

auto[0]

auto[1]

426208

1

T25

4379

T26

5

T31

1

auto[1]

auto[1]

auto[0]

2931363

1

T25

28180

T26

37

T31

5

auto[1]

auto[1]

auto[1]

426433

1

T25

4034

T26

3

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8855807

1

T24

257

T25

69018

T26

129

auto[1]

6686436

1

T25

68964

T26

172

T31

17

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14689303

1

T24

257

T25

129360

T26

291

auto[1]

852940

1

T25

8622

T26

10

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8818762

1

T24

257

T25

68452

T26

126

auto[1]

6723481

1

T25

69530

T26

175

T31

26

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2933595

1

T25

32288

T26

55

T31

16

auto[1]

auto[0]

auto[1]

424509

1

T25

4738

T26

3

T31

2

auto[1]

auto[1]

auto[0]

2936946

1

T25

28620

T26

110

T31

8

auto[1]

auto[1]

auto[1]

428431

1

T25

3884

T26

7

T1

1270

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8845005

1

T24

257

T25

73241

T26

147

auto[1]

6697238

1

T25

64741

T26

154

T31

61

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14689994

1

T24

257

T25

129548

T26

291

auto[1]

852249

1

T25

8434

T26

10

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8833303

1

T24

257

T25

69856

T26

114

auto[1]

6708940

1

T25

68126

T26

187

T31

38

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2927190

1

T25

31488

T26

76

T31

9

auto[1]

auto[0]

auto[1]

424664

1

T25

4514

T26

4

T1

1078

auto[1]

auto[1]

auto[0]

2929501

1

T25

28204

T26

101

T31

27

auto[1]

auto[1]

auto[1]

427585

1

T25

3920

T26

6

T31

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8850320

1

T24

257

T25

69539

T26

141

auto[1]

6691923

1

T25

68443

T26

160

T31

28

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14694380

1

T24

257

T25

129685

T26

292

auto[1]

847863

1

T25

8297

T26

9

T31

3

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8859609

1

T24

257

T25

71170

T26

183

auto[1]

6682634

1

T25

66812

T26

118

T31

46

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2912285

1

T25

29699

T26

49

T31

31

auto[1]

auto[0]

auto[1]

422734

1

T25

4166

T26

6

T31

2

auto[1]

auto[1]

auto[0]

2922486

1

T25

28816

T26

60

T31

12

auto[1]

auto[1]

auto[1]

425129

1

T25

4131

T26

3

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8846629

1

T24

257

T25

71064

T26

153

auto[1]

6695614

1

T25

66918

T26

148

T31

61

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14691741

1

T24

257

T25

129740

T26

291

auto[1]

850502

1

T25

8242

T26

10

T31

4

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8840529

1

T24

257

T25

71346

T26

119

auto[1]

6701714

1

T25

66636

T26

182

T31

50

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2928337

1

T25

30325

T26

90

T31

5

auto[1]

auto[0]

auto[1]

425744

1

T25

4266

T26

5

T21

1

auto[1]

auto[1]

auto[0]

2922875

1

T25

28069

T26

82

T31

41

auto[1]

auto[1]

auto[1]

424758

1

T25

3976

T26

5

T31

4

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8841040

1

T24

257

T25

70539

T26

156

auto[1]

6701203

1

T25

67443

T26

145

T31

29

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14683349

1

T24

257

T25

129059

T26

293

auto[1]

858894

1

T25

8923

T26

8

T31

4

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8789172

1

T24

257

T25

67615

T26

150

auto[1]

6753071

1

T25

70367

T26

151

T31

43

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2946580

1

T25

30029

T26

56

T31

24

auto[1]

auto[0]

auto[1]

429294

1

T25

4321

T26

1

T31

3

auto[1]

auto[1]

auto[0]

2947597

1

T25

31415

T26

87

T31

15

auto[1]

auto[1]

auto[1]

429600

1

T25

4602

T26

7

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8872044

1

T24

257

T25

70278

T26

139

auto[1]

6670199

1

T25

67704

T26

162

T31

24

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14699199

1

T24

257

T25

129188

T26

291

auto[1]

843044

1

T25

8794

T26

10

T31

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8894065

1

T24

257

T25

67998

T26

84

auto[1]

6648178

1

T25

69984

T26

217

T31

26

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2917921

1

T25

29708

T26

103

T31

17

auto[1]

auto[0]

auto[1]

423608

1

T25

4287

T26

5

T21

1

auto[1]

auto[1]

auto[0]

2887213

1

T25

31482

T26

104

T31

8

auto[1]

auto[1]

auto[1]

419436

1

T25

4507

T26

5

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8845345

1

T24

257

T25

68090

T26

144

auto[1]

6696898

1

T25

69892

T26

157

T31

17

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14692313

1

T24

257

T25

128924

T26

292

auto[1]

849930

1

T25

9058

T26

9

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8840774

1

T24

257

T25

67063

T26

129

auto[1]

6701469

1

T25

70919

T26

172

T31

41

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2912691

1

T25

31512

T26

94

T31

23

auto[1]

auto[0]

auto[1]

423367

1

T25

4690

T26

5

T31

2

auto[1]

auto[1]

auto[0]

2938848

1

T25

30349

T26

69

T31

16

auto[1]

auto[1]

auto[1]

426563

1

T25

4368

T26

4

T1

1357

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8811202

1

T24

257

T25

71849

T26

120

auto[1]

6731041

1

T25

66133

T26

181

T31

61

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14695942

1

T24

257

T25

129743

T26

294

auto[1]

846301

1

T25

8239

T26

7

T31

4

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8867482

1

T24

257

T25

71732

T26

152

auto[1]

6674761

1

T25

66250

T26

149

T31

61

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2907380

1

T25

29235

T26

47

T31

8

auto[1]

auto[0]

auto[1]

421177

1

T25

4082

T26

2

T31

2

auto[1]

auto[1]

auto[0]

2921080

1

T25

28776

T26

95

T31

49

auto[1]

auto[1]

auto[1]

425124

1

T25

4157

T26

5

T31

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8844111

1

T24

257

T25

67748

T26

178

auto[1]

6698132

1

T25

70234

T26

123

T31

52

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14689682

1

T24

257

T25

129179

T26

288

auto[1]

852561

1

T25

8803

T26

13

T21

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8840938

1

T24

257

T25

68573

T26

124

auto[1]

6701305

1

T25

69409

T26

177

T21

24

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2929350

1

T25

30614

T26

92

T21

22

auto[1]

auto[0]

auto[1]

426814

1

T25

4517

T26

9

T21

2

auto[1]

auto[1]

auto[0]

2919394

1

T25

29992

T26

72

T1

7631

auto[1]

auto[1]

auto[1]

425747

1

T25

4286

T26

4

T1

1212

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8838264

1

T24

257

T25

67937

T26

116

auto[1]

6703979

1

T25

70045

T26

185

T31

10

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14690491

1

T24

257

T25

129618

T26

291

auto[1]

851752

1

T25

8364

T26

10

T31

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8840809

1

T24

257

T25

70217

T26

136

auto[1]

6701434

1

T25

67765

T26

165

T31

29

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2932407

1

T25

28485

T26

60

T31

28

auto[1]

auto[0]

auto[1]

426344

1

T25

3896

T26

5

T31

1

auto[1]

auto[1]

auto[0]

2917275

1

T25

30916

T26

95

T1

8020

auto[1]

auto[1]

auto[1]

425408

1

T25

4468

T26

5

T1

1271

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8809543

1

T24

257

T25

71586

T26

142

auto[1]

6732700

1

T25

66396

T26

159

T31

27

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14689703

1

T24

257

T25

130525

T26

296

auto[1]

852540

1

T25

7457

T26

5

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8833950

1

T24

257

T25

75306

T26

187

auto[1]

6708293

1

T25

62676

T26

114

T31

15

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2920545

1

T25

27529

T26

48

T31

6

auto[1]

auto[0]

auto[1]

424355

1

T25

3701

T26

1

T31

1

auto[1]

auto[1]

auto[0]

2935208

1

T25

27690

T26

61

T31

7

auto[1]

auto[1]

auto[1]

428185

1

T25

3756

T26

4

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8840346

1

T24

257

T25

72859

T26

150

auto[1]

6701897

1

T25

65123

T26

151

T31

56

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14699137

1

T24

257

T25

129512

T26

292

auto[1]

843106

1

T25

8470

T26

9

T31

1

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8880771

1

T24

257

T25

70121

T26

175

auto[1]

6661472

1

T25

67861

T26

126

T31

19

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2915023

1

T25

31755

T26

69

T31

12

auto[1]

auto[0]

auto[1]

422527

1

T25

4559

T26

4

T21

1

auto[1]

auto[1]

auto[0]

2903343

1

T25

27636

T26

48

T31

6

auto[1]

auto[1]

auto[1]

420579

1

T25

3911

T26

5

T31

1

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8856696

1

T24

257

T25

73108

T26

154

auto[1]

6685547

1

T25

64874

T26

147

T31

57

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14691573

1

T24

257

T25

129731

T26

299

auto[1]

850670

1

T25

8251

T26

2

T31

2

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8839710

1

T24

257

T25

71815

T26

213

auto[1]

6702533

1

T25

66167

T26

88

T31

36

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2930457

1

T25

31838

T26

46

T31

9

auto[1]

auto[0]

auto[1]

425749

1

T25

4723

T26

1

T21

1

auto[1]

auto[1]

auto[0]

2921406

1

T25

26078

T26

40

T31

25

auto[1]

auto[1]

auto[1]

424921

1

T25

3528

T26

1

T31

2

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8882884

1

T24

257

T25

70196

T26

172

auto[1]

6659359

1

T25

67786

T26

129

T31

46

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14695165

1

T24

257

T25

129537

T26

291

auto[1]

847078

1

T25

8445

T26

10

T21

1