Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8864326 |
1 |
|
|
T24 |
257 |
|
T25 |
69569 |
|
T26 |
147 |
| auto[1] |
6677917 |
1 |
|
|
T25 |
68413 |
|
T26 |
154 |
|
T31 |
71 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14693911 |
1 |
|
|
T24 |
257 |
|
T25 |
129067 |
|
T26 |
291 |
| auto[1] |
848332 |
1 |
|
|
T25 |
8915 |
|
T26 |
10 |
|
T31 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8855395 |
1 |
|
|
T24 |
257 |
|
T25 |
66988 |
|
T26 |
154 |
| auto[1] |
6686848 |
1 |
|
|
T25 |
70994 |
|
T26 |
147 |
|
T31 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2935175 |
1 |
|
|
T25 |
30471 |
|
T26 |
69 |
|
T21 |
3 |
| auto[1] |
auto[0] |
auto[1] |
426959 |
1 |
|
|
T25 |
4259 |
|
T26 |
5 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2903341 |
1 |
|
|
T25 |
31608 |
|
T26 |
68 |
|
T31 |
30 |
| auto[1] |
auto[1] |
auto[1] |
421373 |
1 |
|
|
T25 |
4656 |
|
T26 |
5 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |