Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8823346 |
1 |
|
|
T24 |
257 |
|
T25 |
67321 |
|
T26 |
143 |
| auto[1] |
6718897 |
1 |
|
|
T25 |
70661 |
|
T26 |
158 |
|
T31 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14689904 |
1 |
|
|
T24 |
257 |
|
T25 |
130067 |
|
T26 |
292 |
| auto[1] |
852339 |
1 |
|
|
T25 |
7915 |
|
T26 |
9 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8830928 |
1 |
|
|
T24 |
257 |
|
T25 |
73858 |
|
T26 |
156 |
| auto[1] |
6711315 |
1 |
|
|
T25 |
64124 |
|
T26 |
145 |
|
T31 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2931271 |
1 |
|
|
T25 |
26695 |
|
T26 |
72 |
|
T31 |
29 |
| auto[1] |
auto[0] |
auto[1] |
426270 |
1 |
|
|
T25 |
3667 |
|
T26 |
5 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2927705 |
1 |
|
|
T25 |
29514 |
|
T26 |
64 |
|
T31 |
10 |
| auto[1] |
auto[1] |
auto[1] |
426069 |
1 |
|
|
T25 |
4248 |
|
T26 |
4 |
|
T1 |
1178 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |