Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8830507 |
1 |
|
|
T24 |
257 |
|
T25 |
67498 |
|
T26 |
186 |
| auto[1] |
6711736 |
1 |
|
|
T25 |
70484 |
|
T26 |
115 |
|
T31 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14694667 |
1 |
|
|
T24 |
257 |
|
T25 |
129215 |
|
T26 |
297 |
| auto[1] |
847576 |
1 |
|
|
T25 |
8767 |
|
T26 |
4 |
|
T31 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8859022 |
1 |
|
|
T24 |
257 |
|
T25 |
68529 |
|
T26 |
144 |
| auto[1] |
6683221 |
1 |
|
|
T25 |
69453 |
|
T26 |
157 |
|
T31 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2911010 |
1 |
|
|
T25 |
29628 |
|
T26 |
90 |
|
T31 |
26 |
| auto[1] |
auto[0] |
auto[1] |
423092 |
1 |
|
|
T25 |
4205 |
|
T26 |
1 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2924635 |
1 |
|
|
T25 |
31058 |
|
T26 |
63 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[1] |
424484 |
1 |
|
|
T25 |
4562 |
|
T26 |
3 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |