Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8848047 |
1 |
|
|
T24 |
257 |
|
T25 |
70810 |
|
T26 |
149 |
| auto[1] |
6694196 |
1 |
|
|
T25 |
67172 |
|
T26 |
152 |
|
T31 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14695716 |
1 |
|
|
T24 |
257 |
|
T25 |
129473 |
|
T26 |
296 |
| auto[1] |
846527 |
1 |
|
|
T25 |
8509 |
|
T26 |
5 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8870615 |
1 |
|
|
T24 |
257 |
|
T25 |
70538 |
|
T26 |
170 |
| auto[1] |
6671628 |
1 |
|
|
T25 |
67444 |
|
T26 |
131 |
|
T31 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2922969 |
1 |
|
|
T25 |
31412 |
|
T26 |
67 |
|
T31 |
9 |
| auto[1] |
auto[0] |
auto[1] |
425620 |
1 |
|
|
T25 |
4603 |
|
T26 |
2 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2902132 |
1 |
|
|
T25 |
27523 |
|
T26 |
59 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
420907 |
1 |
|
|
T25 |
3906 |
|
T26 |
3 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |