Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8854916 |
1 |
|
|
T24 |
257 |
|
T25 |
68526 |
|
T26 |
158 |
| auto[1] |
6687327 |
1 |
|
|
T25 |
69456 |
|
T26 |
143 |
|
T31 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14690822 |
1 |
|
|
T24 |
257 |
|
T25 |
128977 |
|
T26 |
294 |
| auto[1] |
851421 |
1 |
|
|
T25 |
9005 |
|
T26 |
7 |
|
T31 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8829070 |
1 |
|
|
T24 |
257 |
|
T25 |
67847 |
|
T26 |
130 |
| auto[1] |
6713173 |
1 |
|
|
T25 |
70135 |
|
T26 |
171 |
|
T31 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2943143 |
1 |
|
|
T25 |
31127 |
|
T26 |
89 |
|
T31 |
16 |
| auto[1] |
auto[0] |
auto[1] |
427545 |
1 |
|
|
T25 |
4678 |
|
T26 |
5 |
|
T1 |
1205 |
| auto[1] |
auto[1] |
auto[0] |
2918609 |
1 |
|
|
T25 |
30003 |
|
T26 |
75 |
|
T31 |
13 |
| auto[1] |
auto[1] |
auto[1] |
423876 |
1 |
|
|
T25 |
4327 |
|
T26 |
2 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |