Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8831856 |
1 |
|
|
T24 |
257 |
|
T25 |
71116 |
|
T26 |
98 |
| auto[1] |
6710387 |
1 |
|
|
T25 |
66866 |
|
T26 |
203 |
|
T31 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12870041 |
1 |
|
|
T24 |
257 |
|
T25 |
113275 |
|
T26 |
239 |
| auto[1] |
2672202 |
1 |
|
|
T25 |
24707 |
|
T26 |
62 |
|
T31 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8848125 |
1 |
|
|
T24 |
257 |
|
T25 |
69731 |
|
T26 |
158 |
| auto[1] |
6694118 |
1 |
|
|
T25 |
68251 |
|
T26 |
143 |
|
T31 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1998817 |
1 |
|
|
T25 |
22338 |
|
T26 |
37 |
|
T31 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1330327 |
1 |
|
|
T25 |
13057 |
|
T26 |
6 |
|
T21 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2023099 |
1 |
|
|
T25 |
21206 |
|
T26 |
44 |
|
T31 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1341875 |
1 |
|
|
T25 |
11650 |
|
T26 |
56 |
|
T31 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |