Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8819924 |
1 |
|
|
T24 |
257 |
|
T25 |
68397 |
|
T26 |
147 |
| auto[1] |
6722319 |
1 |
|
|
T25 |
69585 |
|
T26 |
154 |
|
T31 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12882164 |
1 |
|
|
T24 |
257 |
|
T25 |
113170 |
|
T26 |
244 |
| auto[1] |
2660079 |
1 |
|
|
T25 |
24812 |
|
T26 |
57 |
|
T31 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8864138 |
1 |
|
|
T24 |
257 |
|
T25 |
70120 |
|
T26 |
120 |
| auto[1] |
6678105 |
1 |
|
|
T25 |
67862 |
|
T26 |
181 |
|
T31 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2000180 |
1 |
|
|
T25 |
21544 |
|
T26 |
59 |
|
T31 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1326008 |
1 |
|
|
T25 |
12540 |
|
T26 |
22 |
|
T31 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2017846 |
1 |
|
|
T25 |
21506 |
|
T26 |
65 |
|
T31 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1334071 |
1 |
|
|
T25 |
12272 |
|
T26 |
35 |
|
T1 |
2982 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |