Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8848102 |
1 |
|
|
T24 |
257 |
|
T25 |
68514 |
|
T26 |
115 |
| auto[1] |
6694141 |
1 |
|
|
T25 |
69468 |
|
T26 |
186 |
|
T31 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12868594 |
1 |
|
|
T24 |
257 |
|
T25 |
112371 |
|
T26 |
220 |
| auto[1] |
2673649 |
1 |
|
|
T25 |
25611 |
|
T26 |
81 |
|
T31 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8838479 |
1 |
|
|
T24 |
257 |
|
T25 |
67752 |
|
T26 |
137 |
| auto[1] |
6703764 |
1 |
|
|
T25 |
70230 |
|
T26 |
164 |
|
T31 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2021033 |
1 |
|
|
T25 |
23561 |
|
T26 |
26 |
|
T31 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1340844 |
1 |
|
|
T25 |
13274 |
|
T26 |
34 |
|
T31 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2009082 |
1 |
|
|
T25 |
21058 |
|
T26 |
57 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1332805 |
1 |
|
|
T25 |
12337 |
|
T26 |
47 |
|
T31 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |