Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8830452 |
1 |
|
|
T24 |
257 |
|
T25 |
66993 |
|
T26 |
116 |
| auto[1] |
6711791 |
1 |
|
|
T25 |
70989 |
|
T26 |
185 |
|
T31 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12874319 |
1 |
|
|
T24 |
257 |
|
T25 |
113042 |
|
T26 |
195 |
| auto[1] |
2667924 |
1 |
|
|
T25 |
24940 |
|
T26 |
106 |
|
T31 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8832044 |
1 |
|
|
T24 |
257 |
|
T25 |
71269 |
|
T26 |
168 |
| auto[1] |
6710199 |
1 |
|
|
T25 |
66713 |
|
T26 |
133 |
|
T31 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2019549 |
1 |
|
|
T25 |
20244 |
|
T26 |
7 |
|
T31 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1331988 |
1 |
|
|
T25 |
11807 |
|
T26 |
35 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2022726 |
1 |
|
|
T25 |
21529 |
|
T26 |
20 |
|
T31 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1335936 |
1 |
|
|
T25 |
13133 |
|
T26 |
71 |
|
T31 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |