Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8866866 |
1 |
|
|
T24 |
257 |
|
T25 |
70813 |
|
T26 |
144 |
| auto[1] |
6675377 |
1 |
|
|
T25 |
67169 |
|
T26 |
157 |
|
T31 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2933203 |
1 |
|
|
T25 |
28784 |
|
T26 |
101 |
|
T31 |
17 |
| auto[1] |
auto[0] |
auto[1] |
427256 |
1 |
|
|
T25 |
4190 |
|
T26 |
7 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2895096 |
1 |
|
|
T25 |
29940 |
|
T26 |
46 |
|
T31 |
18 |
| auto[1] |
auto[1] |
auto[1] |
419822 |
1 |
|
|
T25 |
4255 |
|
T26 |
3 |
|
T1 |
1205 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |