Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8820643 |
1 |
|
|
T24 |
257 |
|
T25 |
72703 |
|
T26 |
204 |
| auto[1] |
6721600 |
1 |
|
|
T25 |
65279 |
|
T26 |
97 |
|
T31 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12875748 |
1 |
|
|
T24 |
257 |
|
T25 |
112151 |
|
T26 |
239 |
| auto[1] |
2666495 |
1 |
|
|
T25 |
25831 |
|
T26 |
62 |
|
T31 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8852451 |
1 |
|
|
T24 |
257 |
|
T25 |
67358 |
|
T26 |
158 |
| auto[1] |
6689792 |
1 |
|
|
T25 |
70624 |
|
T26 |
143 |
|
T31 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2012049 |
1 |
|
|
T25 |
23366 |
|
T26 |
59 |
|
T31 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1330377 |
1 |
|
|
T25 |
13330 |
|
T26 |
31 |
|
T31 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2011248 |
1 |
|
|
T25 |
21427 |
|
T26 |
22 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1336118 |
1 |
|
|
T25 |
12501 |
|
T26 |
31 |
|
T31 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |