Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8845005 |
1 |
|
|
T24 |
257 |
|
T25 |
73241 |
|
T26 |
147 |
| auto[1] |
6697238 |
1 |
|
|
T25 |
64741 |
|
T26 |
154 |
|
T31 |
61 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12864842 |
1 |
|
|
T24 |
257 |
|
T25 |
112881 |
|
T26 |
211 |
| auto[1] |
2677401 |
1 |
|
|
T25 |
25101 |
|
T26 |
90 |
|
T31 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8820874 |
1 |
|
|
T24 |
257 |
|
T25 |
69639 |
|
T26 |
179 |
| auto[1] |
6721369 |
1 |
|
|
T25 |
68343 |
|
T26 |
122 |
|
T31 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2029542 |
1 |
|
|
T25 |
23666 |
|
T26 |
24 |
|
T31 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1341488 |
1 |
|
|
T25 |
13579 |
|
T26 |
41 |
|
T31 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2014426 |
1 |
|
|
T25 |
19576 |
|
T26 |
8 |
|
T31 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1335913 |
1 |
|
|
T25 |
11522 |
|
T26 |
49 |
|
T31 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |