Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8850320 |
1 |
|
|
T24 |
257 |
|
T25 |
69539 |
|
T26 |
141 |
| auto[1] |
6691923 |
1 |
|
|
T25 |
68443 |
|
T26 |
160 |
|
T31 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12876395 |
1 |
|
|
T24 |
257 |
|
T25 |
112672 |
|
T26 |
186 |
| auto[1] |
2665848 |
1 |
|
|
T25 |
25310 |
|
T26 |
115 |
|
T31 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8846750 |
1 |
|
|
T24 |
257 |
|
T25 |
68413 |
|
T26 |
107 |
| auto[1] |
6695493 |
1 |
|
|
T25 |
69569 |
|
T26 |
194 |
|
T31 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2021853 |
1 |
|
|
T25 |
23820 |
|
T26 |
33 |
|
T31 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1336375 |
1 |
|
|
T25 |
13434 |
|
T26 |
63 |
|
T31 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2007792 |
1 |
|
|
T25 |
20439 |
|
T26 |
46 |
|
T31 |
14 |
| auto[1] |
auto[1] |
auto[1] |
1329473 |
1 |
|
|
T25 |
11876 |
|
T26 |
52 |
|
T31 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |