Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8841040 |
1 |
|
|
T24 |
257 |
|
T25 |
70539 |
|
T26 |
156 |
| auto[1] |
6701203 |
1 |
|
|
T25 |
67443 |
|
T26 |
145 |
|
T31 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12881759 |
1 |
|
|
T24 |
257 |
|
T25 |
113556 |
|
T26 |
205 |
| auto[1] |
2660484 |
1 |
|
|
T25 |
24426 |
|
T26 |
96 |
|
T31 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8871040 |
1 |
|
|
T24 |
257 |
|
T25 |
71123 |
|
T26 |
111 |
| auto[1] |
6671203 |
1 |
|
|
T25 |
66859 |
|
T26 |
190 |
|
T31 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2003091 |
1 |
|
|
T25 |
20380 |
|
T26 |
43 |
|
T31 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1329896 |
1 |
|
|
T25 |
12509 |
|
T26 |
70 |
|
T31 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2007628 |
1 |
|
|
T25 |
22053 |
|
T26 |
51 |
|
T31 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1330588 |
1 |
|
|
T25 |
11917 |
|
T26 |
26 |
|
T31 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |