Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8845345 |
1 |
|
|
T24 |
257 |
|
T25 |
68090 |
|
T26 |
144 |
| auto[1] |
6696898 |
1 |
|
|
T25 |
69892 |
|
T26 |
157 |
|
T31 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12880130 |
1 |
|
|
T24 |
257 |
|
T25 |
112601 |
|
T26 |
200 |
| auto[1] |
2662113 |
1 |
|
|
T25 |
25381 |
|
T26 |
101 |
|
T31 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8867200 |
1 |
|
|
T24 |
257 |
|
T25 |
69197 |
|
T26 |
131 |
| auto[1] |
6675043 |
1 |
|
|
T25 |
68785 |
|
T26 |
170 |
|
T31 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2004657 |
1 |
|
|
T25 |
20377 |
|
T26 |
32 |
|
T1 |
4502 |
| auto[1] |
auto[0] |
auto[1] |
1330909 |
1 |
|
|
T25 |
12215 |
|
T26 |
56 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2008273 |
1 |
|
|
T25 |
23027 |
|
T26 |
37 |
|
T21 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1331204 |
1 |
|
|
T25 |
13166 |
|
T26 |
45 |
|
T31 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |