Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8811202 |
1 |
|
|
T24 |
257 |
|
T25 |
71849 |
|
T26 |
120 |
| auto[1] |
6731041 |
1 |
|
|
T25 |
66133 |
|
T26 |
181 |
|
T31 |
61 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12871174 |
1 |
|
|
T24 |
257 |
|
T25 |
113557 |
|
T26 |
224 |
| auto[1] |
2671069 |
1 |
|
|
T25 |
24425 |
|
T26 |
77 |
|
T31 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8836516 |
1 |
|
|
T24 |
257 |
|
T25 |
71514 |
|
T26 |
189 |
| auto[1] |
6705727 |
1 |
|
|
T25 |
66468 |
|
T26 |
112 |
|
T31 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2003466 |
1 |
|
|
T25 |
22133 |
|
T26 |
22 |
|
T31 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1329583 |
1 |
|
|
T25 |
12401 |
|
T26 |
30 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2031192 |
1 |
|
|
T25 |
19910 |
|
T26 |
13 |
|
T31 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1341486 |
1 |
|
|
T25 |
12024 |
|
T26 |
47 |
|
T31 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |